arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7790-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7790";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &iic0;
  28                 i2c5 = &iic1;
  29                 i2c6 = &iic2;
  30                 i2c7 = &iic3;
  31                 spi0 = &qspi;
  32                 spi1 = &msiof0;
  33                 spi2 = &msiof1;
  34                 spi3 = &msiof2;
  35                 spi4 = &msiof3;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <0>;
  46                         clock-frequency = <1300000000>;
  47                         voltage-tolerance = <1>; /* 1% */
  48                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  49                         clock-latency = <300000>; /* 300 us */
  50
  51                         /* kHz - uV - OPPs unknown yet */
  52                         operating-points = <1400000 1000000>,
  53                                            <1225000 1000000>,
  54                                            <1050000 1000000>,
  55                                            < 875000 1000000>,
  56                                            < 700000 1000000>,
  57                                            < 350000 1000000>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <1>;
  64                         clock-frequency = <1300000000>;
  65                 };
  66
  67                 cpu2: cpu@2 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <2>;
  71                         clock-frequency = <1300000000>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <3>;
  78                         clock-frequency = <1300000000>;
  79                 };
  80
  81                 cpu4: cpu@4 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x100>;
  85                         clock-frequency = <780000000>;
  86                 };
  87
  88                 cpu5: cpu@5 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         reg = <0x101>;
  92                         clock-frequency = <780000000>;
  93                 };
  94
  95                 cpu6: cpu@6 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a7";
  98                         reg = <0x102>;
  99                         clock-frequency = <780000000>;
 100                 };
 101
 102                 cpu7: cpu@7 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a7";
 105                         reg = <0x103>;
 106                         clock-frequency = <780000000>;
 107                 };
 108         };
 109
 110         gic: interrupt-controller@f1001000 {
 111                 compatible = "arm,cortex-a15-gic";
 112                 #interrupt-cells = <3>;
 113                 #address-cells = <0>;
 114                 interrupt-controller;
 115                 reg = <0 0xf1001000 0 0x1000>,
 116                         <0 0xf1002000 0 0x1000>,
 117                         <0 0xf1004000 0 0x2000>,
 118                         <0 0xf1006000 0 0x2000>;
 119                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 120         };
 121
 122         gpio0: gpio@e6050000 {
 123                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 124                 reg = <0 0xe6050000 0 0x50>;
 125                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 0 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 132         };
 133
 134         gpio1: gpio@e6051000 {
 135                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 136                 reg = <0 0xe6051000 0 0x50>;
 137                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 32 32>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 144         };
 145
 146         gpio2: gpio@e6052000 {
 147                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 148                 reg = <0 0xe6052000 0 0x50>;
 149                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 150                 #gpio-cells = <2>;
 151                 gpio-controller;
 152                 gpio-ranges = <&pfc 0 64 32>;
 153                 #interrupt-cells = <2>;
 154                 interrupt-controller;
 155                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 156         };
 157
 158         gpio3: gpio@e6053000 {
 159                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 160                 reg = <0 0xe6053000 0 0x50>;
 161                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 162                 #gpio-cells = <2>;
 163                 gpio-controller;
 164                 gpio-ranges = <&pfc 0 96 32>;
 165                 #interrupt-cells = <2>;
 166                 interrupt-controller;
 167                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 168         };
 169
 170         gpio4: gpio@e6054000 {
 171                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 172                 reg = <0 0xe6054000 0 0x50>;
 173                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 174                 #gpio-cells = <2>;
 175                 gpio-controller;
 176                 gpio-ranges = <&pfc 0 128 32>;
 177                 #interrupt-cells = <2>;
 178                 interrupt-controller;
 179                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 180         };
 181
 182         gpio5: gpio@e6055000 {
 183                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 184                 reg = <0 0xe6055000 0 0x50>;
 185                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 186                 #gpio-cells = <2>;
 187                 gpio-controller;
 188                 gpio-ranges = <&pfc 0 160 32>;
 189                 #interrupt-cells = <2>;
 190                 interrupt-controller;
 191                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 192         };
 193
 194         thermal@e61f0000 {
 195                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 196                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 197                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 199         };
 200
 201         timer {
 202                 compatible = "arm,armv7-timer";
 203                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 204                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 205                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 206                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 207         };
 208
 209         irqc0: interrupt-controller@e61c0000 {
 210                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 211                 #interrupt-cells = <2>;
 212                 interrupt-controller;
 213                 reg = <0 0xe61c0000 0 0x200>;
 214                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 215                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 216                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 217                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 218         };
 219
 220         i2c0: i2c@e6508000 {
 221                 #address-cells = <1>;
 222                 #size-cells = <0>;
 223                 compatible = "renesas,i2c-r8a7790";
 224                 reg = <0 0xe6508000 0 0x40>;
 225                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 227                 status = "disabled";
 228         };
 229
 230         i2c1: i2c@e6518000 {
 231                 #address-cells = <1>;
 232                 #size-cells = <0>;
 233                 compatible = "renesas,i2c-r8a7790";
 234                 reg = <0 0xe6518000 0 0x40>;
 235                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 237                 status = "disabled";
 238         };
 239
 240         i2c2: i2c@e6530000 {
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 compatible = "renesas,i2c-r8a7790";
 244                 reg = <0 0xe6530000 0 0x40>;
 245                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 247                 status = "disabled";
 248         };
 249
 250         i2c3: i2c@e6540000 {
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 compatible = "renesas,i2c-r8a7790";
 254                 reg = <0 0xe6540000 0 0x40>;
 255                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 257                 status = "disabled";
 258         };
 259
 260         iic0: i2c@e6500000 {
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 264                 reg = <0 0xe6500000 0 0x425>;
 265                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 267                 status = "disabled";
 268         };
 269
 270         iic1: i2c@e6510000 {
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 274                 reg = <0 0xe6510000 0 0x425>;
 275                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 276                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 277                 status = "disabled";
 278         };
 279
 280         iic2: i2c@e6520000 {
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 284                 reg = <0 0xe6520000 0 0x425>;
 285                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 287                 status = "disabled";
 288         };
 289
 290         iic3: i2c@e60b0000 {
 291                 #address-cells = <1>;
 292                 #size-cells = <0>;
 293                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 294                 reg = <0 0xe60b0000 0 0x425>;
 295                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 296                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 297                 status = "disabled";
 298         };
 299
 300         mmcif0: mmcif@ee200000 {
 301                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 302                 reg = <0 0xee200000 0 0x80>;
 303                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 305                 reg-io-width = <4>;
 306                 status = "disabled";
 307         };
 308
 309         mmcif1: mmc@ee220000 {
 310                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 311                 reg = <0 0xee220000 0 0x80>;
 312                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 314                 reg-io-width = <4>;
 315                 status = "disabled";
 316         };
 317
 318         pfc: pfc@e6060000 {
 319                 compatible = "renesas,pfc-r8a7790";
 320                 reg = <0 0xe6060000 0 0x250>;
 321         };
 322
 323         sdhi0: sd@ee100000 {
 324                 compatible = "renesas,sdhi-r8a7790";
 325                 reg = <0 0xee100000 0 0x200>;
 326                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 328                 cap-sd-highspeed;
 329                 status = "disabled";
 330         };
 331
 332         sdhi1: sd@ee120000 {
 333                 compatible = "renesas,sdhi-r8a7790";
 334                 reg = <0 0xee120000 0 0x200>;
 335                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 337                 cap-sd-highspeed;
 338                 status = "disabled";
 339         };
 340
 341         sdhi2: sd@ee140000 {
 342                 compatible = "renesas,sdhi-r8a7790";
 343                 reg = <0 0xee140000 0 0x100>;
 344                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 346                 cap-sd-highspeed;
 347                 status = "disabled";
 348         };
 349
 350         sdhi3: sd@ee160000 {
 351                 compatible = "renesas,sdhi-r8a7790";
 352                 reg = <0 0xee160000 0 0x100>;
 353                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 355                 cap-sd-highspeed;
 356                 status = "disabled";
 357         };
 358
 359         scifa0: serial@e6c40000 {
 360                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 361                 reg = <0 0xe6c40000 0 64>;
 362                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 364                 clock-names = "sci_ick";
 365                 status = "disabled";
 366         };
 367
 368         scifa1: serial@e6c50000 {
 369                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 370                 reg = <0 0xe6c50000 0 64>;
 371                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 372                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 373                 clock-names = "sci_ick";
 374                 status = "disabled";
 375         };
 376
 377         scifa2: serial@e6c60000 {
 378                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 379                 reg = <0 0xe6c60000 0 64>;
 380                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 382                 clock-names = "sci_ick";
 383                 status = "disabled";
 384         };
 385
 386         scifb0: serial@e6c20000 {
 387                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 388                 reg = <0 0xe6c20000 0 64>;
 389                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 391                 clock-names = "sci_ick";
 392                 status = "disabled";
 393         };
 394
 395         scifb1: serial@e6c30000 {
 396                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 397                 reg = <0 0xe6c30000 0 64>;
 398                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 400                 clock-names = "sci_ick";
 401                 status = "disabled";
 402         };
 403
 404         scifb2: serial@e6ce0000 {
 405                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 406                 reg = <0 0xe6ce0000 0 64>;
 407                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 409                 clock-names = "sci_ick";
 410                 status = "disabled";
 411         };
 412
 413         scif0: serial@e6e60000 {
 414                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 415                 reg = <0 0xe6e60000 0 64>;
 416                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 417                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 418                 clock-names = "sci_ick";
 419                 status = "disabled";
 420         };
 421
 422         scif1: serial@e6e68000 {
 423                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 424                 reg = <0 0xe6e68000 0 64>;
 425                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 427                 clock-names = "sci_ick";
 428                 status = "disabled";
 429         };
 430
 431         hscif0: serial@e62c0000 {
 432                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 433                 reg = <0 0xe62c0000 0 96>;
 434                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 436                 clock-names = "sci_ick";
 437                 status = "disabled";
 438         };
 439
 440         hscif1: serial@e62c8000 {
 441                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 442                 reg = <0 0xe62c8000 0 96>;
 443                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 445                 clock-names = "sci_ick";
 446                 status = "disabled";
 447         };
 448
 449         ether: ethernet@ee700000 {
 450                 compatible = "renesas,ether-r8a7790";
 451                 reg = <0 0xee700000 0 0x400>;
 452                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 454                 phy-mode = "rmii";
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 status = "disabled";
 458         };
 459
 460         sata0: sata@ee300000 {
 461                 compatible = "renesas,sata-r8a7790";
 462                 reg = <0 0xee300000 0 0x2000>;
 463                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 465                 status = "disabled";
 466         };
 467
 468         sata1: sata@ee500000 {
 469                 compatible = "renesas,sata-r8a7790";
 470                 reg = <0 0xee500000 0 0x2000>;
 471                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 472                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 473                 status = "disabled";
 474         };
 475
 476         clocks {
 477                 #address-cells = <2>;
 478                 #size-cells = <2>;
 479                 ranges;
 480
 481                 /* External root clock */
 482                 extal_clk: extal_clk {
 483                         compatible = "fixed-clock";
 484                         #clock-cells = <0>;
 485                         /* This value must be overriden by the board. */
 486                         clock-frequency = <0>;
 487                         clock-output-names = "extal";
 488                 };
 489
 490                 /* External PCIe clock - can be overridden by the board */
 491                 pcie_bus_clk: pcie_bus_clk {
 492                         compatible = "fixed-clock";
 493                         #clock-cells = <0>;
 494                         clock-frequency = <100000000>;
 495                         clock-output-names = "pcie_bus";
 496                         status = "disabled";
 497                 };
 498
 499                 /*
 500                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 501                  * default. Boards that provide audio clocks should override them.
 502                  */
 503                 audio_clk_a: audio_clk_a {
 504                         compatible = "fixed-clock";
 505                         #clock-cells = <0>;
 506                         clock-frequency = <0>;
 507                         clock-output-names = "audio_clk_a";
 508                 };
 509                 audio_clk_b: audio_clk_b {
 510                         compatible = "fixed-clock";
 511                         #clock-cells = <0>;
 512                         clock-frequency = <0>;
 513                         clock-output-names = "audio_clk_b";
 514                 };
 515                 audio_clk_c: audio_clk_c {
 516                         compatible = "fixed-clock";
 517                         #clock-cells = <0>;
 518                         clock-frequency = <0>;
 519                         clock-output-names = "audio_clk_c";
 520                 };
 521
 522                 /* Special CPG clocks */
 523                 cpg_clocks: cpg_clocks@e6150000 {
 524                         compatible = "renesas,r8a7790-cpg-clocks",
 525                                      "renesas,rcar-gen2-cpg-clocks";
 526                         reg = <0 0xe6150000 0 0x1000>;
 527                         clocks = <&extal_clk>;
 528                         #clock-cells = <1>;
 529                         clock-output-names = "main", "pll0", "pll1", "pll3",
 530                                              "lb", "qspi", "sdh", "sd0", "sd1",
 531                                              "z";
 532                 };
 533
 534                 /* Variable factor clocks */
 535                 sd2_clk: sd2_clk@e6150078 {
 536                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 537                         reg = <0 0xe6150078 0 4>;
 538                         clocks = <&pll1_div2_clk>;
 539                         #clock-cells = <0>;
 540                         clock-output-names = "sd2";
 541                 };
 542                 sd3_clk: sd3_clk@e615007c {
 543                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 544                         reg = <0 0xe615007c 0 4>;
 545                         clocks = <&pll1_div2_clk>;
 546                         #clock-cells = <0>;
 547                         clock-output-names = "sd3";
 548                 };
 549                 mmc0_clk: mmc0_clk@e6150240 {
 550                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 551                         reg = <0 0xe6150240 0 4>;
 552                         clocks = <&pll1_div2_clk>;
 553                         #clock-cells = <0>;
 554                         clock-output-names = "mmc0";
 555                 };
 556                 mmc1_clk: mmc1_clk@e6150244 {
 557                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 558                         reg = <0 0xe6150244 0 4>;
 559                         clocks = <&pll1_div2_clk>;
 560                         #clock-cells = <0>;
 561                         clock-output-names = "mmc1";
 562                 };
 563                 ssp_clk: ssp_clk@e6150248 {
 564                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 565                         reg = <0 0xe6150248 0 4>;
 566                         clocks = <&pll1_div2_clk>;
 567                         #clock-cells = <0>;
 568                         clock-output-names = "ssp";
 569                 };
 570                 ssprs_clk: ssprs_clk@e615024c {
 571                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 572                         reg = <0 0xe615024c 0 4>;
 573                         clocks = <&pll1_div2_clk>;
 574                         #clock-cells = <0>;
 575                         clock-output-names = "ssprs";
 576                 };
 577
 578                 /* Fixed factor clocks */
 579                 pll1_div2_clk: pll1_div2_clk {
 580                         compatible = "fixed-factor-clock";
 581                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 582                         #clock-cells = <0>;
 583                         clock-div = <2>;
 584                         clock-mult = <1>;
 585                         clock-output-names = "pll1_div2";
 586                 };
 587                 z2_clk: z2_clk {
 588                         compatible = "fixed-factor-clock";
 589                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 590                         #clock-cells = <0>;
 591                         clock-div = <2>;
 592                         clock-mult = <1>;
 593                         clock-output-names = "z2";
 594                 };
 595                 zg_clk: zg_clk {
 596                         compatible = "fixed-factor-clock";
 597                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 598                         #clock-cells = <0>;
 599                         clock-div = <3>;
 600                         clock-mult = <1>;
 601                         clock-output-names = "zg";
 602                 };
 603                 zx_clk: zx_clk {
 604                         compatible = "fixed-factor-clock";
 605                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 606                         #clock-cells = <0>;
 607                         clock-div = <3>;
 608                         clock-mult = <1>;
 609                         clock-output-names = "zx";
 610                 };
 611                 zs_clk: zs_clk {
 612                         compatible = "fixed-factor-clock";
 613                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 614                         #clock-cells = <0>;
 615                         clock-div = <6>;
 616                         clock-mult = <1>;
 617                         clock-output-names = "zs";
 618                 };
 619                 hp_clk: hp_clk {
 620                         compatible = "fixed-factor-clock";
 621                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 622                         #clock-cells = <0>;
 623                         clock-div = <12>;
 624                         clock-mult = <1>;
 625                         clock-output-names = "hp";
 626                 };
 627                 i_clk: i_clk {
 628                         compatible = "fixed-factor-clock";
 629                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 630                         #clock-cells = <0>;
 631                         clock-div = <2>;
 632                         clock-mult = <1>;
 633                         clock-output-names = "i";
 634                 };
 635                 b_clk: b_clk {
 636                         compatible = "fixed-factor-clock";
 637                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 638                         #clock-cells = <0>;
 639                         clock-div = <12>;
 640                         clock-mult = <1>;
 641                         clock-output-names = "b";
 642                 };
 643                 p_clk: p_clk {
 644                         compatible = "fixed-factor-clock";
 645                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 646                         #clock-cells = <0>;
 647                         clock-div = <24>;
 648                         clock-mult = <1>;
 649                         clock-output-names = "p";
 650                 };
 651                 cl_clk: cl_clk {
 652                         compatible = "fixed-factor-clock";
 653                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 654                         #clock-cells = <0>;
 655                         clock-div = <48>;
 656                         clock-mult = <1>;
 657                         clock-output-names = "cl";
 658                 };
 659                 m2_clk: m2_clk {
 660                         compatible = "fixed-factor-clock";
 661                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 662                         #clock-cells = <0>;
 663                         clock-div = <8>;
 664                         clock-mult = <1>;
 665                         clock-output-names = "m2";
 666                 };
 667                 imp_clk: imp_clk {
 668                         compatible = "fixed-factor-clock";
 669                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 670                         #clock-cells = <0>;
 671                         clock-div = <4>;
 672                         clock-mult = <1>;
 673                         clock-output-names = "imp";
 674                 };
 675                 rclk_clk: rclk_clk {
 676                         compatible = "fixed-factor-clock";
 677                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 678                         #clock-cells = <0>;
 679                         clock-div = <(48 * 1024)>;
 680                         clock-mult = <1>;
 681                         clock-output-names = "rclk";
 682                 };
 683                 oscclk_clk: oscclk_clk {
 684                         compatible = "fixed-factor-clock";
 685                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 686                         #clock-cells = <0>;
 687                         clock-div = <(12 * 1024)>;
 688                         clock-mult = <1>;
 689                         clock-output-names = "oscclk";
 690                 };
 691                 zb3_clk: zb3_clk {
 692                         compatible = "fixed-factor-clock";
 693                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 694                         #clock-cells = <0>;
 695                         clock-div = <4>;
 696                         clock-mult = <1>;
 697                         clock-output-names = "zb3";
 698                 };
 699                 zb3d2_clk: zb3d2_clk {
 700                         compatible = "fixed-factor-clock";
 701                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 702                         #clock-cells = <0>;
 703                         clock-div = <8>;
 704                         clock-mult = <1>;
 705                         clock-output-names = "zb3d2";
 706                 };
 707                 ddr_clk: ddr_clk {
 708                         compatible = "fixed-factor-clock";
 709                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 710                         #clock-cells = <0>;
 711                         clock-div = <8>;
 712                         clock-mult = <1>;
 713                         clock-output-names = "ddr";
 714                 };
 715                 mp_clk: mp_clk {
 716                         compatible = "fixed-factor-clock";
 717                         clocks = <&pll1_div2_clk>;
 718                         #clock-cells = <0>;
 719                         clock-div = <15>;
 720                         clock-mult = <1>;
 721                         clock-output-names = "mp";
 722                 };
 723                 cp_clk: cp_clk {
 724                         compatible = "fixed-factor-clock";
 725                         clocks = <&extal_clk>;
 726                         #clock-cells = <0>;
 727                         clock-div = <2>;
 728                         clock-mult = <1>;
 729                         clock-output-names = "cp";
 730                 };
 731
 732                 /* Gate clocks */
 733                 mstp0_clks: mstp0_clks@e6150130 {
 734                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 735                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 736                         clocks = <&mp_clk>;
 737                         #clock-cells = <1>;
 738                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 739                         clock-output-names = "msiof0";
 740                 };
 741                 mstp1_clks: mstp1_clks@e6150134 {
 742                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 743                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 744                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 745                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 746                                  <&zs_clk>;
 747                         #clock-cells = <1>;
 748                         renesas,clock-indices = <
 749                                 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 750                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 751                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
 752                         >;
 753                         clock-output-names =
 754                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 755                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 756                 };
 757                 mstp2_clks: mstp2_clks@e6150138 {
 758                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 759                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 760                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 761                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
 762                         #clock-cells = <1>;
 763                         renesas,clock-indices = <
 764                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 765                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 766                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 767                         >;
 768                         clock-output-names =
 769                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 770                                 "scifb1", "msiof1", "msiof3", "scifb2";
 771                 };
 772                 mstp3_clks: mstp3_clks@e615013c {
 773                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 774                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 775                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
 776                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
 777                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 778                         #clock-cells = <1>;
 779                         renesas,clock-indices = <
 780                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 781                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
 782                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
 783                         >;
 784                         clock-output-names =
 785                                 "iic2", "tpu0", "mmcif1", "sdhi3",
 786                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 787                                 "iic0", "pciec", "iic1", "ssusb", "cmt1";
 788                 };
 789                 mstp5_clks: mstp5_clks@e6150144 {
 790                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 791                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 792                         clocks = <&extal_clk>, <&p_clk>;
 793                         #clock-cells = <1>;
 794                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 795                         clock-output-names = "thermal", "pwm";
 796                 };
 797                 mstp7_clks: mstp7_clks@e615014c {
 798                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 799                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 800                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 801                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 802                                  <&zx_clk>;
 803                         #clock-cells = <1>;
 804                         renesas,clock-indices = <
 805                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 806                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 807                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 808                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 809                         >;
 810                         clock-output-names =
 811                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 812                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 813                 };
 814                 mstp8_clks: mstp8_clks@e6150990 {
 815                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 816                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 817                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
 818                                  <&zs_clk>, <&zs_clk>;
 819                         #clock-cells = <1>;
 820                         renesas,clock-indices = <
 821                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 822                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
 823                                 R8A7790_CLK_SATA0
 824                         >;
 825                         clock-output-names =
 826                                 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 827                 };
 828                 mstp9_clks: mstp9_clks@e6150994 {
 829                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 830                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 831                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
 832                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
 833                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
 834                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 835                         #clock-cells = <1>;
 836                         renesas,clock-indices = <
 837                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
 838                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
 839                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
 840                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
 841                         >;
 842                         clock-output-names =
 843                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 844                                 "rcan1", "rcan0", "qspi_mod", "iic3",
 845                                 "i2c3", "i2c2", "i2c1", "i2c0";
 846                 };
 847                 mstp10_clks: mstp10_clks@e6150998 {
 848                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 849                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
 850                         clocks = <&p_clk>,
 851                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 852                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 853                                 <&p_clk>,
 854                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 855                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 856                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 857                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 858                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 859                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
 860
 861                         #clock-cells = <1>;
 862                         clock-indices = <
 863                                 R8A7790_CLK_SSI_ALL
 864                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
 865                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
 866                                 R8A7790_CLK_SCU_ALL
 867                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
 868                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
 869                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
 870                         >;
 871                         clock-output-names =
 872                                 "ssi-all",
 873                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
 874                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
 875                                 "scu-all",
 876                                 "scu-dvc1", "scu-dvc0",
 877                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
 878                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
 879                 };
 880         };
 881
 882         qspi: spi@e6b10000 {
 883                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
 884                 reg = <0 0xe6b10000 0 0x2c>;
 885                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 886                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 887                 num-cs = <1>;
 888                 #address-cells = <1>;
 889                 #size-cells = <0>;
 890                 status = "disabled";
 891         };
 892
 893         msiof0: spi@e6e20000 {
 894                 compatible = "renesas,msiof-r8a7790";
 895                 reg = <0 0xe6e20000 0 0x0064>;
 896                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 897                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
 898                 #address-cells = <1>;
 899                 #size-cells = <0>;
 900                 status = "disabled";
 901         };
 902
 903         msiof1: spi@e6e10000 {
 904                 compatible = "renesas,msiof-r8a7790";
 905                 reg = <0 0xe6e10000 0 0x0064>;
 906                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 907                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
 908                 #address-cells = <1>;
 909                 #size-cells = <0>;
 910                 status = "disabled";
 911         };
 912
 913         msiof2: spi@e6e00000 {
 914                 compatible = "renesas,msiof-r8a7790";
 915                 reg = <0 0xe6e00000 0 0x0064>;
 916                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 917                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
 918                 #address-cells = <1>;
 919                 #size-cells = <0>;
 920                 status = "disabled";
 921         };
 922
 923         msiof3: spi@e6c90000 {
 924                 compatible = "renesas,msiof-r8a7790";
 925                 reg = <0 0xe6c90000 0 0x0064>;
 926                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
 927                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
 928                 #address-cells = <1>;
 929                 #size-cells = <0>;
 930                 status = "disabled";
 931         };
 932
 933         pci0: pci@ee090000 {
 934                 compatible = "renesas,pci-r8a7790";
 935                 device_type = "pci";
 936                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
 937                 reg = <0 0xee090000 0 0xc00>,
 938                       <0 0xee080000 0 0x1100>;
 939                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 940                 status = "disabled";
 941
 942                 bus-range = <0 0>;
 943                 #address-cells = <3>;
 944                 #size-cells = <2>;
 945                 #interrupt-cells = <1>;
 946                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 947                 interrupt-map-mask = <0xff00 0 0 0x7>;
 948                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
 949                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
 950                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
 951         };
 952
 953         pci1: pci@ee0b0000 {
 954                 compatible = "renesas,pci-r8a7790";
 955                 device_type = "pci";
 956                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
 957                 reg = <0 0xee0b0000 0 0xc00>,
 958                       <0 0xee0a0000 0 0x1100>;
 959                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 960                 status = "disabled";
 961
 962                 bus-range = <1 1>;
 963                 #address-cells = <3>;
 964                 #size-cells = <2>;
 965                 #interrupt-cells = <1>;
 966                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
 967                 interrupt-map-mask = <0xff00 0 0 0x7>;
 968                 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
 969                                  0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
 970                                  0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
 971         };
 972
 973         pci2: pci@ee0d0000 {
 974                 compatible = "renesas,pci-r8a7790";
 975                 device_type = "pci";
 976                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
 977                 reg = <0 0xee0d0000 0 0xc00>,
 978                       <0 0xee0c0000 0 0x1100>;
 979                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 980                 status = "disabled";
 981
 982                 bus-range = <2 2>;
 983                 #address-cells = <3>;
 984                 #size-cells = <2>;
 985                 #interrupt-cells = <1>;
 986                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 987                 interrupt-map-mask = <0xff00 0 0 0x7>;
 988                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
 989                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
 990                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
 991         };
 992
 993         pciec: pcie@fe000000 {
 994                 compatible = "renesas,pcie-r8a7790";
 995                 reg = <0 0xfe000000 0 0x80000>;
 996                 #address-cells = <3>;
 997                 #size-cells = <2>;
 998                 bus-range = <0x00 0xff>;
 999                 device_type = "pci";
1000                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1001                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1002                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1003                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1004                 /* Map all possible DDR as inbound ranges */
1005                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1006                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1007                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1008                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1009                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1010                 #interrupt-cells = <1>;
1011                 interrupt-map-mask = <0 0 0 0>;
1012                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1013                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1014                 clock-names = "pcie", "pcie_bus";
1015                 status = "disabled";
1016         };
1017
1018         rcar_sound: rcar_sound@0xec500000 {
1019                 #sound-dai-cells = <1>;
1020                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1021                 interrupt-parent = <&gic>;
1022                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1023                         <0 0xec5a0000 0 0x100>,  /* ADG */
1024                         <0 0xec540000 0 0x1000>, /* SSIU */
1025                         <0 0xec541000 0 0x1280>; /* SSI */
1026                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1027                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1028                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1029                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1030                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1031                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1032                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1033                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1034                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1035                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1036                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1037                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1038                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1039                 clock-names = "ssi-all",
1040                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1041                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1042                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1043                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1044                                 "dvc.0", "dvc.1",
1045                                 "clk_a", "clk_b", "clk_c", "clk_i";
1046
1047                 status = "disabled";
1048
1049                 rcar_sound,dvc {
1050                         dvc0: dvc@0 { };
1051                         dvc1: dvc@1 { };
1052                 };
1053
1054                 rcar_sound,src {
1055                         src0: src@0 { };
1056                         src1: src@1 { };
1057                         src2: src@2 { };
1058                         src3: src@3 { };
1059                         src4: src@4 { };
1060                         src5: src@5 { };
1061                         src6: src@6 { };
1062                         src7: src@7 { };
1063                         src8: src@8 { };
1064                         src9: src@9 { };
1065                 };
1066
1067                 rcar_sound,ssi {
1068                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1069                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1070                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1071                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1072                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1073                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1074                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1075                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1076                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1077                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1078                 };
1079         };
1080 };