2 * Device Tree Source for the r8a7790 SoC
4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7790-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7790";
18 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a15";
46 clock-frequency = <1300000000>;
47 voltage-tolerance = <1>; /* 1% */
48 clocks = <&cpg_clocks R8A7790_CLK_Z>;
49 clock-latency = <300000>; /* 300 us */
51 /* kHz - uV - OPPs unknown yet */
52 operating-points = <1400000 1000000>,
62 compatible = "arm,cortex-a15";
64 clock-frequency = <1300000000>;
69 compatible = "arm,cortex-a15";
71 clock-frequency = <1300000000>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1300000000>;
83 compatible = "arm,cortex-a7";
85 clock-frequency = <780000000>;
90 compatible = "arm,cortex-a7";
92 clock-frequency = <780000000>;
97 compatible = "arm,cortex-a7";
99 clock-frequency = <780000000>;
104 compatible = "arm,cortex-a7";
106 clock-frequency = <780000000>;
110 gic: interrupt-controller@f1001000 {
111 compatible = "arm,cortex-a15-gic";
112 #interrupt-cells = <3>;
113 #address-cells = <0>;
114 interrupt-controller;
115 reg = <0 0xf1001000 0 0x1000>,
116 <0 0xf1002000 0 0x1000>,
117 <0 0xf1004000 0 0x2000>,
118 <0 0xf1006000 0 0x2000>;
119 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
122 gpio0: gpio@e6050000 {
123 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
124 reg = <0 0xe6050000 0 0x50>;
125 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
128 gpio-ranges = <&pfc 0 0 32>;
129 #interrupt-cells = <2>;
130 interrupt-controller;
131 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
134 gpio1: gpio@e6051000 {
135 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
136 reg = <0 0xe6051000 0 0x50>;
137 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
140 gpio-ranges = <&pfc 0 32 32>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
143 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
146 gpio2: gpio@e6052000 {
147 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
148 reg = <0 0xe6052000 0 0x50>;
149 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
152 gpio-ranges = <&pfc 0 64 32>;
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
158 gpio3: gpio@e6053000 {
159 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
160 reg = <0 0xe6053000 0 0x50>;
161 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
164 gpio-ranges = <&pfc 0 96 32>;
165 #interrupt-cells = <2>;
166 interrupt-controller;
167 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
170 gpio4: gpio@e6054000 {
171 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
172 reg = <0 0xe6054000 0 0x50>;
173 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pfc 0 128 32>;
177 #interrupt-cells = <2>;
178 interrupt-controller;
179 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
182 gpio5: gpio@e6055000 {
183 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
184 reg = <0 0xe6055000 0 0x50>;
185 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
188 gpio-ranges = <&pfc 0 160 32>;
189 #interrupt-cells = <2>;
190 interrupt-controller;
191 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
195 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
196 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
197 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
202 compatible = "arm,armv7-timer";
203 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
204 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
205 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
206 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
209 irqc0: interrupt-controller@e61c0000 {
210 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
211 #interrupt-cells = <2>;
212 interrupt-controller;
213 reg = <0 0xe61c0000 0 0x200>;
214 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
215 <0 1 IRQ_TYPE_LEVEL_HIGH>,
216 <0 2 IRQ_TYPE_LEVEL_HIGH>,
217 <0 3 IRQ_TYPE_LEVEL_HIGH>;
221 #address-cells = <1>;
223 compatible = "renesas,i2c-r8a7790";
224 reg = <0 0xe6508000 0 0x40>;
225 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
231 #address-cells = <1>;
233 compatible = "renesas,i2c-r8a7790";
234 reg = <0 0xe6518000 0 0x40>;
235 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
241 #address-cells = <1>;
243 compatible = "renesas,i2c-r8a7790";
244 reg = <0 0xe6530000 0 0x40>;
245 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
251 #address-cells = <1>;
253 compatible = "renesas,i2c-r8a7790";
254 reg = <0 0xe6540000 0 0x40>;
255 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
261 #address-cells = <1>;
263 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
264 reg = <0 0xe6500000 0 0x425>;
265 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
271 #address-cells = <1>;
273 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
274 reg = <0 0xe6510000 0 0x425>;
275 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
281 #address-cells = <1>;
283 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
284 reg = <0 0xe6520000 0 0x425>;
285 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
291 #address-cells = <1>;
293 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
294 reg = <0 0xe60b0000 0 0x425>;
295 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
300 mmcif0: mmcif@ee200000 {
301 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
302 reg = <0 0xee200000 0 0x80>;
303 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
309 mmcif1: mmc@ee220000 {
310 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
311 reg = <0 0xee220000 0 0x80>;
312 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
319 compatible = "renesas,pfc-r8a7790";
320 reg = <0 0xe6060000 0 0x250>;
324 compatible = "renesas,sdhi-r8a7790";
325 reg = <0 0xee100000 0 0x200>;
326 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
333 compatible = "renesas,sdhi-r8a7790";
334 reg = <0 0xee120000 0 0x200>;
335 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
342 compatible = "renesas,sdhi-r8a7790";
343 reg = <0 0xee140000 0 0x100>;
344 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
351 compatible = "renesas,sdhi-r8a7790";
352 reg = <0 0xee160000 0 0x100>;
353 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
359 scifa0: serial@e6c40000 {
360 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
361 reg = <0 0xe6c40000 0 64>;
362 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
364 clock-names = "sci_ick";
368 scifa1: serial@e6c50000 {
369 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
370 reg = <0 0xe6c50000 0 64>;
371 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
373 clock-names = "sci_ick";
377 scifa2: serial@e6c60000 {
378 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
379 reg = <0 0xe6c60000 0 64>;
380 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
382 clock-names = "sci_ick";
386 scifb0: serial@e6c20000 {
387 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
388 reg = <0 0xe6c20000 0 64>;
389 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
391 clock-names = "sci_ick";
395 scifb1: serial@e6c30000 {
396 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
397 reg = <0 0xe6c30000 0 64>;
398 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
400 clock-names = "sci_ick";
404 scifb2: serial@e6ce0000 {
405 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
406 reg = <0 0xe6ce0000 0 64>;
407 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
409 clock-names = "sci_ick";
413 scif0: serial@e6e60000 {
414 compatible = "renesas,scif-r8a7790", "renesas,scif";
415 reg = <0 0xe6e60000 0 64>;
416 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
418 clock-names = "sci_ick";
422 scif1: serial@e6e68000 {
423 compatible = "renesas,scif-r8a7790", "renesas,scif";
424 reg = <0 0xe6e68000 0 64>;
425 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
427 clock-names = "sci_ick";
431 hscif0: serial@e62c0000 {
432 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
433 reg = <0 0xe62c0000 0 96>;
434 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
436 clock-names = "sci_ick";
440 hscif1: serial@e62c8000 {
441 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
442 reg = <0 0xe62c8000 0 96>;
443 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
445 clock-names = "sci_ick";
449 ether: ethernet@ee700000 {
450 compatible = "renesas,ether-r8a7790";
451 reg = <0 0xee700000 0 0x400>;
452 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
455 #address-cells = <1>;
460 sata0: sata@ee300000 {
461 compatible = "renesas,sata-r8a7790";
462 reg = <0 0xee300000 0 0x2000>;
463 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
468 sata1: sata@ee500000 {
469 compatible = "renesas,sata-r8a7790";
470 reg = <0 0xee500000 0 0x2000>;
471 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
477 #address-cells = <2>;
481 /* External root clock */
482 extal_clk: extal_clk {
483 compatible = "fixed-clock";
485 /* This value must be overriden by the board. */
486 clock-frequency = <0>;
487 clock-output-names = "extal";
490 /* External PCIe clock - can be overridden by the board */
491 pcie_bus_clk: pcie_bus_clk {
492 compatible = "fixed-clock";
494 clock-frequency = <100000000>;
495 clock-output-names = "pcie_bus";
500 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
501 * default. Boards that provide audio clocks should override them.
503 audio_clk_a: audio_clk_a {
504 compatible = "fixed-clock";
506 clock-frequency = <0>;
507 clock-output-names = "audio_clk_a";
509 audio_clk_b: audio_clk_b {
510 compatible = "fixed-clock";
512 clock-frequency = <0>;
513 clock-output-names = "audio_clk_b";
515 audio_clk_c: audio_clk_c {
516 compatible = "fixed-clock";
518 clock-frequency = <0>;
519 clock-output-names = "audio_clk_c";
522 /* Special CPG clocks */
523 cpg_clocks: cpg_clocks@e6150000 {
524 compatible = "renesas,r8a7790-cpg-clocks",
525 "renesas,rcar-gen2-cpg-clocks";
526 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>;
529 clock-output-names = "main", "pll0", "pll1", "pll3",
530 "lb", "qspi", "sdh", "sd0", "sd1",
534 /* Variable factor clocks */
535 sd2_clk: sd2_clk@e6150078 {
536 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
537 reg = <0 0xe6150078 0 4>;
538 clocks = <&pll1_div2_clk>;
540 clock-output-names = "sd2";
542 sd3_clk: sd3_clk@e615007c {
543 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
544 reg = <0 0xe615007c 0 4>;
545 clocks = <&pll1_div2_clk>;
547 clock-output-names = "sd3";
549 mmc0_clk: mmc0_clk@e6150240 {
550 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
551 reg = <0 0xe6150240 0 4>;
552 clocks = <&pll1_div2_clk>;
554 clock-output-names = "mmc0";
556 mmc1_clk: mmc1_clk@e6150244 {
557 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
558 reg = <0 0xe6150244 0 4>;
559 clocks = <&pll1_div2_clk>;
561 clock-output-names = "mmc1";
563 ssp_clk: ssp_clk@e6150248 {
564 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
565 reg = <0 0xe6150248 0 4>;
566 clocks = <&pll1_div2_clk>;
568 clock-output-names = "ssp";
570 ssprs_clk: ssprs_clk@e615024c {
571 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
572 reg = <0 0xe615024c 0 4>;
573 clocks = <&pll1_div2_clk>;
575 clock-output-names = "ssprs";
578 /* Fixed factor clocks */
579 pll1_div2_clk: pll1_div2_clk {
580 compatible = "fixed-factor-clock";
581 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
585 clock-output-names = "pll1_div2";
588 compatible = "fixed-factor-clock";
589 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
593 clock-output-names = "z2";
596 compatible = "fixed-factor-clock";
597 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
601 clock-output-names = "zg";
604 compatible = "fixed-factor-clock";
605 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
609 clock-output-names = "zx";
612 compatible = "fixed-factor-clock";
613 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
617 clock-output-names = "zs";
620 compatible = "fixed-factor-clock";
621 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
625 clock-output-names = "hp";
628 compatible = "fixed-factor-clock";
629 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
633 clock-output-names = "i";
636 compatible = "fixed-factor-clock";
637 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
641 clock-output-names = "b";
644 compatible = "fixed-factor-clock";
645 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
649 clock-output-names = "p";
652 compatible = "fixed-factor-clock";
653 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
657 clock-output-names = "cl";
660 compatible = "fixed-factor-clock";
661 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
665 clock-output-names = "m2";
668 compatible = "fixed-factor-clock";
669 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
673 clock-output-names = "imp";
676 compatible = "fixed-factor-clock";
677 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
679 clock-div = <(48 * 1024)>;
681 clock-output-names = "rclk";
683 oscclk_clk: oscclk_clk {
684 compatible = "fixed-factor-clock";
685 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
687 clock-div = <(12 * 1024)>;
689 clock-output-names = "oscclk";
692 compatible = "fixed-factor-clock";
693 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
697 clock-output-names = "zb3";
699 zb3d2_clk: zb3d2_clk {
700 compatible = "fixed-factor-clock";
701 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
705 clock-output-names = "zb3d2";
708 compatible = "fixed-factor-clock";
709 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
713 clock-output-names = "ddr";
716 compatible = "fixed-factor-clock";
717 clocks = <&pll1_div2_clk>;
721 clock-output-names = "mp";
724 compatible = "fixed-factor-clock";
725 clocks = <&extal_clk>;
729 clock-output-names = "cp";
733 mstp0_clks: mstp0_clks@e6150130 {
734 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
735 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
738 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
739 clock-output-names = "msiof0";
741 mstp1_clks: mstp1_clks@e6150134 {
742 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
743 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
744 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
745 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
748 renesas,clock-indices = <
749 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
750 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
751 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
754 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
755 "vsp1-du0", "vsp1-rt", "vsp1-sy";
757 mstp2_clks: mstp2_clks@e6150138 {
758 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
759 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
760 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
761 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
763 renesas,clock-indices = <
764 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
765 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
766 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
769 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
770 "scifb1", "msiof1", "msiof3", "scifb2";
772 mstp3_clks: mstp3_clks@e615013c {
773 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
774 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
775 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
776 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
777 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
779 renesas,clock-indices = <
780 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
781 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
782 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
785 "iic2", "tpu0", "mmcif1", "sdhi3",
786 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
787 "iic0", "pciec", "iic1", "ssusb", "cmt1";
789 mstp5_clks: mstp5_clks@e6150144 {
790 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
791 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
792 clocks = <&extal_clk>, <&p_clk>;
794 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
795 clock-output-names = "thermal", "pwm";
797 mstp7_clks: mstp7_clks@e615014c {
798 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
799 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
800 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
801 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
804 renesas,clock-indices = <
805 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
806 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
807 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
808 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
811 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
812 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
814 mstp8_clks: mstp8_clks@e6150990 {
815 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
816 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
817 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
818 <&zs_clk>, <&zs_clk>;
820 renesas,clock-indices = <
821 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
822 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
826 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
828 mstp9_clks: mstp9_clks@e6150994 {
829 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
830 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
831 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
832 <&cp_clk>, <&cp_clk>, <&cp_clk>,
833 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
834 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
836 renesas,clock-indices = <
837 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
838 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
839 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
840 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
843 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
844 "rcan1", "rcan0", "qspi_mod", "iic3",
845 "i2c3", "i2c2", "i2c1", "i2c0";
847 mstp10_clks: mstp10_clks@e6150998 {
848 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
849 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
851 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
852 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
854 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
855 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
856 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
857 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
858 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
859 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
864 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
865 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
867 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
868 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
869 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
873 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
874 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
876 "scu-dvc1", "scu-dvc0",
877 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
878 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
883 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
884 reg = <0 0xe6b10000 0 0x2c>;
885 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
888 #address-cells = <1>;
893 msiof0: spi@e6e20000 {
894 compatible = "renesas,msiof-r8a7790";
895 reg = <0 0xe6e20000 0 0x0064>;
896 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
898 #address-cells = <1>;
903 msiof1: spi@e6e10000 {
904 compatible = "renesas,msiof-r8a7790";
905 reg = <0 0xe6e10000 0 0x0064>;
906 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
908 #address-cells = <1>;
913 msiof2: spi@e6e00000 {
914 compatible = "renesas,msiof-r8a7790";
915 reg = <0 0xe6e00000 0 0x0064>;
916 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
918 #address-cells = <1>;
923 msiof3: spi@e6c90000 {
924 compatible = "renesas,msiof-r8a7790";
925 reg = <0 0xe6c90000 0 0x0064>;
926 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
928 #address-cells = <1>;
933 pciec: pcie@fe000000 {
934 compatible = "renesas,pcie-r8a7790";
935 reg = <0 0xfe000000 0 0x80000>;
936 #address-cells = <3>;
938 bus-range = <0x00 0xff>;
940 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
941 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
942 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
943 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
944 /* Map all possible DDR as inbound ranges */
945 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
946 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
947 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
948 <0 117 IRQ_TYPE_LEVEL_HIGH>,
949 <0 118 IRQ_TYPE_LEVEL_HIGH>;
950 #interrupt-cells = <1>;
951 interrupt-map-mask = <0 0 0 0>;
952 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
954 clock-names = "pcie", "pcie_bus";
958 rcar_sound: rcar_sound@0xec500000 {
959 #sound-dai-cells = <1>;
960 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
961 interrupt-parent = <&gic>;
962 reg = <0 0xec500000 0 0x1000>, /* SCU */
963 <0 0xec5a0000 0 0x100>, /* ADG */
964 <0 0xec540000 0 0x1000>, /* SSIU */
965 <0 0xec541000 0 0x1280>; /* SSI */
966 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
967 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
968 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
969 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
970 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
971 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
972 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
973 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
974 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
975 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
976 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
977 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
978 clock-names = "ssi-all",
979 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
980 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
981 "src.9", "src.8", "src.7", "src.6", "src.5",
982 "src.4", "src.3", "src.2", "src.1", "src.0",
983 "clk_a", "clk_b", "clk_c", "clk_i";
1001 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1002 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1003 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1004 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1005 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1006 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1007 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1008 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1009 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1010 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };