arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7790-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7790";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &iic0;
  28                 i2c5 = &iic1;
  29                 i2c6 = &iic2;
  30                 i2c7 = &iic3;
  31                 spi0 = &qspi;
  32                 spi1 = &msiof0;
  33                 spi2 = &msiof1;
  34                 spi3 = &msiof2;
  35                 spi4 = &msiof3;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <0>;
  46                         clock-frequency = <1300000000>;
  47                         voltage-tolerance = <1>; /* 1% */
  48                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  49                         clock-latency = <300000>; /* 300 us */
  50
  51                         /* kHz - uV - OPPs unknown yet */
  52                         operating-points = <1400000 1000000>,
  53                                            <1225000 1000000>,
  54                                            <1050000 1000000>,
  55                                            < 875000 1000000>,
  56                                            < 700000 1000000>,
  57                                            < 350000 1000000>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <1>;
  64                         clock-frequency = <1300000000>;
  65                 };
  66
  67                 cpu2: cpu@2 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <2>;
  71                         clock-frequency = <1300000000>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <3>;
  78                         clock-frequency = <1300000000>;
  79                 };
  80
  81                 cpu4: cpu@4 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x100>;
  85                         clock-frequency = <780000000>;
  86                 };
  87
  88                 cpu5: cpu@5 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         reg = <0x101>;
  92                         clock-frequency = <780000000>;
  93                 };
  94
  95                 cpu6: cpu@6 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a7";
  98                         reg = <0x102>;
  99                         clock-frequency = <780000000>;
 100                 };
 101
 102                 cpu7: cpu@7 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a7";
 105                         reg = <0x103>;
 106                         clock-frequency = <780000000>;
 107                 };
 108         };
 109
 110         gic: interrupt-controller@f1001000 {
 111                 compatible = "arm,cortex-a15-gic";
 112                 #interrupt-cells = <3>;
 113                 #address-cells = <0>;
 114                 interrupt-controller;
 115                 reg = <0 0xf1001000 0 0x1000>,
 116                         <0 0xf1002000 0 0x1000>,
 117                         <0 0xf1004000 0 0x2000>,
 118                         <0 0xf1006000 0 0x2000>;
 119                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 120         };
 121
 122         gpio0: gpio@e6050000 {
 123                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 124                 reg = <0 0xe6050000 0 0x50>;
 125                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 0 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 132         };
 133
 134         gpio1: gpio@e6051000 {
 135                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 136                 reg = <0 0xe6051000 0 0x50>;
 137                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 32 32>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 144         };
 145
 146         gpio2: gpio@e6052000 {
 147                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 148                 reg = <0 0xe6052000 0 0x50>;
 149                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 150                 #gpio-cells = <2>;
 151                 gpio-controller;
 152                 gpio-ranges = <&pfc 0 64 32>;
 153                 #interrupt-cells = <2>;
 154                 interrupt-controller;
 155                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 156         };
 157
 158         gpio3: gpio@e6053000 {
 159                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 160                 reg = <0 0xe6053000 0 0x50>;
 161                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 162                 #gpio-cells = <2>;
 163                 gpio-controller;
 164                 gpio-ranges = <&pfc 0 96 32>;
 165                 #interrupt-cells = <2>;
 166                 interrupt-controller;
 167                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 168         };
 169
 170         gpio4: gpio@e6054000 {
 171                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 172                 reg = <0 0xe6054000 0 0x50>;
 173                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 174                 #gpio-cells = <2>;
 175                 gpio-controller;
 176                 gpio-ranges = <&pfc 0 128 32>;
 177                 #interrupt-cells = <2>;
 178                 interrupt-controller;
 179                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 180         };
 181
 182         gpio5: gpio@e6055000 {
 183                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 184                 reg = <0 0xe6055000 0 0x50>;
 185                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 186                 #gpio-cells = <2>;
 187                 gpio-controller;
 188                 gpio-ranges = <&pfc 0 160 32>;
 189                 #interrupt-cells = <2>;
 190                 interrupt-controller;
 191                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 192         };
 193
 194         thermal@e61f0000 {
 195                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 196                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 197                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 199         };
 200
 201         timer {
 202                 compatible = "arm,armv7-timer";
 203                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 204                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 205                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 206                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 207         };
 208
 209         cmt0: timer@ffca0000 {
 210                 compatible = "renesas,cmt-48-gen2";
 211                 reg = <0 0xffca0000 0 0x1004>;
 212                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 213                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 215                 clock-names = "fck";
 216
 217                 renesas,channels-mask = <0x60>;
 218
 219                 status = "disabled";
 220         };
 221
 222         cmt1: timer@e6130000 {
 223                 compatible = "renesas,cmt-48-gen2";
 224                 reg = <0 0xe6130000 0 0x1004>;
 225                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 226                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 227                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 228                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 229                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 230                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 231                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 232                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 234                 clock-names = "fck";
 235
 236                 renesas,channels-mask = <0xff>;
 237
 238                 status = "disabled";
 239         };
 240
 241         irqc0: interrupt-controller@e61c0000 {
 242                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 243                 #interrupt-cells = <2>;
 244                 interrupt-controller;
 245                 reg = <0 0xe61c0000 0 0x200>;
 246                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 247                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 248                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 249                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 250         };
 251
 252         dmac0: dma-controller@e6700000 {
 253                 compatible = "renesas,rcar-dmac";
 254                 reg = <0 0xe6700000 0 0x20000>;
 255                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 256                               0 200 IRQ_TYPE_LEVEL_HIGH
 257                               0 201 IRQ_TYPE_LEVEL_HIGH
 258                               0 202 IRQ_TYPE_LEVEL_HIGH
 259                               0 203 IRQ_TYPE_LEVEL_HIGH
 260                               0 204 IRQ_TYPE_LEVEL_HIGH
 261                               0 205 IRQ_TYPE_LEVEL_HIGH
 262                               0 206 IRQ_TYPE_LEVEL_HIGH
 263                               0 207 IRQ_TYPE_LEVEL_HIGH
 264                               0 208 IRQ_TYPE_LEVEL_HIGH
 265                               0 209 IRQ_TYPE_LEVEL_HIGH
 266                               0 210 IRQ_TYPE_LEVEL_HIGH
 267                               0 211 IRQ_TYPE_LEVEL_HIGH
 268                               0 212 IRQ_TYPE_LEVEL_HIGH
 269                               0 213 IRQ_TYPE_LEVEL_HIGH
 270                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 271                 interrupt-names = "error",
 272                                 "ch0", "ch1", "ch2", "ch3",
 273                                 "ch4", "ch5", "ch6", "ch7",
 274                                 "ch8", "ch9", "ch10", "ch11",
 275                                 "ch12", "ch13", "ch14";
 276                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 277                 clock-names = "fck";
 278                 #dma-cells = <1>;
 279                 dma-channels = <15>;
 280         };
 281
 282         dmac1: dma-controller@e6720000 {
 283                 compatible = "renesas,rcar-dmac";
 284                 reg = <0 0xe6720000 0 0x20000>;
 285                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 286                               0 216 IRQ_TYPE_LEVEL_HIGH
 287                               0 217 IRQ_TYPE_LEVEL_HIGH
 288                               0 218 IRQ_TYPE_LEVEL_HIGH
 289                               0 219 IRQ_TYPE_LEVEL_HIGH
 290                               0 308 IRQ_TYPE_LEVEL_HIGH
 291                               0 309 IRQ_TYPE_LEVEL_HIGH
 292                               0 310 IRQ_TYPE_LEVEL_HIGH
 293                               0 311 IRQ_TYPE_LEVEL_HIGH
 294                               0 312 IRQ_TYPE_LEVEL_HIGH
 295                               0 313 IRQ_TYPE_LEVEL_HIGH
 296                               0 314 IRQ_TYPE_LEVEL_HIGH
 297                               0 315 IRQ_TYPE_LEVEL_HIGH
 298                               0 316 IRQ_TYPE_LEVEL_HIGH
 299                               0 317 IRQ_TYPE_LEVEL_HIGH
 300                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 301                 interrupt-names = "error",
 302                                 "ch0", "ch1", "ch2", "ch3",
 303                                 "ch4", "ch5", "ch6", "ch7",
 304                                 "ch8", "ch9", "ch10", "ch11",
 305                                 "ch12", "ch13", "ch14";
 306                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 307                 clock-names = "fck";
 308                 #dma-cells = <1>;
 309                 dma-channels = <15>;
 310         };
 311         i2c0: i2c@e6508000 {
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 compatible = "renesas,i2c-r8a7790";
 315                 reg = <0 0xe6508000 0 0x40>;
 316                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 318                 status = "disabled";
 319         };
 320
 321         i2c1: i2c@e6518000 {
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 compatible = "renesas,i2c-r8a7790";
 325                 reg = <0 0xe6518000 0 0x40>;
 326                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 328                 status = "disabled";
 329         };
 330
 331         i2c2: i2c@e6530000 {
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 compatible = "renesas,i2c-r8a7790";
 335                 reg = <0 0xe6530000 0 0x40>;
 336                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 337                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 338                 status = "disabled";
 339         };
 340
 341         i2c3: i2c@e6540000 {
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 compatible = "renesas,i2c-r8a7790";
 345                 reg = <0 0xe6540000 0 0x40>;
 346                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 348                 status = "disabled";
 349         };
 350
 351         iic0: i2c@e6500000 {
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 355                 reg = <0 0xe6500000 0 0x425>;
 356                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 357                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 358                 status = "disabled";
 359         };
 360
 361         iic1: i2c@e6510000 {
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 365                 reg = <0 0xe6510000 0 0x425>;
 366                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 368                 status = "disabled";
 369         };
 370
 371         iic2: i2c@e6520000 {
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 375                 reg = <0 0xe6520000 0 0x425>;
 376                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 378                 status = "disabled";
 379         };
 380
 381         iic3: i2c@e60b0000 {
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 385                 reg = <0 0xe60b0000 0 0x425>;
 386                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 388                 status = "disabled";
 389         };
 390
 391         mmcif0: mmcif@ee200000 {
 392                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 393                 reg = <0 0xee200000 0 0x80>;
 394                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 396                 reg-io-width = <4>;
 397                 status = "disabled";
 398         };
 399
 400         mmcif1: mmc@ee220000 {
 401                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 402                 reg = <0 0xee220000 0 0x80>;
 403                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 405                 reg-io-width = <4>;
 406                 status = "disabled";
 407         };
 408
 409         pfc: pfc@e6060000 {
 410                 compatible = "renesas,pfc-r8a7790";
 411                 reg = <0 0xe6060000 0 0x250>;
 412         };
 413
 414         sdhi0: sd@ee100000 {
 415                 compatible = "renesas,sdhi-r8a7790";
 416                 reg = <0 0xee100000 0 0x200>;
 417                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 418                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 419                 cap-sd-highspeed;
 420                 status = "disabled";
 421         };
 422
 423         sdhi1: sd@ee120000 {
 424                 compatible = "renesas,sdhi-r8a7790";
 425                 reg = <0 0xee120000 0 0x200>;
 426                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 428                 cap-sd-highspeed;
 429                 status = "disabled";
 430         };
 431
 432         sdhi2: sd@ee140000 {
 433                 compatible = "renesas,sdhi-r8a7790";
 434                 reg = <0 0xee140000 0 0x100>;
 435                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 436                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 437                 cap-sd-highspeed;
 438                 status = "disabled";
 439         };
 440
 441         sdhi3: sd@ee160000 {
 442                 compatible = "renesas,sdhi-r8a7790";
 443                 reg = <0 0xee160000 0 0x100>;
 444                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 445                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 446                 cap-sd-highspeed;
 447                 status = "disabled";
 448         };
 449
 450         scifa0: serial@e6c40000 {
 451                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 452                 reg = <0 0xe6c40000 0 64>;
 453                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 455                 clock-names = "sci_ick";
 456                 status = "disabled";
 457         };
 458
 459         scifa1: serial@e6c50000 {
 460                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 461                 reg = <0 0xe6c50000 0 64>;
 462                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 463                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 464                 clock-names = "sci_ick";
 465                 status = "disabled";
 466         };
 467
 468         scifa2: serial@e6c60000 {
 469                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 470                 reg = <0 0xe6c60000 0 64>;
 471                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 472                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 473                 clock-names = "sci_ick";
 474                 status = "disabled";
 475         };
 476
 477         scifb0: serial@e6c20000 {
 478                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 479                 reg = <0 0xe6c20000 0 64>;
 480                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 481                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 482                 clock-names = "sci_ick";
 483                 status = "disabled";
 484         };
 485
 486         scifb1: serial@e6c30000 {
 487                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 488                 reg = <0 0xe6c30000 0 64>;
 489                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 491                 clock-names = "sci_ick";
 492                 status = "disabled";
 493         };
 494
 495         scifb2: serial@e6ce0000 {
 496                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 497                 reg = <0 0xe6ce0000 0 64>;
 498                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 500                 clock-names = "sci_ick";
 501                 status = "disabled";
 502         };
 503
 504         scif0: serial@e6e60000 {
 505                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 506                 reg = <0 0xe6e60000 0 64>;
 507                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 509                 clock-names = "sci_ick";
 510                 status = "disabled";
 511         };
 512
 513         scif1: serial@e6e68000 {
 514                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 515                 reg = <0 0xe6e68000 0 64>;
 516                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 518                 clock-names = "sci_ick";
 519                 status = "disabled";
 520         };
 521
 522         hscif0: serial@e62c0000 {
 523                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 524                 reg = <0 0xe62c0000 0 96>;
 525                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 526                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 527                 clock-names = "sci_ick";
 528                 status = "disabled";
 529         };
 530
 531         hscif1: serial@e62c8000 {
 532                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 533                 reg = <0 0xe62c8000 0 96>;
 534                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 535                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 536                 clock-names = "sci_ick";
 537                 status = "disabled";
 538         };
 539
 540         ether: ethernet@ee700000 {
 541                 compatible = "renesas,ether-r8a7790";
 542                 reg = <0 0xee700000 0 0x400>;
 543                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 544                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 545                 phy-mode = "rmii";
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         sata0: sata@ee300000 {
 552                 compatible = "renesas,sata-r8a7790";
 553                 reg = <0 0xee300000 0 0x2000>;
 554                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 555                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 556                 status = "disabled";
 557         };
 558
 559         sata1: sata@ee500000 {
 560                 compatible = "renesas,sata-r8a7790";
 561                 reg = <0 0xee500000 0 0x2000>;
 562                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 564                 status = "disabled";
 565         };
 566
 567         clocks {
 568                 #address-cells = <2>;
 569                 #size-cells = <2>;
 570                 ranges;
 571
 572                 /* External root clock */
 573                 extal_clk: extal_clk {
 574                         compatible = "fixed-clock";
 575                         #clock-cells = <0>;
 576                         /* This value must be overriden by the board. */
 577                         clock-frequency = <0>;
 578                         clock-output-names = "extal";
 579                 };
 580
 581                 /* External PCIe clock - can be overridden by the board */
 582                 pcie_bus_clk: pcie_bus_clk {
 583                         compatible = "fixed-clock";
 584                         #clock-cells = <0>;
 585                         clock-frequency = <100000000>;
 586                         clock-output-names = "pcie_bus";
 587                         status = "disabled";
 588                 };
 589
 590                 /*
 591                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 592                  * default. Boards that provide audio clocks should override them.
 593                  */
 594                 audio_clk_a: audio_clk_a {
 595                         compatible = "fixed-clock";
 596                         #clock-cells = <0>;
 597                         clock-frequency = <0>;
 598                         clock-output-names = "audio_clk_a";
 599                 };
 600                 audio_clk_b: audio_clk_b {
 601                         compatible = "fixed-clock";
 602                         #clock-cells = <0>;
 603                         clock-frequency = <0>;
 604                         clock-output-names = "audio_clk_b";
 605                 };
 606                 audio_clk_c: audio_clk_c {
 607                         compatible = "fixed-clock";
 608                         #clock-cells = <0>;
 609                         clock-frequency = <0>;
 610                         clock-output-names = "audio_clk_c";
 611                 };
 612
 613                 /* Special CPG clocks */
 614                 cpg_clocks: cpg_clocks@e6150000 {
 615                         compatible = "renesas,r8a7790-cpg-clocks",
 616                                      "renesas,rcar-gen2-cpg-clocks";
 617                         reg = <0 0xe6150000 0 0x1000>;
 618                         clocks = <&extal_clk>;
 619                         #clock-cells = <1>;
 620                         clock-output-names = "main", "pll0", "pll1", "pll3",
 621                                              "lb", "qspi", "sdh", "sd0", "sd1",
 622                                              "z";
 623                 };
 624
 625                 /* Variable factor clocks */
 626                 sd2_clk: sd2_clk@e6150078 {
 627                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 628                         reg = <0 0xe6150078 0 4>;
 629                         clocks = <&pll1_div2_clk>;
 630                         #clock-cells = <0>;
 631                         clock-output-names = "sd2";
 632                 };
 633                 sd3_clk: sd3_clk@e615007c {
 634                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 635                         reg = <0 0xe615007c 0 4>;
 636                         clocks = <&pll1_div2_clk>;
 637                         #clock-cells = <0>;
 638                         clock-output-names = "sd3";
 639                 };
 640                 mmc0_clk: mmc0_clk@e6150240 {
 641                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 642                         reg = <0 0xe6150240 0 4>;
 643                         clocks = <&pll1_div2_clk>;
 644                         #clock-cells = <0>;
 645                         clock-output-names = "mmc0";
 646                 };
 647                 mmc1_clk: mmc1_clk@e6150244 {
 648                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 649                         reg = <0 0xe6150244 0 4>;
 650                         clocks = <&pll1_div2_clk>;
 651                         #clock-cells = <0>;
 652                         clock-output-names = "mmc1";
 653                 };
 654                 ssp_clk: ssp_clk@e6150248 {
 655                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 656                         reg = <0 0xe6150248 0 4>;
 657                         clocks = <&pll1_div2_clk>;
 658                         #clock-cells = <0>;
 659                         clock-output-names = "ssp";
 660                 };
 661                 ssprs_clk: ssprs_clk@e615024c {
 662                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 663                         reg = <0 0xe615024c 0 4>;
 664                         clocks = <&pll1_div2_clk>;
 665                         #clock-cells = <0>;
 666                         clock-output-names = "ssprs";
 667                 };
 668
 669                 /* Fixed factor clocks */
 670                 pll1_div2_clk: pll1_div2_clk {
 671                         compatible = "fixed-factor-clock";
 672                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 673                         #clock-cells = <0>;
 674                         clock-div = <2>;
 675                         clock-mult = <1>;
 676                         clock-output-names = "pll1_div2";
 677                 };
 678                 z2_clk: z2_clk {
 679                         compatible = "fixed-factor-clock";
 680                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 681                         #clock-cells = <0>;
 682                         clock-div = <2>;
 683                         clock-mult = <1>;
 684                         clock-output-names = "z2";
 685                 };
 686                 zg_clk: zg_clk {
 687                         compatible = "fixed-factor-clock";
 688                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 689                         #clock-cells = <0>;
 690                         clock-div = <3>;
 691                         clock-mult = <1>;
 692                         clock-output-names = "zg";
 693                 };
 694                 zx_clk: zx_clk {
 695                         compatible = "fixed-factor-clock";
 696                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 697                         #clock-cells = <0>;
 698                         clock-div = <3>;
 699                         clock-mult = <1>;
 700                         clock-output-names = "zx";
 701                 };
 702                 zs_clk: zs_clk {
 703                         compatible = "fixed-factor-clock";
 704                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 705                         #clock-cells = <0>;
 706                         clock-div = <6>;
 707                         clock-mult = <1>;
 708                         clock-output-names = "zs";
 709                 };
 710                 hp_clk: hp_clk {
 711                         compatible = "fixed-factor-clock";
 712                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 713                         #clock-cells = <0>;
 714                         clock-div = <12>;
 715                         clock-mult = <1>;
 716                         clock-output-names = "hp";
 717                 };
 718                 i_clk: i_clk {
 719                         compatible = "fixed-factor-clock";
 720                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 721                         #clock-cells = <0>;
 722                         clock-div = <2>;
 723                         clock-mult = <1>;
 724                         clock-output-names = "i";
 725                 };
 726                 b_clk: b_clk {
 727                         compatible = "fixed-factor-clock";
 728                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 729                         #clock-cells = <0>;
 730                         clock-div = <12>;
 731                         clock-mult = <1>;
 732                         clock-output-names = "b";
 733                 };
 734                 p_clk: p_clk {
 735                         compatible = "fixed-factor-clock";
 736                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 737                         #clock-cells = <0>;
 738                         clock-div = <24>;
 739                         clock-mult = <1>;
 740                         clock-output-names = "p";
 741                 };
 742                 cl_clk: cl_clk {
 743                         compatible = "fixed-factor-clock";
 744                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 745                         #clock-cells = <0>;
 746                         clock-div = <48>;
 747                         clock-mult = <1>;
 748                         clock-output-names = "cl";
 749                 };
 750                 m2_clk: m2_clk {
 751                         compatible = "fixed-factor-clock";
 752                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 753                         #clock-cells = <0>;
 754                         clock-div = <8>;
 755                         clock-mult = <1>;
 756                         clock-output-names = "m2";
 757                 };
 758                 imp_clk: imp_clk {
 759                         compatible = "fixed-factor-clock";
 760                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 761                         #clock-cells = <0>;
 762                         clock-div = <4>;
 763                         clock-mult = <1>;
 764                         clock-output-names = "imp";
 765                 };
 766                 rclk_clk: rclk_clk {
 767                         compatible = "fixed-factor-clock";
 768                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 769                         #clock-cells = <0>;
 770                         clock-div = <(48 * 1024)>;
 771                         clock-mult = <1>;
 772                         clock-output-names = "rclk";
 773                 };
 774                 oscclk_clk: oscclk_clk {
 775                         compatible = "fixed-factor-clock";
 776                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 777                         #clock-cells = <0>;
 778                         clock-div = <(12 * 1024)>;
 779                         clock-mult = <1>;
 780                         clock-output-names = "oscclk";
 781                 };
 782                 zb3_clk: zb3_clk {
 783                         compatible = "fixed-factor-clock";
 784                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 785                         #clock-cells = <0>;
 786                         clock-div = <4>;
 787                         clock-mult = <1>;
 788                         clock-output-names = "zb3";
 789                 };
 790                 zb3d2_clk: zb3d2_clk {
 791                         compatible = "fixed-factor-clock";
 792                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 793                         #clock-cells = <0>;
 794                         clock-div = <8>;
 795                         clock-mult = <1>;
 796                         clock-output-names = "zb3d2";
 797                 };
 798                 ddr_clk: ddr_clk {
 799                         compatible = "fixed-factor-clock";
 800                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 801                         #clock-cells = <0>;
 802                         clock-div = <8>;
 803                         clock-mult = <1>;
 804                         clock-output-names = "ddr";
 805                 };
 806                 mp_clk: mp_clk {
 807                         compatible = "fixed-factor-clock";
 808                         clocks = <&pll1_div2_clk>;
 809                         #clock-cells = <0>;
 810                         clock-div = <15>;
 811                         clock-mult = <1>;
 812                         clock-output-names = "mp";
 813                 };
 814                 cp_clk: cp_clk {
 815                         compatible = "fixed-factor-clock";
 816                         clocks = <&extal_clk>;
 817                         #clock-cells = <0>;
 818                         clock-div = <2>;
 819                         clock-mult = <1>;
 820                         clock-output-names = "cp";
 821                 };
 822
 823                 /* Gate clocks */
 824                 mstp0_clks: mstp0_clks@e6150130 {
 825                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 826                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 827                         clocks = <&mp_clk>;
 828                         #clock-cells = <1>;
 829                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 830                         clock-output-names = "msiof0";
 831                 };
 832                 mstp1_clks: mstp1_clks@e6150134 {
 833                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 834                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 835                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 836                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 837                                  <&zs_clk>;
 838                         #clock-cells = <1>;
 839                         renesas,clock-indices = <
 840                                 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 841                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 842                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
 843                         >;
 844                         clock-output-names =
 845                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 846                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 847                 };
 848                 mstp2_clks: mstp2_clks@e6150138 {
 849                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 850                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 851                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 852                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
 853                                  <&zs_clk>;
 854                         #clock-cells = <1>;
 855                         renesas,clock-indices = <
 856                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 857                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 858                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 859                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
 860                         >;
 861                         clock-output-names =
 862                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 863                                 "scifb1", "msiof1", "msiof3", "scifb2",
 864                                 "sys-dmac1", "sys-dmac0";
 865                 };
 866                 mstp3_clks: mstp3_clks@e615013c {
 867                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 868                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 869                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
 870                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
 871                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 872                         #clock-cells = <1>;
 873                         renesas,clock-indices = <
 874                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 875                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
 876                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
 877                         >;
 878                         clock-output-names =
 879                                 "iic2", "tpu0", "mmcif1", "sdhi3",
 880                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 881                                 "iic0", "pciec", "iic1", "ssusb", "cmt1";
 882                 };
 883                 mstp5_clks: mstp5_clks@e6150144 {
 884                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 885                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 886                         clocks = <&extal_clk>, <&p_clk>;
 887                         #clock-cells = <1>;
 888                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 889                         clock-output-names = "thermal", "pwm";
 890                 };
 891                 mstp7_clks: mstp7_clks@e615014c {
 892                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 893                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 894                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 895                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 896                                  <&zx_clk>;
 897                         #clock-cells = <1>;
 898                         renesas,clock-indices = <
 899                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 900                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 901                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 902                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 903                         >;
 904                         clock-output-names =
 905                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 906                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 907                 };
 908                 mstp8_clks: mstp8_clks@e6150990 {
 909                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 910                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 911                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
 912                                  <&zs_clk>, <&zs_clk>;
 913                         #clock-cells = <1>;
 914                         renesas,clock-indices = <
 915                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 916                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
 917                                 R8A7790_CLK_SATA0
 918                         >;
 919                         clock-output-names =
 920                                 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 921                 };
 922                 mstp9_clks: mstp9_clks@e6150994 {
 923                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 924                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 925                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
 926                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
 927                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
 928                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 929                         #clock-cells = <1>;
 930                         renesas,clock-indices = <
 931                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
 932                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
 933                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
 934                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
 935                         >;
 936                         clock-output-names =
 937                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 938                                 "rcan1", "rcan0", "qspi_mod", "iic3",
 939                                 "i2c3", "i2c2", "i2c1", "i2c0";
 940                 };
 941                 mstp10_clks: mstp10_clks@e6150998 {
 942                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 943                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
 944                         clocks = <&p_clk>,
 945                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 946                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 947                                 <&p_clk>,
 948                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 949                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 950                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 951                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 952                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 953                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
 954
 955                         #clock-cells = <1>;
 956                         clock-indices = <
 957                                 R8A7790_CLK_SSI_ALL
 958                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
 959                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
 960                                 R8A7790_CLK_SCU_ALL
 961                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
 962                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
 963                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
 964                         >;
 965                         clock-output-names =
 966                                 "ssi-all",
 967                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
 968                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
 969                                 "scu-all",
 970                                 "scu-dvc1", "scu-dvc0",
 971                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
 972                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
 973                 };
 974         };
 975
 976         qspi: spi@e6b10000 {
 977                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
 978                 reg = <0 0xe6b10000 0 0x2c>;
 979                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 980                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 981                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 982                 dma-names = "tx", "rx";
 983                 num-cs = <1>;
 984                 #address-cells = <1>;
 985                 #size-cells = <0>;
 986                 status = "disabled";
 987         };
 988
 989         msiof0: spi@e6e20000 {
 990                 compatible = "renesas,msiof-r8a7790";
 991                 reg = <0 0xe6e20000 0 0x0064>;
 992                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 993                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
 994                 #address-cells = <1>;
 995                 #size-cells = <0>;
 996                 status = "disabled";
 997         };
 998
 999         msiof1: spi@e6e10000 {
1000                 compatible = "renesas,msiof-r8a7790";
1001                 reg = <0 0xe6e10000 0 0x0064>;
1002                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1003                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1004                 #address-cells = <1>;
1005                 #size-cells = <0>;
1006                 status = "disabled";
1007         };
1008
1009         msiof2: spi@e6e00000 {
1010                 compatible = "renesas,msiof-r8a7790";
1011                 reg = <0 0xe6e00000 0 0x0064>;
1012                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1013                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1014                 #address-cells = <1>;
1015                 #size-cells = <0>;
1016                 status = "disabled";
1017         };
1018
1019         msiof3: spi@e6c90000 {
1020                 compatible = "renesas,msiof-r8a7790";
1021                 reg = <0 0xe6c90000 0 0x0064>;
1022                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1023                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1024                 #address-cells = <1>;
1025                 #size-cells = <0>;
1026                 status = "disabled";
1027         };
1028
1029         pci0: pci@ee090000 {
1030                 compatible = "renesas,pci-r8a7790";
1031                 device_type = "pci";
1032                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1033                 reg = <0 0xee090000 0 0xc00>,
1034                       <0 0xee080000 0 0x1100>;
1035                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1036                 status = "disabled";
1037
1038                 bus-range = <0 0>;
1039                 #address-cells = <3>;
1040                 #size-cells = <2>;
1041                 #interrupt-cells = <1>;
1042                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1043                 interrupt-map-mask = <0xff00 0 0 0x7>;
1044                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1045                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1046                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1047         };
1048
1049         pci1: pci@ee0b0000 {
1050                 compatible = "renesas,pci-r8a7790";
1051                 device_type = "pci";
1052                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1053                 reg = <0 0xee0b0000 0 0xc00>,
1054                       <0 0xee0a0000 0 0x1100>;
1055                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1056                 status = "disabled";
1057
1058                 bus-range = <1 1>;
1059                 #address-cells = <3>;
1060                 #size-cells = <2>;
1061                 #interrupt-cells = <1>;
1062                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1063                 interrupt-map-mask = <0xff00 0 0 0x7>;
1064                 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1065                                  0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1066                                  0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1067         };
1068
1069         pci2: pci@ee0d0000 {
1070                 compatible = "renesas,pci-r8a7790";
1071                 device_type = "pci";
1072                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1073                 reg = <0 0xee0d0000 0 0xc00>,
1074                       <0 0xee0c0000 0 0x1100>;
1075                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1076                 status = "disabled";
1077
1078                 bus-range = <2 2>;
1079                 #address-cells = <3>;
1080                 #size-cells = <2>;
1081                 #interrupt-cells = <1>;
1082                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1083                 interrupt-map-mask = <0xff00 0 0 0x7>;
1084                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1085                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1086                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1087         };
1088
1089         pciec: pcie@fe000000 {
1090                 compatible = "renesas,pcie-r8a7790";
1091                 reg = <0 0xfe000000 0 0x80000>;
1092                 #address-cells = <3>;
1093                 #size-cells = <2>;
1094                 bus-range = <0x00 0xff>;
1095                 device_type = "pci";
1096                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1097                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1098                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1099                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1100                 /* Map all possible DDR as inbound ranges */
1101                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1102                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1103                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1104                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1105                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1106                 #interrupt-cells = <1>;
1107                 interrupt-map-mask = <0 0 0 0>;
1108                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1109                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1110                 clock-names = "pcie", "pcie_bus";
1111                 status = "disabled";
1112         };
1113
1114         rcar_sound: rcar_sound@0xec500000 {
1115                 #sound-dai-cells = <1>;
1116                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1117                 interrupt-parent = <&gic>;
1118                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1119                         <0 0xec5a0000 0 0x100>,  /* ADG */
1120                         <0 0xec540000 0 0x1000>, /* SSIU */
1121                         <0 0xec541000 0 0x1280>; /* SSI */
1122                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1123                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1124                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1125                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1126                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1127                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1128                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1129                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1130                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1131                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1132                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1133                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1134                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1135                 clock-names = "ssi-all",
1136                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1137                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1138                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1139                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1140                                 "dvc.0", "dvc.1",
1141                                 "clk_a", "clk_b", "clk_c", "clk_i";
1142
1143                 status = "disabled";
1144
1145                 rcar_sound,dvc {
1146                         dvc0: dvc@0 { };
1147                         dvc1: dvc@1 { };
1148                 };
1149
1150                 rcar_sound,src {
1151                         src0: src@0 { };
1152                         src1: src@1 { };
1153                         src2: src@2 { };
1154                         src3: src@3 { };
1155                         src4: src@4 { };
1156                         src5: src@5 { };
1157                         src6: src@6 { };
1158                         src7: src@7 { };
1159                         src8: src@8 { };
1160                         src9: src@9 { };
1161                 };
1162
1163                 rcar_sound,ssi {
1164                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1165                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1166                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1167                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1168                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1169                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1170                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1171                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1172                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1173                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1174                 };
1175         };
1176 };