arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Cogent Embedded Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7790-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7790";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &iic0;
  28                 i2c5 = &iic1;
  29                 i2c6 = &iic2;
  30                 i2c7 = &iic3;
  31                 spi0 = &qspi;
  32                 spi1 = &msiof0;
  33                 spi2 = &msiof1;
  34                 spi3 = &msiof2;
  35                 spi4 = &msiof3;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <0>;
  46                         clock-frequency = <1300000000>;
  47                         voltage-tolerance = <1>; /* 1% */
  48                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  49                         clock-latency = <300000>; /* 300 us */
  50
  51                         /* kHz - uV - OPPs unknown yet */
  52                         operating-points = <1400000 1000000>,
  53                                            <1225000 1000000>,
  54                                            <1050000 1000000>,
  55                                            < 875000 1000000>,
  56                                            < 700000 1000000>,
  57                                            < 350000 1000000>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <1>;
  64                         clock-frequency = <1300000000>;
  65                 };
  66
  67                 cpu2: cpu@2 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a15";
  70                         reg = <2>;
  71                         clock-frequency = <1300000000>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <3>;
  78                         clock-frequency = <1300000000>;
  79                 };
  80
  81                 cpu4: cpu@4 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x100>;
  85                         clock-frequency = <780000000>;
  86                 };
  87
  88                 cpu5: cpu@5 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         reg = <0x101>;
  92                         clock-frequency = <780000000>;
  93                 };
  94
  95                 cpu6: cpu@6 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a7";
  98                         reg = <0x102>;
  99                         clock-frequency = <780000000>;
 100                 };
 101
 102                 cpu7: cpu@7 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a7";
 105                         reg = <0x103>;
 106                         clock-frequency = <780000000>;
 107                 };
 108         };
 109
 110         gic: interrupt-controller@f1001000 {
 111                 compatible = "arm,cortex-a15-gic";
 112                 #interrupt-cells = <3>;
 113                 #address-cells = <0>;
 114                 interrupt-controller;
 115                 reg = <0 0xf1001000 0 0x1000>,
 116                         <0 0xf1002000 0 0x1000>,
 117                         <0 0xf1004000 0 0x2000>,
 118                         <0 0xf1006000 0 0x2000>;
 119                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 120         };
 121
 122         gpio0: gpio@e6050000 {
 123                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 124                 reg = <0 0xe6050000 0 0x50>;
 125                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 0 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 132         };
 133
 134         gpio1: gpio@e6051000 {
 135                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 136                 reg = <0 0xe6051000 0 0x50>;
 137                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 32 32>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 144         };
 145
 146         gpio2: gpio@e6052000 {
 147                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 148                 reg = <0 0xe6052000 0 0x50>;
 149                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 150                 #gpio-cells = <2>;
 151                 gpio-controller;
 152                 gpio-ranges = <&pfc 0 64 32>;
 153                 #interrupt-cells = <2>;
 154                 interrupt-controller;
 155                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 156         };
 157
 158         gpio3: gpio@e6053000 {
 159                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 160                 reg = <0 0xe6053000 0 0x50>;
 161                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 162                 #gpio-cells = <2>;
 163                 gpio-controller;
 164                 gpio-ranges = <&pfc 0 96 32>;
 165                 #interrupt-cells = <2>;
 166                 interrupt-controller;
 167                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 168         };
 169
 170         gpio4: gpio@e6054000 {
 171                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 172                 reg = <0 0xe6054000 0 0x50>;
 173                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 174                 #gpio-cells = <2>;
 175                 gpio-controller;
 176                 gpio-ranges = <&pfc 0 128 32>;
 177                 #interrupt-cells = <2>;
 178                 interrupt-controller;
 179                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 180         };
 181
 182         gpio5: gpio@e6055000 {
 183                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 184                 reg = <0 0xe6055000 0 0x50>;
 185                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 186                 #gpio-cells = <2>;
 187                 gpio-controller;
 188                 gpio-ranges = <&pfc 0 160 32>;
 189                 #interrupt-cells = <2>;
 190                 interrupt-controller;
 191                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 192         };
 193
 194         thermal@e61f0000 {
 195                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 196                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 197                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 199         };
 200
 201         timer {
 202                 compatible = "arm,armv7-timer";
 203                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 204                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 205                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 206                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 207         };
 208
 209         irqc0: interrupt-controller@e61c0000 {
 210                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 211                 #interrupt-cells = <2>;
 212                 interrupt-controller;
 213                 reg = <0 0xe61c0000 0 0x200>;
 214                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 215                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 216                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 217                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 218         };
 219
 220         i2c0: i2c@e6508000 {
 221                 #address-cells = <1>;
 222                 #size-cells = <0>;
 223                 compatible = "renesas,i2c-r8a7790";
 224                 reg = <0 0xe6508000 0 0x40>;
 225                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 227                 status = "disabled";
 228         };
 229
 230         i2c1: i2c@e6518000 {
 231                 #address-cells = <1>;
 232                 #size-cells = <0>;
 233                 compatible = "renesas,i2c-r8a7790";
 234                 reg = <0 0xe6518000 0 0x40>;
 235                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 237                 status = "disabled";
 238         };
 239
 240         i2c2: i2c@e6530000 {
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 compatible = "renesas,i2c-r8a7790";
 244                 reg = <0 0xe6530000 0 0x40>;
 245                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 247                 status = "disabled";
 248         };
 249
 250         i2c3: i2c@e6540000 {
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 compatible = "renesas,i2c-r8a7790";
 254                 reg = <0 0xe6540000 0 0x40>;
 255                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 257                 status = "disabled";
 258         };
 259
 260         iic0: i2c@e6500000 {
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 264                 reg = <0 0xe6500000 0 0x425>;
 265                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 267                 status = "disabled";
 268         };
 269
 270         iic1: i2c@e6510000 {
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 274                 reg = <0 0xe6510000 0 0x425>;
 275                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 276                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 277                 status = "disabled";
 278         };
 279
 280         iic2: i2c@e6520000 {
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 284                 reg = <0 0xe6520000 0 0x425>;
 285                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 287                 status = "disabled";
 288         };
 289
 290         iic3: i2c@e60b0000 {
 291                 #address-cells = <1>;
 292                 #size-cells = <0>;
 293                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 294                 reg = <0 0xe60b0000 0 0x425>;
 295                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 296                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 297                 status = "disabled";
 298         };
 299
 300         mmcif0: mmcif@ee200000 {
 301                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 302                 reg = <0 0xee200000 0 0x80>;
 303                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 305                 reg-io-width = <4>;
 306                 status = "disabled";
 307         };
 308
 309         mmcif1: mmc@ee220000 {
 310                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 311                 reg = <0 0xee220000 0 0x80>;
 312                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 314                 reg-io-width = <4>;
 315                 status = "disabled";
 316         };
 317
 318         pfc: pfc@e6060000 {
 319                 compatible = "renesas,pfc-r8a7790";
 320                 reg = <0 0xe6060000 0 0x250>;
 321         };
 322
 323         sdhi0: sd@ee100000 {
 324                 compatible = "renesas,sdhi-r8a7790";
 325                 reg = <0 0xee100000 0 0x200>;
 326                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 328                 cap-sd-highspeed;
 329                 status = "disabled";
 330         };
 331
 332         sdhi1: sd@ee120000 {
 333                 compatible = "renesas,sdhi-r8a7790";
 334                 reg = <0 0xee120000 0 0x200>;
 335                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 337                 cap-sd-highspeed;
 338                 status = "disabled";
 339         };
 340
 341         sdhi2: sd@ee140000 {
 342                 compatible = "renesas,sdhi-r8a7790";
 343                 reg = <0 0xee140000 0 0x100>;
 344                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 346                 cap-sd-highspeed;
 347                 status = "disabled";
 348         };
 349
 350         sdhi3: sd@ee160000 {
 351                 compatible = "renesas,sdhi-r8a7790";
 352                 reg = <0 0xee160000 0 0x100>;
 353                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 355                 cap-sd-highspeed;
 356                 status = "disabled";
 357         };
 358
 359         scifa0: serial@e6c40000 {
 360                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 361                 reg = <0 0xe6c40000 0 64>;
 362                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 364                 clock-names = "sci_ick";
 365                 status = "disabled";
 366         };
 367
 368         scifa1: serial@e6c50000 {
 369                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 370                 reg = <0 0xe6c50000 0 64>;
 371                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 372                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 373                 clock-names = "sci_ick";
 374                 status = "disabled";
 375         };
 376
 377         scifa2: serial@e6c60000 {
 378                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 379                 reg = <0 0xe6c60000 0 64>;
 380                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 382                 clock-names = "sci_ick";
 383                 status = "disabled";
 384         };
 385
 386         scifb0: serial@e6c20000 {
 387                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 388                 reg = <0 0xe6c20000 0 64>;
 389                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 391                 clock-names = "sci_ick";
 392                 status = "disabled";
 393         };
 394
 395         scifb1: serial@e6c30000 {
 396                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 397                 reg = <0 0xe6c30000 0 64>;
 398                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 400                 clock-names = "sci_ick";
 401                 status = "disabled";
 402         };
 403
 404         scifb2: serial@e6ce0000 {
 405                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 406                 reg = <0 0xe6ce0000 0 64>;
 407                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 409                 clock-names = "sci_ick";
 410                 status = "disabled";
 411         };
 412
 413         scif0: serial@e6e60000 {
 414                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 415                 reg = <0 0xe6e60000 0 64>;
 416                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 417                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 418                 clock-names = "sci_ick";
 419                 status = "disabled";
 420         };
 421
 422         scif1: serial@e6e68000 {
 423                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 424                 reg = <0 0xe6e68000 0 64>;
 425                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 427                 clock-names = "sci_ick";
 428                 status = "disabled";
 429         };
 430
 431         hscif0: serial@e62c0000 {
 432                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 433                 reg = <0 0xe62c0000 0 96>;
 434                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 436                 clock-names = "sci_ick";
 437                 status = "disabled";
 438         };
 439
 440         hscif1: serial@e62c8000 {
 441                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 442                 reg = <0 0xe62c8000 0 96>;
 443                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 445                 clock-names = "sci_ick";
 446                 status = "disabled";
 447         };
 448
 449         ether: ethernet@ee700000 {
 450                 compatible = "renesas,ether-r8a7790";
 451                 reg = <0 0xee700000 0 0x400>;
 452                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 454                 phy-mode = "rmii";
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 status = "disabled";
 458         };
 459
 460         sata0: sata@ee300000 {
 461                 compatible = "renesas,sata-r8a7790";
 462                 reg = <0 0xee300000 0 0x2000>;
 463                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 465                 status = "disabled";
 466         };
 467
 468         sata1: sata@ee500000 {
 469                 compatible = "renesas,sata-r8a7790";
 470                 reg = <0 0xee500000 0 0x2000>;
 471                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 472                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 473                 status = "disabled";
 474         };
 475
 476         clocks {
 477                 #address-cells = <2>;
 478                 #size-cells = <2>;
 479                 ranges;
 480
 481                 /* External root clock */
 482                 extal_clk: extal_clk {
 483                         compatible = "fixed-clock";
 484                         #clock-cells = <0>;
 485                         /* This value must be overriden by the board. */
 486                         clock-frequency = <0>;
 487                         clock-output-names = "extal";
 488                 };
 489
 490                 /*
 491                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 492                  * default. Boards that provide audio clocks should override them.
 493                  */
 494                 audio_clk_a: audio_clk_a {
 495                         compatible = "fixed-clock";
 496                         #clock-cells = <0>;
 497                         clock-frequency = <0>;
 498                         clock-output-names = "audio_clk_a";
 499                 };
 500                 audio_clk_b: audio_clk_b {
 501                         compatible = "fixed-clock";
 502                         #clock-cells = <0>;
 503                         clock-frequency = <0>;
 504                         clock-output-names = "audio_clk_b";
 505                 };
 506                 audio_clk_c: audio_clk_c {
 507                         compatible = "fixed-clock";
 508                         #clock-cells = <0>;
 509                         clock-frequency = <0>;
 510                         clock-output-names = "audio_clk_c";
 511                 };
 512
 513                 /* Special CPG clocks */
 514                 cpg_clocks: cpg_clocks@e6150000 {
 515                         compatible = "renesas,r8a7790-cpg-clocks",
 516                                      "renesas,rcar-gen2-cpg-clocks";
 517                         reg = <0 0xe6150000 0 0x1000>;
 518                         clocks = <&extal_clk>;
 519                         #clock-cells = <1>;
 520                         clock-output-names = "main", "pll0", "pll1", "pll3",
 521                                              "lb", "qspi", "sdh", "sd0", "sd1",
 522                                              "z";
 523                 };
 524
 525                 /* Variable factor clocks */
 526                 sd2_clk: sd2_clk@e6150078 {
 527                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 528                         reg = <0 0xe6150078 0 4>;
 529                         clocks = <&pll1_div2_clk>;
 530                         #clock-cells = <0>;
 531                         clock-output-names = "sd2";
 532                 };
 533                 sd3_clk: sd3_clk@e615007c {
 534                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 535                         reg = <0 0xe615007c 0 4>;
 536                         clocks = <&pll1_div2_clk>;
 537                         #clock-cells = <0>;
 538                         clock-output-names = "sd3";
 539                 };
 540                 mmc0_clk: mmc0_clk@e6150240 {
 541                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 542                         reg = <0 0xe6150240 0 4>;
 543                         clocks = <&pll1_div2_clk>;
 544                         #clock-cells = <0>;
 545                         clock-output-names = "mmc0";
 546                 };
 547                 mmc1_clk: mmc1_clk@e6150244 {
 548                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 549                         reg = <0 0xe6150244 0 4>;
 550                         clocks = <&pll1_div2_clk>;
 551                         #clock-cells = <0>;
 552                         clock-output-names = "mmc1";
 553                 };
 554                 ssp_clk: ssp_clk@e6150248 {
 555                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 556                         reg = <0 0xe6150248 0 4>;
 557                         clocks = <&pll1_div2_clk>;
 558                         #clock-cells = <0>;
 559                         clock-output-names = "ssp";
 560                 };
 561                 ssprs_clk: ssprs_clk@e615024c {
 562                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 563                         reg = <0 0xe615024c 0 4>;
 564                         clocks = <&pll1_div2_clk>;
 565                         #clock-cells = <0>;
 566                         clock-output-names = "ssprs";
 567                 };
 568
 569                 /* Fixed factor clocks */
 570                 pll1_div2_clk: pll1_div2_clk {
 571                         compatible = "fixed-factor-clock";
 572                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 573                         #clock-cells = <0>;
 574                         clock-div = <2>;
 575                         clock-mult = <1>;
 576                         clock-output-names = "pll1_div2";
 577                 };
 578                 z2_clk: z2_clk {
 579                         compatible = "fixed-factor-clock";
 580                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 581                         #clock-cells = <0>;
 582                         clock-div = <2>;
 583                         clock-mult = <1>;
 584                         clock-output-names = "z2";
 585                 };
 586                 zg_clk: zg_clk {
 587                         compatible = "fixed-factor-clock";
 588                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 589                         #clock-cells = <0>;
 590                         clock-div = <3>;
 591                         clock-mult = <1>;
 592                         clock-output-names = "zg";
 593                 };
 594                 zx_clk: zx_clk {
 595                         compatible = "fixed-factor-clock";
 596                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 597                         #clock-cells = <0>;
 598                         clock-div = <3>;
 599                         clock-mult = <1>;
 600                         clock-output-names = "zx";
 601                 };
 602                 zs_clk: zs_clk {
 603                         compatible = "fixed-factor-clock";
 604                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 605                         #clock-cells = <0>;
 606                         clock-div = <6>;
 607                         clock-mult = <1>;
 608                         clock-output-names = "zs";
 609                 };
 610                 hp_clk: hp_clk {
 611                         compatible = "fixed-factor-clock";
 612                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 613                         #clock-cells = <0>;
 614                         clock-div = <12>;
 615                         clock-mult = <1>;
 616                         clock-output-names = "hp";
 617                 };
 618                 i_clk: i_clk {
 619                         compatible = "fixed-factor-clock";
 620                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 621                         #clock-cells = <0>;
 622                         clock-div = <2>;
 623                         clock-mult = <1>;
 624                         clock-output-names = "i";
 625                 };
 626                 b_clk: b_clk {
 627                         compatible = "fixed-factor-clock";
 628                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 629                         #clock-cells = <0>;
 630                         clock-div = <12>;
 631                         clock-mult = <1>;
 632                         clock-output-names = "b";
 633                 };
 634                 p_clk: p_clk {
 635                         compatible = "fixed-factor-clock";
 636                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 637                         #clock-cells = <0>;
 638                         clock-div = <24>;
 639                         clock-mult = <1>;
 640                         clock-output-names = "p";
 641                 };
 642                 cl_clk: cl_clk {
 643                         compatible = "fixed-factor-clock";
 644                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 645                         #clock-cells = <0>;
 646                         clock-div = <48>;
 647                         clock-mult = <1>;
 648                         clock-output-names = "cl";
 649                 };
 650                 m2_clk: m2_clk {
 651                         compatible = "fixed-factor-clock";
 652                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 653                         #clock-cells = <0>;
 654                         clock-div = <8>;
 655                         clock-mult = <1>;
 656                         clock-output-names = "m2";
 657                 };
 658                 imp_clk: imp_clk {
 659                         compatible = "fixed-factor-clock";
 660                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 661                         #clock-cells = <0>;
 662                         clock-div = <4>;
 663                         clock-mult = <1>;
 664                         clock-output-names = "imp";
 665                 };
 666                 rclk_clk: rclk_clk {
 667                         compatible = "fixed-factor-clock";
 668                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 669                         #clock-cells = <0>;
 670                         clock-div = <(48 * 1024)>;
 671                         clock-mult = <1>;
 672                         clock-output-names = "rclk";
 673                 };
 674                 oscclk_clk: oscclk_clk {
 675                         compatible = "fixed-factor-clock";
 676                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 677                         #clock-cells = <0>;
 678                         clock-div = <(12 * 1024)>;
 679                         clock-mult = <1>;
 680                         clock-output-names = "oscclk";
 681                 };
 682                 zb3_clk: zb3_clk {
 683                         compatible = "fixed-factor-clock";
 684                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 685                         #clock-cells = <0>;
 686                         clock-div = <4>;
 687                         clock-mult = <1>;
 688                         clock-output-names = "zb3";
 689                 };
 690                 zb3d2_clk: zb3d2_clk {
 691                         compatible = "fixed-factor-clock";
 692                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 693                         #clock-cells = <0>;
 694                         clock-div = <8>;
 695                         clock-mult = <1>;
 696                         clock-output-names = "zb3d2";
 697                 };
 698                 ddr_clk: ddr_clk {
 699                         compatible = "fixed-factor-clock";
 700                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 701                         #clock-cells = <0>;
 702                         clock-div = <8>;
 703                         clock-mult = <1>;
 704                         clock-output-names = "ddr";
 705                 };
 706                 mp_clk: mp_clk {
 707                         compatible = "fixed-factor-clock";
 708                         clocks = <&pll1_div2_clk>;
 709                         #clock-cells = <0>;
 710                         clock-div = <15>;
 711                         clock-mult = <1>;
 712                         clock-output-names = "mp";
 713                 };
 714                 cp_clk: cp_clk {
 715                         compatible = "fixed-factor-clock";
 716                         clocks = <&extal_clk>;
 717                         #clock-cells = <0>;
 718                         clock-div = <2>;
 719                         clock-mult = <1>;
 720                         clock-output-names = "cp";
 721                 };
 722
 723                 /* Gate clocks */
 724                 mstp0_clks: mstp0_clks@e6150130 {
 725                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 726                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 727                         clocks = <&mp_clk>;
 728                         #clock-cells = <1>;
 729                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 730                         clock-output-names = "msiof0";
 731                 };
 732                 mstp1_clks: mstp1_clks@e6150134 {
 733                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 734                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 735                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 736                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 737                                  <&zs_clk>;
 738                         #clock-cells = <1>;
 739                         renesas,clock-indices = <
 740                                 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 741                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 742                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
 743                         >;
 744                         clock-output-names =
 745                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 746                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 747                 };
 748                 mstp2_clks: mstp2_clks@e6150138 {
 749                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 750                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 751                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 752                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
 753                         #clock-cells = <1>;
 754                         renesas,clock-indices = <
 755                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 756                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 757                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 758                         >;
 759                         clock-output-names =
 760                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 761                                 "scifb1", "msiof1", "msiof3", "scifb2";
 762                 };
 763                 mstp3_clks: mstp3_clks@e615013c {
 764                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 765                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 766                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
 767                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
 768                                  <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 769                         #clock-cells = <1>;
 770                         renesas,clock-indices = <
 771                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 772                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
 773                                 R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
 774                         >;
 775                         clock-output-names =
 776                                 "iic2", "tpu0", "mmcif1", "sdhi3",
 777                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 778                                 "iic0", "iic1", "ssusb", "cmt1";
 779                 };
 780                 mstp5_clks: mstp5_clks@e6150144 {
 781                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 782                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 783                         clocks = <&extal_clk>, <&p_clk>;
 784                         #clock-cells = <1>;
 785                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 786                         clock-output-names = "thermal", "pwm";
 787                 };
 788                 mstp7_clks: mstp7_clks@e615014c {
 789                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 790                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 791                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 792                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 793                                  <&zx_clk>;
 794                         #clock-cells = <1>;
 795                         renesas,clock-indices = <
 796                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 797                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 798                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 799                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 800                         >;
 801                         clock-output-names =
 802                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 803                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 804                 };
 805                 mstp8_clks: mstp8_clks@e6150990 {
 806                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 807                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 808                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
 809                                  <&zs_clk>, <&zs_clk>;
 810                         #clock-cells = <1>;
 811                         renesas,clock-indices = <
 812                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 813                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
 814                                 R8A7790_CLK_SATA0
 815                         >;
 816                         clock-output-names =
 817                                 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 818                 };
 819                 mstp9_clks: mstp9_clks@e6150994 {
 820                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 821                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 822                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
 823                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
 824                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
 825                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 826                         #clock-cells = <1>;
 827                         renesas,clock-indices = <
 828                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
 829                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
 830                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
 831                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
 832                         >;
 833                         clock-output-names =
 834                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 835                                 "rcan1", "rcan0", "qspi_mod", "iic3",
 836                                 "i2c3", "i2c2", "i2c1", "i2c0";
 837                 };
 838                 mstp10_clks: mstp10_clks@e6150998 {
 839                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 840                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
 841                         clocks = <&p_clk>,
 842                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 843                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 844                                 <&p_clk>,
 845                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 846                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 847                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 848                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 849                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
 850                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
 851
 852                         #clock-cells = <1>;
 853                         clock-indices = <
 854                                 R8A7790_CLK_SSI_ALL
 855                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
 856                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
 857                                 R8A7790_CLK_SCU_ALL
 858                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
 859                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
 860                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
 861                         >;
 862                         clock-output-names =
 863                                 "ssi-all",
 864                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
 865                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
 866                                 "scu-all",
 867                                 "scu-dvc1", "scu-dvc0",
 868                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
 869                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
 870                 };
 871         };
 872
 873         qspi: spi@e6b10000 {
 874                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
 875                 reg = <0 0xe6b10000 0 0x2c>;
 876                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 877                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 878                 num-cs = <1>;
 879                 #address-cells = <1>;
 880                 #size-cells = <0>;
 881                 status = "disabled";
 882         };
 883
 884         msiof0: spi@e6e20000 {
 885                 compatible = "renesas,msiof-r8a7790";
 886                 reg = <0 0xe6e20000 0 0x0064>;
 887                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 888                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
 889                 #address-cells = <1>;
 890                 #size-cells = <0>;
 891                 status = "disabled";
 892         };
 893
 894         msiof1: spi@e6e10000 {
 895                 compatible = "renesas,msiof-r8a7790";
 896                 reg = <0 0xe6e10000 0 0x0064>;
 897                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 898                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
 899                 #address-cells = <1>;
 900                 #size-cells = <0>;
 901                 status = "disabled";
 902         };
 903
 904         msiof2: spi@e6e00000 {
 905                 compatible = "renesas,msiof-r8a7790";
 906                 reg = <0 0xe6e00000 0 0x0064>;
 907                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 908                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
 909                 #address-cells = <1>;
 910                 #size-cells = <0>;
 911                 status = "disabled";
 912         };
 913
 914         msiof3: spi@e6c90000 {
 915                 compatible = "renesas,msiof-r8a7790";
 916                 reg = <0 0xe6c90000 0 0x0064>;
 917                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
 918                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
 919                 #address-cells = <1>;
 920                 #size-cells = <0>;
 921                 status = "disabled";
 922         };
 923
 924         rcar_sound: rcar_sound@0xec500000 {
 925                 #sound-dai-cells = <1>;
 926                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
 927                 interrupt-parent = <&gic>;
 928                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
 929                         <0 0xec5a0000 0 0x100>,  /* ADG */
 930                         <0 0xec540000 0 0x1000>, /* SSIU */
 931                         <0 0xec541000 0 0x1280>; /* SSI */
 932                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
 933                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
 934                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
 935                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
 936                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
 937                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
 938                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
 939                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
 940                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
 941                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
 942                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
 943                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
 944                 clock-names = "ssi-all",
 945                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
 946                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
 947                                 "src.9", "src.8", "src.7", "src.6", "src.5",
 948                                 "src.4", "src.3", "src.2", "src.1", "src.0",
 949                                 "clk_a", "clk_b", "clk_c", "clk_i";
 950
 951                 status = "disabled";
 952
 953                 rcar_sound,src {
 954                         src0: src@0 { };
 955                         src1: src@1 { };
 956                         src2: src@2 { };
 957                         src3: src@3 { };
 958                         src4: src@4 { };
 959                         src5: src@5 { };
 960                         src6: src@6 { };
 961                         src7: src@7 { };
 962                         src8: src@8 { };
 963                         src9: src@9 { };
 964                 };
 965
 966                 rcar_sound,ssi {
 967                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
 968                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
 969                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
 970                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
 971                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
 972                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
 973                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
 974                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
 975                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
 976                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
 977                 };
 978         };
 979 };