arch/arm/boot/dts/r8a7779.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7779
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Simon Horman
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /include/ "skeleton.dtsi"
  13
  14 #include <dt-bindings/clock/r8a7779-clock.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7779";
  19         interrupt-parent = <&gic>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <0>;
  29                         clock-frequency = <1000000000>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                         clock-frequency = <1000000000>;
  36                 };
  37                 cpu@2 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a9";
  40                         reg = <2>;
  41                         clock-frequency = <1000000000>;
  42                 };
  43                 cpu@3 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a9";
  46                         reg = <3>;
  47                         clock-frequency = <1000000000>;
  48                 };
  49         };
  50
  51         aliases {
  52                 spi0 = &hspi0;
  53                 spi1 = &hspi1;
  54                 spi2 = &hspi2;
  55         };
  56
  57         gic: interrupt-controller@f0001000 {
  58                 compatible = "arm,cortex-a9-gic";
  59                 #interrupt-cells = <3>;
  60                 interrupt-controller;
  61                 reg = <0xf0001000 0x1000>,
  62                       <0xf0000100 0x100>;
  63         };
  64
  65         gpio0: gpio@ffc40000 {
  66                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  67                 reg = <0xffc40000 0x2c>;
  68                 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
  69                 #gpio-cells = <2>;
  70                 gpio-controller;
  71                 gpio-ranges = <&pfc 0 0 32>;
  72                 #interrupt-cells = <2>;
  73                 interrupt-controller;
  74         };
  75
  76         gpio1: gpio@ffc41000 {
  77                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  78                 reg = <0xffc41000 0x2c>;
  79                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
  80                 #gpio-cells = <2>;
  81                 gpio-controller;
  82                 gpio-ranges = <&pfc 0 32 32>;
  83                 #interrupt-cells = <2>;
  84                 interrupt-controller;
  85         };
  86
  87         gpio2: gpio@ffc42000 {
  88                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  89                 reg = <0xffc42000 0x2c>;
  90                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
  91                 #gpio-cells = <2>;
  92                 gpio-controller;
  93                 gpio-ranges = <&pfc 0 64 32>;
  94                 #interrupt-cells = <2>;
  95                 interrupt-controller;
  96         };
  97
  98         gpio3: gpio@ffc43000 {
  99                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 100                 reg = <0xffc43000 0x2c>;
 101                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 102                 #gpio-cells = <2>;
 103                 gpio-controller;
 104                 gpio-ranges = <&pfc 0 96 32>;
 105                 #interrupt-cells = <2>;
 106                 interrupt-controller;
 107         };
 108
 109         gpio4: gpio@ffc44000 {
 110                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 111                 reg = <0xffc44000 0x2c>;
 112                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 113                 #gpio-cells = <2>;
 114                 gpio-controller;
 115                 gpio-ranges = <&pfc 0 128 32>;
 116                 #interrupt-cells = <2>;
 117                 interrupt-controller;
 118         };
 119
 120         gpio5: gpio@ffc45000 {
 121                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 122                 reg = <0xffc45000 0x2c>;
 123                 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
 124                 #gpio-cells = <2>;
 125                 gpio-controller;
 126                 gpio-ranges = <&pfc 0 160 32>;
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129         };
 130
 131         gpio6: gpio@ffc46000 {
 132                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 133                 reg = <0xffc46000 0x2c>;
 134                 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 gpio-ranges = <&pfc 0 192 9>;
 138                 #interrupt-cells = <2>;
 139                 interrupt-controller;
 140         };
 141
 142         irqpin0: irqpin@fe780010 {
 143                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 144                 #interrupt-cells = <2>;
 145                 status = "disabled";
 146                 interrupt-controller;
 147                 reg = <0xfe78001c 4>,
 148                         <0xfe780010 4>,
 149                         <0xfe780024 4>,
 150                         <0xfe780044 4>,
 151                         <0xfe780064 4>;
 152                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
 153                               0 28 IRQ_TYPE_LEVEL_HIGH
 154                               0 29 IRQ_TYPE_LEVEL_HIGH
 155                               0 30 IRQ_TYPE_LEVEL_HIGH>;
 156                 sense-bitfield-width = <2>;
 157         };
 158
 159         i2c0: i2c@ffc70000 {
 160                 #address-cells = <1>;
 161                 #size-cells = <0>;
 162                 compatible = "renesas,i2c-r8a7779";
 163                 reg = <0xffc70000 0x1000>;
 164                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
 165                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 166                 status = "disabled";
 167         };
 168
 169         i2c1: i2c@ffc71000 {
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172                 compatible = "renesas,i2c-r8a7779";
 173                 reg = <0xffc71000 0x1000>;
 174                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 176                 status = "disabled";
 177         };
 178
 179         i2c2: i2c@ffc72000 {
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 compatible = "renesas,i2c-r8a7779";
 183                 reg = <0xffc72000 0x1000>;
 184                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 186                 status = "disabled";
 187         };
 188
 189         i2c3: i2c@ffc73000 {
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 compatible = "renesas,i2c-r8a7779";
 193                 reg = <0xffc73000 0x1000>;
 194                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 196                 status = "disabled";
 197         };
 198
 199         pfc: pfc@fffc0000 {
 200                 compatible = "renesas,pfc-r8a7779";
 201                 reg = <0xfffc0000 0x23c>;
 202         };
 203
 204         thermal@ffc48000 {
 205                 compatible = "renesas,rcar-thermal";
 206                 reg = <0xffc48000 0x38>;
 207         };
 208
 209         sata: sata@fc600000 {
 210                 compatible = "renesas,rcar-sata";
 211                 reg = <0xfc600000 0x2000>;
 212                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 214         };
 215
 216         sdhi0: sd@ffe4c000 {
 217                 compatible = "renesas,sdhi-r8a7779";
 218                 reg = <0xffe4c000 0x100>;
 219                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 221                 cap-sd-highspeed;
 222                 cap-sdio-irq;
 223                 status = "disabled";
 224         };
 225
 226         sdhi1: sd@ffe4d000 {
 227                 compatible = "renesas,sdhi-r8a7779";
 228                 reg = <0xffe4d000 0x100>;
 229                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 231                 cap-sd-highspeed;
 232                 cap-sdio-irq;
 233                 status = "disabled";
 234         };
 235
 236         sdhi2: sd@ffe4e000 {
 237                 compatible = "renesas,sdhi-r8a7779";
 238                 reg = <0xffe4e000 0x100>;
 239                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 241                 cap-sd-highspeed;
 242                 cap-sdio-irq;
 243                 status = "disabled";
 244         };
 245
 246         sdhi3: sd@ffe4f000 {
 247                 compatible = "renesas,sdhi-r8a7779";
 248                 reg = <0xffe4f000 0x100>;
 249                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 250                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 251                 cap-sd-highspeed;
 252                 cap-sdio-irq;
 253                 status = "disabled";
 254         };
 255
 256         hspi0: spi@fffc7000 {
 257                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 258                 reg = <0xfffc7000 0x18>;
 259                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 260                 #address-cells = <1>;
 261                 #size-cells = <0>;
 262                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 263                 status = "disabled";
 264         };
 265
 266         hspi1: spi@fffc8000 {
 267                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 268                 reg = <0xfffc8000 0x18>;
 269                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 273                 status = "disabled";
 274         };
 275
 276         hspi2: spi@fffc6000 {
 277                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 278                 reg = <0xfffc6000 0x18>;
 279                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 283                 status = "disabled";
 284         };
 285
 286         clocks {
 287                 #address-cells = <1>;
 288                 #size-cells = <1>;
 289                 ranges;
 290
 291                 /* External root clock */
 292                 extal_clk: extal_clk {
 293                         compatible = "fixed-clock";
 294                         #clock-cells = <0>;
 295                         /* This value must be overriden by the board. */
 296                         clock-frequency = <0>;
 297                         clock-output-names = "extal";
 298                 };
 299
 300                 /* Special CPG clocks */
 301                 cpg_clocks: clocks@ffc80000 {
 302                         compatible = "renesas,r8a7779-cpg-clocks";
 303                         reg = <0xffc80000 0x30>;
 304                         clocks = <&extal_clk>;
 305                         #clock-cells = <1>;
 306                         clock-output-names = "plla", "z", "zs", "s",
 307                                              "s1", "p", "b", "out";
 308                 };
 309
 310                 /* Fixed factor clocks */
 311                 i_clk: i_clk {
 312                         compatible = "fixed-factor-clock";
 313                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 314                         #clock-cells = <0>;
 315                         clock-div = <2>;
 316                         clock-mult = <1>;
 317                         clock-output-names = "i";
 318                 };
 319                 s3_clk: s3_clk {
 320                         compatible = "fixed-factor-clock";
 321                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 322                         #clock-cells = <0>;
 323                         clock-div = <8>;
 324                         clock-mult = <1>;
 325                         clock-output-names = "s3";
 326                 };
 327                 s4_clk: s4_clk {
 328                         compatible = "fixed-factor-clock";
 329                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 330                         #clock-cells = <0>;
 331                         clock-div = <16>;
 332                         clock-mult = <1>;
 333                         clock-output-names = "s4";
 334                 };
 335                 g_clk: g_clk {
 336                         compatible = "fixed-factor-clock";
 337                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 338                         #clock-cells = <0>;
 339                         clock-div = <24>;
 340                         clock-mult = <1>;
 341                         clock-output-names = "g";
 342                 };
 343
 344                 /* Gate clocks */
 345                 mstp0_clks: clocks@ffc80030 {
 346                         compatible = "renesas,r8a7779-mstp-clocks",
 347                                      "renesas,cpg-mstp-clocks";
 348                         reg = <0xffc80030 4>;
 349                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 350                                  <&cpg_clocks R8A7779_CLK_P>,
 351                                  <&cpg_clocks R8A7779_CLK_P>,
 352                                  <&cpg_clocks R8A7779_CLK_P>,
 353                                  <&cpg_clocks R8A7779_CLK_S>,
 354                                  <&cpg_clocks R8A7779_CLK_S>,
 355                                  <&cpg_clocks R8A7779_CLK_S1>,
 356                                  <&cpg_clocks R8A7779_CLK_S1>,
 357                                  <&cpg_clocks R8A7779_CLK_S1>,
 358                                  <&cpg_clocks R8A7779_CLK_S1>,
 359                                  <&cpg_clocks R8A7779_CLK_S1>,
 360                                  <&cpg_clocks R8A7779_CLK_S1>,
 361                                  <&cpg_clocks R8A7779_CLK_P>,
 362                                  <&cpg_clocks R8A7779_CLK_P>,
 363                                  <&cpg_clocks R8A7779_CLK_P>,
 364                                  <&cpg_clocks R8A7779_CLK_P>;
 365                         #clock-cells = <1>;
 366                         renesas,clock-indices = <
 367                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 368                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 369                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 370                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 371                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 372                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 373                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 374                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 375                         >;
 376                         clock-output-names =
 377                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 378                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 379                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 380                                 "i2c0";
 381                 };
 382                 mstp1_clks: clocks@ffc80034 {
 383                         compatible = "renesas,r8a7779-mstp-clocks",
 384                                      "renesas,cpg-mstp-clocks";
 385                         reg = <0xffc80034 4>, <0xffc80044 4>;
 386                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 387                                  <&cpg_clocks R8A7779_CLK_P>,
 388                                  <&cpg_clocks R8A7779_CLK_S>,
 389                                  <&cpg_clocks R8A7779_CLK_S>,
 390                                  <&cpg_clocks R8A7779_CLK_S>,
 391                                  <&cpg_clocks R8A7779_CLK_S>,
 392                                  <&cpg_clocks R8A7779_CLK_P>,
 393                                  <&cpg_clocks R8A7779_CLK_P>,
 394                                  <&cpg_clocks R8A7779_CLK_P>,
 395                                  <&cpg_clocks R8A7779_CLK_S>;
 396                         #clock-cells = <1>;
 397                         renesas,clock-indices = <
 398                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 399                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 400                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 401                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 402                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 403                         >;
 404                         clock-output-names =
 405                                 "usb01", "usb2",
 406                                 "du", "vin2",
 407                                 "vin1", "vin0",
 408                                 "ether", "sata",
 409                                 "pcie", "vin3";
 410                 };
 411                 mstp3_clks: clocks@ffc8003c {
 412                         compatible = "renesas,r8a7779-mstp-clocks",
 413                                      "renesas,cpg-mstp-clocks";
 414                         reg = <0xffc8003c 4>;
 415                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 416                                  <&s4_clk>, <&s4_clk>;
 417                         #clock-cells = <1>;
 418                         renesas,clock-indices = <
 419                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 420                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 421                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 422                         >;
 423                         clock-output-names =
 424                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 425                                 "mmc1", "mmc0";
 426                 };
 427         };
 428 };