arch/arm/boot/dts/r8a7740.dtsi

   1 /*
   2  * Device Tree Source for the r8a7740 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 #include <dt-bindings/clock/r8a7740-clock.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7740";
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a9";
  25                         device_type = "cpu";
  26                         reg = <0x0>;
  27                         clock-frequency = <800000000>;
  28                 };
  29         };
  30
  31         gic: interrupt-controller@c2800000 {
  32                 compatible = "arm,cortex-a9-gic";
  33                 #interrupt-cells = <3>;
  34                 interrupt-controller;
  35                 reg = <0xc2800000 0x1000>,
  36                       <0xc2000000 0x1000>;
  37         };
  38
  39         pmu {
  40                 compatible = "arm,cortex-a9-pmu";
  41                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
  42         };
  43
  44         /* irqpin0: IRQ0 - IRQ7 */
  45         irqpin0: irqpin@e6900000 {
  46                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  47                 #interrupt-cells = <2>;
  48                 interrupt-controller;
  49                 reg = <0xe6900000 4>,
  50                         <0xe6900010 4>,
  51                         <0xe6900020 1>,
  52                         <0xe6900040 1>,
  53                         <0xe6900060 1>;
  54                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
  55                               0 149 IRQ_TYPE_LEVEL_HIGH
  56                               0 149 IRQ_TYPE_LEVEL_HIGH
  57                               0 149 IRQ_TYPE_LEVEL_HIGH
  58                               0 149 IRQ_TYPE_LEVEL_HIGH
  59                               0 149 IRQ_TYPE_LEVEL_HIGH
  60                               0 149 IRQ_TYPE_LEVEL_HIGH
  61                               0 149 IRQ_TYPE_LEVEL_HIGH>;
  62         };
  63
  64         /* irqpin1: IRQ8 - IRQ15 */
  65         irqpin1: irqpin@e6900004 {
  66                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  67                 #interrupt-cells = <2>;
  68                 interrupt-controller;
  69                 reg = <0xe6900004 4>,
  70                         <0xe6900014 4>,
  71                         <0xe6900024 1>,
  72                         <0xe6900044 1>,
  73                         <0xe6900064 1>;
  74                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
  75                               0 149 IRQ_TYPE_LEVEL_HIGH
  76                               0 149 IRQ_TYPE_LEVEL_HIGH
  77                               0 149 IRQ_TYPE_LEVEL_HIGH
  78                               0 149 IRQ_TYPE_LEVEL_HIGH
  79                               0 149 IRQ_TYPE_LEVEL_HIGH
  80                               0 149 IRQ_TYPE_LEVEL_HIGH
  81                               0 149 IRQ_TYPE_LEVEL_HIGH>;
  82         };
  83
  84         /* irqpin2: IRQ16 - IRQ23 */
  85         irqpin2: irqpin@e6900008 {
  86                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  87                 #interrupt-cells = <2>;
  88                 interrupt-controller;
  89                 reg = <0xe6900008 4>,
  90                         <0xe6900018 4>,
  91                         <0xe6900028 1>,
  92                         <0xe6900048 1>,
  93                         <0xe6900068 1>;
  94                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
  95                               0 149 IRQ_TYPE_LEVEL_HIGH
  96                               0 149 IRQ_TYPE_LEVEL_HIGH
  97                               0 149 IRQ_TYPE_LEVEL_HIGH
  98                               0 149 IRQ_TYPE_LEVEL_HIGH
  99                               0 149 IRQ_TYPE_LEVEL_HIGH
 100                               0 149 IRQ_TYPE_LEVEL_HIGH
 101                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 102         };
 103
 104         /* irqpin3: IRQ24 - IRQ31 */
 105         irqpin3: irqpin@e690000c {
 106                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109                 reg = <0xe690000c 4>,
 110                         <0xe690001c 4>,
 111                         <0xe690002c 1>,
 112                         <0xe690004c 1>,
 113                         <0xe690006c 1>;
 114                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
 115                               0 149 IRQ_TYPE_LEVEL_HIGH
 116                               0 149 IRQ_TYPE_LEVEL_HIGH
 117                               0 149 IRQ_TYPE_LEVEL_HIGH
 118                               0 149 IRQ_TYPE_LEVEL_HIGH
 119                               0 149 IRQ_TYPE_LEVEL_HIGH
 120                               0 149 IRQ_TYPE_LEVEL_HIGH
 121                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 122         };
 123
 124         ether: ethernet@e9a00000 {
 125                 compatible = "renesas,gether-r8a7740";
 126                 reg = <0xe9a00000 0x800>,
 127                       <0xe9a01800 0x800>;
 128                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 129                 /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */
 130                 phy-mode = "mii";
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 status = "disabled";
 134         };
 135
 136         i2c0: i2c@fff20000 {
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 140                 reg = <0xfff20000 0x425>;
 141                 interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
 142                               0 202 IRQ_TYPE_LEVEL_HIGH
 143                               0 203 IRQ_TYPE_LEVEL_HIGH
 144                               0 204 IRQ_TYPE_LEVEL_HIGH>;
 145                 status = "disabled";
 146         };
 147
 148         i2c1: i2c@e6c20000 {
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 152                 reg = <0xe6c20000 0x425>;
 153                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
 154                               0 71 IRQ_TYPE_LEVEL_HIGH
 155                               0 72 IRQ_TYPE_LEVEL_HIGH
 156                               0 73 IRQ_TYPE_LEVEL_HIGH>;
 157                 status = "disabled";
 158         };
 159
 160         scifa0: serial@e6c40000 {
 161                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 162                 reg = <0xe6c40000 0x100>;
 163                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 164                 status = "disabled";
 165         };
 166
 167         scifa1: serial@e6c50000 {
 168                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 169                 reg = <0xe6c50000 0x100>;
 170                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
 171                 status = "disabled";
 172         };
 173
 174         scifa2: serial@e6c60000 {
 175                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 176                 reg = <0xe6c60000 0x100>;
 177                 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
 178                 status = "disabled";
 179         };
 180
 181         scifa3: serial@e6c70000 {
 182                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 183                 reg = <0xe6c70000 0x100>;
 184                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 185                 status = "disabled";
 186         };
 187
 188         scifa4: serial@e6c80000 {
 189                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 190                 reg = <0xe6c80000 0x100>;
 191                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 192                 status = "disabled";
 193         };
 194
 195         scifa5: serial@e6cb0000 {
 196                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 197                 reg = <0xe6cb0000 0x100>;
 198                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 199                 status = "disabled";
 200         };
 201
 202         scifa6: serial@e6cc0000 {
 203                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 204                 reg = <0xe6cc0000 0x100>;
 205                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 206                 status = "disabled";
 207         };
 208
 209         scifa7: serial@e6cd0000 {
 210                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 211                 reg = <0xe6cd0000 0x100>;
 212                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 213                 status = "disabled";
 214         };
 215
 216         scifb8: serial@e6c30000 {
 217                 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
 218                 reg = <0xe6c30000 0x100>;
 219                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 220                 status = "disabled";
 221         };
 222
 223         pfc: pfc@e6050000 {
 224                 compatible = "renesas,pfc-r8a7740";
 225                 reg = <0xe6050000 0x8000>,
 226                       <0xe605800c 0x20>;
 227                 gpio-controller;
 228                 #gpio-cells = <2>;
 229                 interrupts-extended =
 230                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 231                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 232                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 233                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 234                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 235                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 236                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 237                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 238         };
 239
 240         tpu: pwm@e6600000 {
 241                 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
 242                 reg = <0xe6600000 0x100>;
 243                 status = "disabled";
 244                 #pwm-cells = <3>;
 245         };
 246
 247         mmcif0: mmc@e6bd0000 {
 248                 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
 249                 reg = <0xe6bd0000 0x100>;
 250                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
 251                               0 57 IRQ_TYPE_LEVEL_HIGH>;
 252                 status = "disabled";
 253         };
 254
 255         sdhi0: sd@e6850000 {
 256                 compatible = "renesas,sdhi-r8a7740";
 257                 reg = <0xe6850000 0x100>;
 258                 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
 259                               0 118 IRQ_TYPE_LEVEL_HIGH
 260                               0 119 IRQ_TYPE_LEVEL_HIGH>;
 261                 cap-sd-highspeed;
 262                 cap-sdio-irq;
 263                 status = "disabled";
 264         };
 265
 266         sdhi1: sd@e6860000 {
 267                 compatible = "renesas,sdhi-r8a7740";
 268                 reg = <0xe6860000 0x100>;
 269                 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
 270                               0 122 IRQ_TYPE_LEVEL_HIGH
 271                               0 123 IRQ_TYPE_LEVEL_HIGH>;
 272                 cap-sd-highspeed;
 273                 cap-sdio-irq;
 274                 status = "disabled";
 275         };
 276
 277         sdhi2: sd@e6870000 {
 278                 compatible = "renesas,sdhi-r8a7740";
 279                 reg = <0xe6870000 0x100>;
 280                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
 281                               0 126 IRQ_TYPE_LEVEL_HIGH
 282                               0 127 IRQ_TYPE_LEVEL_HIGH>;
 283                 cap-sd-highspeed;
 284                 cap-sdio-irq;
 285                 status = "disabled";
 286         };
 287
 288         sh_fsi2: sound@fe1f0000 {
 289                 #sound-dai-cells = <1>;
 290                 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
 291                 reg = <0xfe1f0000 0x400>;
 292                 interrupts = <0 9 0x4>;
 293                 status = "disabled";
 294         };
 295
 296         clocks {
 297                 #address-cells = <1>;
 298                 #size-cells = <1>;
 299                 ranges;
 300
 301                 /* External root clock */
 302                 extalr_clk: extalr_clk {
 303                         compatible = "fixed-clock";
 304                         #clock-cells = <0>;
 305                         clock-frequency = <32768>;
 306                         clock-output-names = "extalr";
 307                 };
 308                 extal1_clk: extal1_clk {
 309                         compatible = "fixed-clock";
 310                         #clock-cells = <0>;
 311                         clock-frequency = <0>;
 312                         clock-output-names = "extal1";
 313                 };
 314                 extal2_clk: extal2_clk {
 315                         compatible = "fixed-clock";
 316                         #clock-cells = <0>;
 317                         clock-frequency = <0>;
 318                         clock-output-names = "extal2";
 319                 };
 320                 dv_clk: dv_clk {
 321                         compatible = "fixed-clock";
 322                         #clock-cells = <0>;
 323                         clock-frequency = <27000000>;
 324                         clock-output-names = "dv";
 325                 };
 326                 fsiack_clk: fsiack_clk {
 327                         compatible = "fixed-clock";
 328                         #clock-cells = <0>;
 329                         clock-frequency = <0>;
 330                         clock-output-names = "fsiack";
 331                 };
 332                 fsibck_clk: fsibck_clk {
 333                         compatible = "fixed-clock";
 334                         #clock-cells = <0>;
 335                         clock-frequency = <0>;
 336                         clock-output-names = "fsibck";
 337                 };
 338
 339                 /* Special CPG clocks */
 340                 cpg_clocks: cpg_clocks@e6150000 {
 341                         compatible = "renesas,r8a7740-cpg-clocks";
 342                         reg = <0xe6150000 0x10000>;
 343                         clocks = <&extal1_clk>, <&extalr_clk>;
 344                         #clock-cells = <1>;
 345                         clock-output-names = "system", "pllc0", "pllc1",
 346                                              "pllc2", "r",
 347                                              "usb24s",
 348                                              "i", "zg", "b", "m1", "hp",
 349                                              "hpp", "usbp", "s", "zb", "m3",
 350                                              "cp";
 351                 };
 352
 353                 /* Variable factor clocks (DIV6) */
 354                 sub_clk: sub_clk@e6150080 {
 355                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 356                         reg = <0xe6150080 4>;
 357                         clocks = <&pllc1_div2_clk>;
 358                         #clock-cells = <0>;
 359                         clock-output-names = "sub";
 360                 };
 361
 362                 /* Fixed factor clocks */
 363                 pllc1_div2_clk: pllc1_div2_clk {
 364                         compatible = "fixed-factor-clock";
 365                         clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
 366                         #clock-cells = <0>;
 367                         clock-div = <2>;
 368                         clock-mult = <1>;
 369                         clock-output-names = "pllc1_div2";
 370                 };
 371                 extal1_div2_clk: extal1_div2_clk {
 372                         compatible = "fixed-factor-clock";
 373                         clocks = <&extal1_clk>;
 374                         #clock-cells = <0>;
 375                         clock-div = <2>;
 376                         clock-mult = <1>;
 377                         clock-output-names = "extal1_div2";
 378                 };
 379
 380                 /* Gate clocks */
 381                 subck_clks: subck_clks@e6150080 {
 382                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 383                         reg = <0xe6150080 4>;
 384                         clocks = <&sub_clk>, <&sub_clk>;
 385                         #clock-cells = <1>;
 386                         renesas,clock-indices = <
 387                                 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
 388                         >;
 389                         clock-output-names =
 390                                 "subck", "subck2";
 391                 };
 392                 mstp1_clks: mstp1_clks@e6150134 {
 393                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 394                         reg = <0xe6150134 4>, <0xe6150038 4>;
 395                         clocks = <&cpg_clocks R8A7740_CLK_S>,
 396                                  <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
 397                                  <&cpg_clocks R8A7740_CLK_B>,
 398                                  <&sub_clk>, <&sub_clk>,
 399                                  <&cpg_clocks R8A7740_CLK_B>;
 400                         #clock-cells = <1>;
 401                         renesas,clock-indices = <
 402                                 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
 403                                 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
 404                                 R8A7740_CLK_LCDC0
 405                         >;
 406                         clock-output-names =
 407                                 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
 408                                 "tmu1", "lcdc0";
 409                 };
 410                 mstp2_clks: mstp2_clks@e6150138 {
 411                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 412                         reg = <0xe6150138 4>, <0xe6150040 4>;
 413                         clocks = <&sub_clk>, <&sub_clk>,
 414                                  <&cpg_clocks R8A7740_CLK_HP>,
 415                                  <&cpg_clocks R8A7740_CLK_HP>,
 416                                  <&cpg_clocks R8A7740_CLK_HP>,
 417                                  <&cpg_clocks R8A7740_CLK_HP>,
 418                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 419                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 420                                  <&sub_clk>;
 421                         #clock-cells = <1>;
 422                         renesas,clock-indices = <
 423                                 R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
 424                                 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
 425                                 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
 426                                 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
 427                                 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
 428                                 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
 429                                 R8A7740_CLK_SCIFA4
 430                         >;
 431                         clock-output-names =
 432                                 "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
 433                                 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
 434                                 "scifa2", "scifa3", "scifa4";
 435                 };
 436                 mstp3_clks: mstp3_clks@e615013c {
 437                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 438                         reg = <0xe615013c 4>, <0xe6150048 4>;
 439                         clocks = <&cpg_clocks R8A7740_CLK_R>,
 440                                  <&cpg_clocks R8A7740_CLK_HP>,
 441                                  <&sub_clk>,
 442                                  <&cpg_clocks R8A7740_CLK_HP>,
 443                                  <&cpg_clocks R8A7740_CLK_HP>,
 444                                  <&cpg_clocks R8A7740_CLK_HP>,
 445                                  <&cpg_clocks R8A7740_CLK_HP>,
 446                                  <&cpg_clocks R8A7740_CLK_HP>,
 447                                  <&cpg_clocks R8A7740_CLK_HP>;
 448                         #clock-cells = <1>;
 449                         renesas,clock-indices = <
 450                                 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
 451                                 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
 452                                 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
 453                         >;
 454                         clock-output-names =
 455                                 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
 456                                 "mmc", "gether", "tpu0";
 457                 };
 458                 mstp4_clks: mstp4_clks@e6150140 {
 459                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 460                         reg = <0xe6150140 4>, <0xe615004c 4>;
 461                         clocks = <&cpg_clocks R8A7740_CLK_HP>,
 462                                  <&cpg_clocks R8A7740_CLK_HP>,
 463                                  <&cpg_clocks R8A7740_CLK_HP>,
 464                                  <&cpg_clocks R8A7740_CLK_HP>;
 465                         #clock-cells = <1>;
 466                         renesas,clock-indices = <
 467                                 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
 468                                 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
 469                         >;
 470                         clock-output-names =
 471                                 "usbhost", "sdhi2", "usbfunc", "usphy";
 472                 };
 473         };
 474 };