1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the r8a73a4 SoC
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "renesas,r8a73a4";
15 interrupt-parent = <&gic>;
25 compatible = "arm,cortex-a15";
27 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
28 clock-frequency = <1500000000>;
29 power-domains = <&pd_a2sl>;
30 next-level-cache = <&L2_CA15>;
33 L2_CA15: cache-controller-0 {
35 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
36 power-domains = <&pd_a3sm>;
41 L2_CA7: cache-controller-1 {
43 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
44 power-domains = <&pd_a3km>;
51 compatible = "arm,coresight-etm3x";
52 power-domains = <&pd_d4>;
56 compatible = "arm,armv7-timer";
57 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
58 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
59 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
60 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
63 dbsc1: memory-controller@e6790000 {
64 compatible = "renesas,dbsc-r8a73a4";
65 reg = <0 0xe6790000 0 0x10000>;
66 power-domains = <&pd_a3bc>;
69 dbsc2: memory-controller@e67a0000 {
70 compatible = "renesas,dbsc-r8a73a4";
71 reg = <0 0xe67a0000 0 0x10000>;
72 power-domains = <&pd_a3bc>;
78 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
79 reg = <0 0xe60b0000 0 0x428>;
80 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
82 power-domains = <&pd_a3sp>;
87 cmt1: timer@e6130000 {
88 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
89 reg = <0 0xe6130000 0 0x1004>;
90 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
100 power-domains = <&pd_c5>;
104 irqc0: interrupt-controller@e61c0000 {
105 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
106 #interrupt-cells = <2>;
107 interrupt-controller;
108 reg = <0 0xe61c0000 0 0x200>;
109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
142 power-domains = <&pd_c4>;
145 irqc1: interrupt-controller@e61c0200 {
146 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 reg = <0 0xe61c0200 0 0x200>;
150 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
177 power-domains = <&pd_c4>;
180 pfc: pinctrl@e6050000 {
181 compatible = "renesas,pfc-r8a73a4";
182 reg = <0 0xe6050000 0 0x9000>;
186 <&pfc 0 0 31>, <&pfc 32 32 9>,
187 <&pfc 64 64 22>, <&pfc 96 96 31>,
188 <&pfc 128 128 7>, <&pfc 160 160 19>,
189 <&pfc 192 192 31>, <&pfc 224 224 27>,
190 <&pfc 256 256 28>, <&pfc 288 288 21>,
192 interrupts-extended =
193 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
194 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
195 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
196 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
197 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
198 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
199 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
200 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
201 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
202 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
203 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
204 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
205 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
206 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
207 <&irqc1 24 0>, <&irqc1 25 0>;
208 power-domains = <&pd_c5>;
212 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
213 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
214 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
215 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
217 power-domains = <&pd_c5>;
221 #address-cells = <1>;
223 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
224 reg = <0 0xe6500000 0 0x428>;
225 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
227 power-domains = <&pd_a3sp>;
232 #address-cells = <1>;
234 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
235 reg = <0 0xe6510000 0 0x428>;
236 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
238 power-domains = <&pd_a3sp>;
243 #address-cells = <1>;
245 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
246 reg = <0 0xe6520000 0 0x428>;
247 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
249 power-domains = <&pd_a3sp>;
254 #address-cells = <1>;
256 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
257 reg = <0 0xe6530000 0 0x428>;
258 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
260 power-domains = <&pd_a3sp>;
265 #address-cells = <1>;
267 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
268 reg = <0 0xe6540000 0 0x428>;
269 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
271 power-domains = <&pd_a3sp>;
276 #address-cells = <1>;
278 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
279 reg = <0 0xe6550000 0 0x428>;
280 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
282 power-domains = <&pd_a3sp>;
287 #address-cells = <1>;
289 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
290 reg = <0 0xe6560000 0 0x428>;
291 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
293 power-domains = <&pd_a3sp>;
298 #address-cells = <1>;
300 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
301 reg = <0 0xe6570000 0 0x428>;
302 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
304 power-domains = <&pd_a3sp>;
308 scifb0: serial@e6c20000 {
309 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
310 reg = <0 0xe6c20000 0 0x100>;
311 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
314 power-domains = <&pd_a3sp>;
318 scifb1: serial@e6c30000 {
319 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
320 reg = <0 0xe6c30000 0 0x100>;
321 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
324 power-domains = <&pd_a3sp>;
328 scifa0: serial@e6c40000 {
329 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
330 reg = <0 0xe6c40000 0 0x100>;
331 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
334 power-domains = <&pd_a3sp>;
338 scifa1: serial@e6c50000 {
339 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
340 reg = <0 0xe6c50000 0 0x100>;
341 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
344 power-domains = <&pd_a3sp>;
348 scifb2: serial@e6ce0000 {
349 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
350 reg = <0 0xe6ce0000 0 0x100>;
351 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
354 power-domains = <&pd_a3sp>;
358 scifb3: serial@e6cf0000 {
359 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
360 reg = <0 0xe6cf0000 0 0x100>;
361 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
364 power-domains = <&pd_c4>;
368 sdhi0: mmc@ee100000 {
369 compatible = "renesas,sdhi-r8a73a4";
370 reg = <0 0xee100000 0 0x100>;
371 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
373 power-domains = <&pd_a3sp>;
378 sdhi1: mmc@ee120000 {
379 compatible = "renesas,sdhi-r8a73a4";
380 reg = <0 0xee120000 0 0x100>;
381 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
383 power-domains = <&pd_a3sp>;
388 sdhi2: mmc@ee140000 {
389 compatible = "renesas,sdhi-r8a73a4";
390 reg = <0 0xee140000 0 0x100>;
391 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
393 power-domains = <&pd_a3sp>;
398 mmcif0: mmc@ee200000 {
399 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
400 reg = <0 0xee200000 0 0x80>;
401 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
403 power-domains = <&pd_a3sp>;
408 mmcif1: mmc@ee220000 {
409 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
410 reg = <0 0xee220000 0 0x80>;
411 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
413 power-domains = <&pd_a3sp>;
418 gic: interrupt-controller@f1001000 {
419 compatible = "arm,gic-400";
420 #interrupt-cells = <3>;
421 #address-cells = <0>;
422 interrupt-controller;
423 reg = <0 0xf1001000 0 0x1000>,
424 <0 0xf1002000 0 0x2000>,
425 <0 0xf1004000 0 0x2000>,
426 <0 0xf1006000 0 0x2000>;
427 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
428 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
430 power-domains = <&pd_c4>;
434 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
436 #address-cells = <1>;
438 ranges = <0 0 0 0x20000000>;
439 reg = <0 0xfec10000 0 0x400>;
441 power-domains = <&pd_c4>;
445 #address-cells = <2>;
449 /* External root clocks */
451 compatible = "fixed-clock";
453 clock-frequency = <32768>;
456 compatible = "fixed-clock";
458 clock-frequency = <25000000>;
461 compatible = "fixed-clock";
463 clock-frequency = <48000000>;
466 compatible = "fixed-clock";
468 /* This value must be overridden by the board. */
469 clock-frequency = <0>;
472 compatible = "fixed-clock";
474 /* This value must be overridden by the board. */
475 clock-frequency = <0>;
478 /* Special CPG clocks */
479 cpg_clocks: cpg_clocks@e6150000 {
480 compatible = "renesas,r8a73a4-cpg-clocks";
481 reg = <0 0xe6150000 0 0x10000>;
482 clocks = <&extal1_clk>, <&extal2_clk>;
484 clock-output-names = "main", "pll0", "pll1", "pll2",
485 "pll2s", "pll2h", "z", "z2",
486 "i", "m3", "b", "m1", "m2",
490 /* Variable factor clocks (DIV6) */
491 zb_clk: zb_clk@e6150010 {
492 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
493 reg = <0 0xe6150010 0 4>;
494 clocks = <&pll1_div2_clk>, <0>,
495 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
497 clock-output-names = "zb";
499 sdhi0_clk: sdhi0ck@e6150074 {
500 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
501 reg = <0 0xe6150074 0 4>;
502 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
506 sdhi1_clk: sdhi1ck@e6150078 {
507 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
508 reg = <0 0xe6150078 0 4>;
509 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
513 sdhi2_clk: sdhi2ck@e615007c {
514 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
515 reg = <0 0xe615007c 0 4>;
516 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
520 mmc0_clk: mmc0@e6150240 {
521 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
522 reg = <0 0xe6150240 0 4>;
523 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
527 mmc1_clk: mmc1@e6150244 {
528 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
529 reg = <0 0xe6150244 0 4>;
530 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
534 vclk1_clk: vclk1@e6150008 {
535 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
536 reg = <0 0xe6150008 0 4>;
537 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
538 <0>, <&extal2_clk>, <&main_div2_clk>,
539 <&extalr_clk>, <0>, <0>;
542 vclk2_clk: vclk2@e615000c {
543 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
544 reg = <0 0xe615000c 0 4>;
545 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
546 <0>, <&extal2_clk>, <&main_div2_clk>,
547 <&extalr_clk>, <0>, <0>;
550 vclk3_clk: vclk3@e615001c {
551 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
552 reg = <0 0xe615001c 0 4>;
553 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
554 <0>, <&extal2_clk>, <&main_div2_clk>,
555 <&extalr_clk>, <0>, <0>;
558 vclk4_clk: vclk4@e6150014 {
559 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
560 reg = <0 0xe6150014 0 4>;
561 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
562 <0>, <&extal2_clk>, <&main_div2_clk>,
563 <&extalr_clk>, <0>, <0>;
566 vclk5_clk: vclk5@e6150034 {
567 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
568 reg = <0 0xe6150034 0 4>;
569 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
570 <0>, <&extal2_clk>, <&main_div2_clk>,
571 <&extalr_clk>, <0>, <0>;
574 fsia_clk: fsia@e6150018 {
575 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
576 reg = <0 0xe6150018 0 4>;
577 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
581 fsib_clk: fsib@e6150090 {
582 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
583 reg = <0 0xe6150090 0 4>;
584 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
588 mp_clk: mp@e6150080 {
589 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
590 reg = <0 0xe6150080 0 4>;
591 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
592 <&extal2_clk>, <&extal2_clk>;
595 m4_clk: m4@e6150098 {
596 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
597 reg = <0 0xe6150098 0 4>;
598 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
601 hsi_clk: hsi@e615026c {
602 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
603 reg = <0 0xe615026c 0 4>;
604 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
605 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
608 spuv_clk: spuv@e6150094 {
609 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
610 reg = <0 0xe6150094 0 4>;
611 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
612 <&extal2_clk>, <&extal2_clk>;
616 /* Fixed factor clocks */
617 main_div2_clk: main_div2 {
618 compatible = "fixed-factor-clock";
619 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
624 pll0_div2_clk: pll0_div2 {
625 compatible = "fixed-factor-clock";
626 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
631 pll1_div2_clk: pll1_div2 {
632 compatible = "fixed-factor-clock";
633 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
638 extal1_div2_clk: extal1_div2 {
639 compatible = "fixed-factor-clock";
640 clocks = <&extal1_clk>;
647 mstp2_clks: mstp2_clks@e6150138 {
648 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
649 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
650 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
651 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
654 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
655 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
656 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
660 "scifa0", "scifa1", "scifb0", "scifb1",
661 "scifb2", "scifb3", "dmac";
663 mstp3_clks: mstp3_clks@e615013c {
664 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
665 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
666 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
667 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
668 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
669 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
670 R8A73A4_CLK_HP>, <&cpg_clocks
671 R8A73A4_CLK_HP>, <&extalr_clk>;
674 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
675 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
676 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
677 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
678 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
682 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
683 "mmcif0", "iic6", "iic7", "iic0", "iic1",
686 mstp4_clks: mstp4_clks@e6150140 {
687 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
688 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
689 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
691 <&cpg_clocks R8A73A4_CLK_HP>,
692 <&cpg_clocks R8A73A4_CLK_HP>;
695 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
696 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
700 "irqc", "intc-sys", "iic5", "iic4", "iic3";
702 mstp5_clks: mstp5_clks@e6150144 {
703 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
704 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
705 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
708 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
715 prr: chipid@ff000044 {
716 compatible = "renesas,prr";
717 reg = <0 0xff000044 0 4>;
720 sysc: system-controller@e6180000 {
721 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
722 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
726 #address-cells = <1>;
728 #power-domain-cells = <0>;
732 #address-cells = <1>;
734 #power-domain-cells = <0>;
738 #power-domain-cells = <0>;
743 #power-domain-cells = <0>;
748 #address-cells = <1>;
750 #power-domain-cells = <0>;
754 #power-domain-cells = <0>;
760 #address-cells = <1>;
762 #power-domain-cells = <0>;
766 #power-domain-cells = <0>;
772 #address-cells = <1>;
774 #power-domain-cells = <0>;
778 #power-domain-cells = <0>;
785 #power-domain-cells = <0>;
790 #power-domain-cells = <0>;
795 #power-domain-cells = <0>;
800 #address-cells = <1>;
802 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
812 #power-domain-cells = <0>;
817 #power-domain-cells = <0>;
822 #address-cells = <1>;
824 #power-domain-cells = <0>;
828 #power-domain-cells = <0>;
833 #power-domain-cells = <0>;
839 #power-domain-cells = <0>;
844 #address-cells = <1>;
846 #power-domain-cells = <0>;
850 #power-domain-cells = <0>;
855 #power-domain-cells = <0>;