arch/arm/boot/dts/r7s9210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R7S9210 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corporation
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
  11
  12 / {
  13         compatible = "renesas,r7s9210";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         /* External clocks */
  19         extal_clk: extal {
  20                 #clock-cells = <0>;
  21                 compatible = "fixed-clock";
  22                 /* Value must be set by board */
  23                 clock-frequency = <0>;
  24         };
  25
  26         rtc_x1_clk: rtc_x1 {
  27                 #clock-cells = <0>;
  28                 compatible = "fixed-clock";
  29                 /* If clk present, value (32678) must be set by board */
  30                 clock-frequency = <0>;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a9";
  40                         reg = <0>;
  41                         clock-frequency = <528000000>;
  42                         next-level-cache = <&L2>;
  43                 };
  44         };
  45
  46         soc {
  47                 compatible = "simple-bus";
  48                 interrupt-parent = <&gic>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges;
  53
  54                 L2: cache-controller@1f003000 {
  55                         compatible = "arm,pl310-cache";
  56                         reg = <0x1f003000 0x1000>;
  57                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  58                         arm,early-bresp-disable;
  59                         arm,full-line-zero-disable;
  60                         cache-unified;
  61                         cache-level = <2>;
  62                 };
  63
  64                 scif0: serial@e8007000 {
  65                         compatible = "renesas,scif-r7s9210";
  66                         reg = <0xe8007000 0x18>;
  67                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
  71                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
  72                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
  73                         interrupt-names = "eri", "rxi", "txi",
  74                                           "bri", "dri", "tei";
  75                         clocks = <&cpg CPG_MOD 47>;
  76                         clock-names = "fck";
  77                         power-domains = <&cpg>;
  78                         status = "disabled";
  79                 };
  80
  81                 scif1: serial@e8007800 {
  82                         compatible = "renesas,scif-r7s9210";
  83                         reg = <0xe8007800 0x18>;
  84                         interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
  89                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
  90                         interrupt-names = "eri", "rxi", "txi",
  91                                           "bri", "dri", "tei";
  92                         clocks = <&cpg CPG_MOD 46>;
  93                         clock-names = "fck";
  94                         power-domains = <&cpg>;
  95                         status = "disabled";
  96                 };
  97
  98                 scif2: serial@e8008000 {
  99                         compatible = "renesas,scif-r7s9210";
 100                         reg = <0xe8008000 0x18>;
 101                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 107                         interrupt-names = "eri", "rxi", "txi",
 108                                           "bri", "dri", "tei";
 109                         clocks = <&cpg CPG_MOD 45>;
 110                         clock-names = "fck";
 111                         power-domains = <&cpg>;
 112                         status = "disabled";
 113                 };
 114
 115                 scif3: serial@e8008800 {
 116                         compatible = "renesas,scif-r7s9210";
 117                         reg = <0xe8008800 0x18>;
 118                         interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
 123                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 124                         interrupt-names = "eri", "rxi", "txi",
 125                                           "bri", "dri", "tei";
 126                         clocks = <&cpg CPG_MOD 44>;
 127                         clock-names = "fck";
 128                         power-domains = <&cpg>;
 129                         status = "disabled";
 130                 };
 131
 132                 scif4: serial@e8009000 {
 133                         compatible = "renesas,scif-r7s9210";
 134                         reg = <0xe8009000 0x18>;
 135                         interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
 139                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
 141                         interrupt-names = "eri", "rxi", "txi",
 142                                           "bri", "dri", "tei";
 143                         clocks = <&cpg CPG_MOD 43>;
 144                         clock-names = "fck";
 145                         power-domains = <&cpg>;
 146                         status = "disabled";
 147                 };
 148
 149                 ostm0: timer@e803b000 {
 150                         compatible = "renesas,r7s9210-ostm", "renesas,ostm";
 151                         reg = <0xe803b000 0x30>;
 152                         interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
 153                         clocks = <&cpg CPG_MOD 36>;
 154                         clock-names = "ostm0";
 155                         power-domains = <&cpg>;
 156                         status = "disabled";
 157                 };
 158
 159                 ostm1: timer@e803c000 {
 160                         compatible = "renesas,r7s9210-ostm", "renesas,ostm";
 161                         reg = <0xe803c000 0x30>;
 162                         interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
 163                         clocks = <&cpg CPG_MOD 35>;
 164                         clock-names = "ostm1";
 165                         power-domains = <&cpg>;
 166                         status = "disabled";
 167                 };
 168
 169                 ostm2: timer@e803d000 {
 170                         compatible = "renesas,r7s9210-ostm", "renesas,ostm";
 171                         reg = <0xe803d000 0x30>;
 172                         interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
 173                         clocks = <&cpg CPG_MOD 34>;
 174                         clock-names = "ostm2";
 175                         power-domains = <&cpg>;
 176                         status = "disabled";
 177                 };
 178
 179                 gic: interrupt-controller@e8221000 {
 180                         compatible = "arm,gic-400";
 181                         #interrupt-cells = <3>;
 182                         #address-cells = <0>;
 183                         interrupt-controller;
 184                         reg = <0xe8221000 0x1000>,
 185                               <0xe8222000 0x1000>;
 186                 };
 187
 188                 cpg: clock-controller@fcfe0010 {
 189                         compatible = "renesas,r7s9210-cpg-mssr";
 190                         reg = <0xfcfe0010 0x455>;
 191                         clocks = <&extal_clk>;
 192                         clock-names = "extal";
 193                         #clock-cells = <2>;
 194                         #power-domain-cells = <0>;
 195                 };
 196
 197                 wdt: watchdog@fcfe7000 {
 198                         compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
 199                         reg = <0xfcfe7000 0x26>;
 200                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
 202                 };
 203
 204                 bsid: chipid@fcfe8004 {
 205                         compatible = "renesas,bsid";
 206                         reg = <0xfcfe8004 4>;
 207                 };
 208
 209                 pinctrl: pin-controller@fcffe000 {
 210                         compatible = "renesas,r7s9210-pinctrl";
 211                         reg = <0xfcffe000 0x1000>;
 212
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                         gpio-ranges = <&pinctrl 0 0 176>;
 216                 };
 217         };
 218 };