arch/arm/boot/dts/r7s9210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R7S9210 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corporation
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
  11
  12 / {
  13         compatible = "renesas,r7s9210";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         /* External clocks */
  19         extal_clk: extal {
  20                 #clock-cells = <0>;
  21                 compatible = "fixed-clock";
  22                 /* Value must be set by board */
  23                 clock-frequency = <0>;
  24         };
  25
  26         rtc_x1_clk: rtc_x1 {
  27                 #clock-cells = <0>;
  28                 compatible = "fixed-clock";
  29                 /* If clk present, value (32678) must be set by board */
  30                 clock-frequency = <0>;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a9";
  40                         reg = <0>;
  41                         clock-frequency = <528000000>;
  42                         next-level-cache = <&L2>;
  43                 };
  44         };
  45
  46         soc {
  47                 compatible = "simple-bus";
  48                 interrupt-parent = <&gic>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges;
  53
  54                 L2: cache-controller@1f003000 {
  55                         compatible = "arm,pl310-cache";
  56                         reg = <0x1f003000 0x1000>;
  57                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  58                         arm,early-bresp-disable;
  59                         arm,full-line-zero-disable;
  60                         cache-unified;
  61                         cache-level = <2>;
  62                 };
  63
  64                 scif0: serial@e8007000 {
  65                         compatible = "renesas,scif-r7s9210";
  66                         reg = <0xe8007000 0x18>;
  67                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
  71                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
  72                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
  73                         interrupt-names = "eri", "rxi", "txi",
  74                                           "bri", "dri", "tei";
  75                         clocks = <&cpg CPG_MOD 47>;
  76                         clock-names = "fck";
  77                         power-domains = <&cpg>;
  78                         status = "disabled";
  79                 };
  80
  81                 scif1: serial@e8007800 {
  82                         compatible = "renesas,scif-r7s9210";
  83                         reg = <0xe8007800 0x18>;
  84                         interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
  89                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
  90                         interrupt-names = "eri", "rxi", "txi",
  91                                           "bri", "dri", "tei";
  92                         clocks = <&cpg CPG_MOD 46>;
  93                         clock-names = "fck";
  94                         power-domains = <&cpg>;
  95                         status = "disabled";
  96                 };
  97
  98                 scif2: serial@e8008000 {
  99                         compatible = "renesas,scif-r7s9210";
 100                         reg = <0xe8008000 0x18>;
 101                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 107                         interrupt-names = "eri", "rxi", "txi",
 108                                           "bri", "dri", "tei";
 109                         clocks = <&cpg CPG_MOD 45>;
 110                         clock-names = "fck";
 111                         power-domains = <&cpg>;
 112                         status = "disabled";
 113                 };
 114
 115                 scif3: serial@e8008800 {
 116                         compatible = "renesas,scif-r7s9210";
 117                         reg = <0xe8008800 0x18>;
 118                         interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
 123                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 124                         interrupt-names = "eri", "rxi", "txi",
 125                                           "bri", "dri", "tei";
 126                         clocks = <&cpg CPG_MOD 44>;
 127                         clock-names = "fck";
 128                         power-domains = <&cpg>;
 129                         status = "disabled";
 130                 };
 131
 132                 scif4: serial@e8009000 {
 133                         compatible = "renesas,scif-r7s9210";
 134                         reg = <0xe8009000 0x18>;
 135                         interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
 139                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
 141                         interrupt-names = "eri", "rxi", "txi",
 142                                           "bri", "dri", "tei";
 143                         clocks = <&cpg CPG_MOD 43>;
 144                         clock-names = "fck";
 145                         power-domains = <&cpg>;
 146                         status = "disabled";
 147                 };
 148
 149                 spi0: spi@e800c800 {
 150                         compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
 151                         reg = <0xe800c800 0x24>;
 152                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
 153                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 154                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
 155                         interrupt-names = "error", "rx", "tx";
 156                         clocks = <&cpg CPG_MOD 97>;
 157                         power-domains = <&cpg>;
 158                         num-cs = <1>;
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         status = "disabled";
 162                 };
 163
 164                 spi1: spi@e800d000 {
 165                         compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
 166                         reg = <0xe800d000 0x24>;
 167                         interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 169                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
 170                         interrupt-names = "error", "rx", "tx";
 171                         clocks = <&cpg CPG_MOD 96>;
 172                         power-domains = <&cpg>;
 173                         num-cs = <1>;
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         status = "disabled";
 177                 };
 178
 179                 spi2: spi@e800d800 {
 180                         compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
 181                         reg = <0xe800d800 0x24>;
 182                         interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
 185                         interrupt-names = "error", "rx", "tx";
 186                         clocks = <&cpg CPG_MOD 95>;
 187                         power-domains = <&cpg>;
 188                         num-cs = <1>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         status = "disabled";
 192                 };
 193
 194                 ether0: ethernet@e8204000 {
 195                         compatible = "renesas,ether-r7s9210";
 196                         reg = <0xe8204000 0x200>;
 197                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&cpg CPG_MOD 65>;
 199                         power-domains = <&cpg>;
 200
 201                         phy-mode = "rmii";
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         status = "disabled";
 205                 };
 206
 207                 ether1: ethernet@e8204200 {
 208                         compatible = "renesas,ether-r7s9210";
 209                         reg = <0xe8204200 0x200>;
 210                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 211                         clocks = <&cpg CPG_MOD 64>;
 212                         power-domains = <&cpg>;
 213                         phy-mode = "rmii";
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216                         status = "disabled";
 217                 };
 218
 219                 i2c0: i2c@e803a000 {
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
 223                         reg = <0xe803a000 0x44>;
 224                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
 226                                      <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
 227                                      <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&cpg CPG_MOD 87>;
 233                         power-domains = <&cpg>;
 234                         clock-frequency = <100000>;
 235                         status = "disabled";
 236                 };
 237
 238                 i2c1: i2c@e803a400 {
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
 242                         reg = <0xe803a400 0x44>;
 243                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
 245                                      <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
 246                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 251                         clocks = <&cpg CPG_MOD 86>;
 252                         power-domains = <&cpg>;
 253                         clock-frequency = <100000>;
 254                         status = "disabled";
 255                 };
 256
 257                 i2c2: i2c@e803a800 {
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                         compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
 261                         reg = <0xe803a800 0x44>;
 262                         interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 263                                      <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
 264                                      <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
 265                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 266                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 268                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 269                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 270                         clocks = <&cpg CPG_MOD 85>;
 271                         power-domains = <&cpg>;
 272                         clock-frequency = <100000>;
 273                         status = "disabled";
 274                 };
 275
 276                 i2c3: i2c@e803ac00 {
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
 280                         reg = <0xe803ac00 0x44>;
 281                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
 283                                      <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
 284                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 287                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 288                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 289                         clocks = <&cpg CPG_MOD 84>;
 290                         power-domains = <&cpg>;
 291                         clock-frequency = <100000>;
 292                         status = "disabled";
 293                 };
 294
 295                 ostm0: timer@e803b000 {
 296                         compatible = "renesas,r7s9210-ostm", "renesas,ostm";
 297                         reg = <0xe803b000 0x30>;
 298                         interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
 299                         clocks = <&cpg CPG_MOD 36>;
 300                         clock-names = "ostm0";
 301                         power-domains = <&cpg>;
 302                         status = "disabled";
 303                 };
 304
 305                 ostm1: timer@e803c000 {
 306                         compatible = "renesas,r7s9210-ostm", "renesas,ostm";
 307                         reg = <0xe803c000 0x30>;
 308                         interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
 309                         clocks = <&cpg CPG_MOD 35>;
 310                         clock-names = "ostm1";
 311                         power-domains = <&cpg>;
 312                         status = "disabled";
 313                 };
 314
 315                 ostm2: timer@e803d000 {
 316                         compatible = "renesas,r7s9210-ostm", "renesas,ostm";
 317                         reg = <0xe803d000 0x30>;
 318                         interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
 319                         clocks = <&cpg CPG_MOD 34>;
 320                         clock-names = "ostm2";
 321                         power-domains = <&cpg>;
 322                         status = "disabled";
 323                 };
 324
 325                 gic: interrupt-controller@e8221000 {
 326                         compatible = "arm,gic-400";
 327                         #interrupt-cells = <3>;
 328                         #address-cells = <0>;
 329                         interrupt-controller;
 330                         reg = <0xe8221000 0x1000>,
 331                               <0xe8222000 0x1000>;
 332                 };
 333
 334                 cpg: clock-controller@fcfe0010 {
 335                         compatible = "renesas,r7s9210-cpg-mssr";
 336                         reg = <0xfcfe0010 0x455>;
 337                         clocks = <&extal_clk>;
 338                         clock-names = "extal";
 339                         #clock-cells = <2>;
 340                         #power-domain-cells = <0>;
 341                 };
 342
 343                 wdt: watchdog@fcfe7000 {
 344                         compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
 345                         reg = <0xfcfe7000 0x26>;
 346                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
 348                 };
 349
 350                 bsid: chipid@fcfe8004 {
 351                         compatible = "renesas,bsid";
 352                         reg = <0xfcfe8004 4>;
 353                 };
 354
 355                 pinctrl: pin-controller@fcffe000 {
 356                         compatible = "renesas,r7s9210-pinctrl";
 357                         reg = <0xfcffe000 0x1000>;
 358
 359                         gpio-controller;
 360                         #gpio-cells = <2>;
 361                         gpio-ranges = <&pinctrl 0 0 176>;
 362                 };
 363         };
 364 };