arch/arm/boot/dts/r7s72100.dtsi

   1 /*
   2  * Device Tree Source for the r7s72100 SoC
   3  *
   4  * Copyright (C) 2013-14 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r7s72100-clock.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r7s72100";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 spi0 = &spi0;
  27                 spi1 = &spi1;
  28                 spi2 = &spi2;
  29                 spi3 = &spi3;
  30                 spi4 = &spi4;
  31         };
  32
  33         clocks {
  34                 ranges;
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37
  38                 /* External clocks */
  39                 extal_clk: extal_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         /* If clk present, value must be set by board */
  43                         clock-frequency = <0>;
  44                         clock-output-names = "extal";
  45                 };
  46
  47                 usb_x1_clk: usb_x1_clk {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         /* If clk present, value must be set by board */
  51                         clock-frequency = <0>;
  52                         clock-output-names = "usb_x1";
  53                 };
  54
  55                 /* Special CPG clocks */
  56                 cpg_clocks: cpg_clocks@fcfe0000 {
  57                         #clock-cells = <1>;
  58                         compatible = "renesas,r7s72100-cpg-clocks",
  59                                      "renesas,rz-cpg-clocks";
  60                         reg = <0xfcfe0000 0x18>;
  61                         clocks = <&extal_clk>, <&usb_x1_clk>;
  62                         clock-output-names = "pll", "i", "g";
  63                 };
  64
  65                 /* Fixed factor clocks */
  66                 b_clk: b_clk {
  67                         #clock-cells = <0>;
  68                         compatible = "fixed-factor-clock";
  69                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  70                         clock-mult = <1>;
  71                         clock-div = <3>;
  72                         clock-output-names = "b";
  73                 };
  74                 p1_clk: p1_clk {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-factor-clock";
  77                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  78                         clock-mult = <1>;
  79                         clock-div = <6>;
  80                         clock-output-names = "p1";
  81                 };
  82                 p0_clk: p0_clk {
  83                         #clock-cells = <0>;
  84                         compatible = "fixed-factor-clock";
  85                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  86                         clock-mult = <1>;
  87                         clock-div = <12>;
  88                         clock-output-names = "p0";
  89                 };
  90
  91                 /* MSTP clocks */
  92                 mstp3_clks: mstp3_clks@fcfe0420 {
  93                         #clock-cells = <1>;
  94                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
  95                         reg = <0xfcfe0420 4>;
  96                         clocks = <&p0_clk>;
  97                         clock-indices = <R7S72100_CLK_MTU2>;
  98                         clock-output-names = "mtu2";
  99                 };
 100
 101                 mstp4_clks: mstp4_clks@fcfe0424 {
 102                         #clock-cells = <1>;
 103                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 104                         reg = <0xfcfe0424 4>;
 105                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 106                                  <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 107                         clock-indices = <
 108                                 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
 109                                 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
 110                         >;
 111                         clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
 112                 };
 113
 114                 mstp9_clks: mstp9_clks@fcfe0438 {
 115                         #clock-cells = <1>;
 116                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 117                         reg = <0xfcfe0438 4>;
 118                         clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
 119                         clock-indices = <
 120                                 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
 121                         >;
 122                         clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
 123                 };
 124         };
 125
 126         cpus {
 127                 #address-cells = <1>;
 128                 #size-cells = <0>;
 129
 130                 cpu@0 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a9";
 133                         reg = <0>;
 134                 };
 135         };
 136
 137         gic: interrupt-controller@e8201000 {
 138                 compatible = "arm,cortex-a9-gic";
 139                 #interrupt-cells = <3>;
 140                 #address-cells = <0>;
 141                 interrupt-controller;
 142                 reg = <0xe8201000 0x1000>,
 143                         <0xe8202000 0x1000>;
 144         };
 145
 146         i2c0: i2c@fcfee000 {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 150                 reg = <0xfcfee000 0x44>;
 151                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
 152                              <0 158 IRQ_TYPE_EDGE_RISING>,
 153                              <0 159 IRQ_TYPE_EDGE_RISING>,
 154                              <0 160 IRQ_TYPE_LEVEL_HIGH>,
 155                              <0 161 IRQ_TYPE_LEVEL_HIGH>,
 156                              <0 162 IRQ_TYPE_LEVEL_HIGH>,
 157                              <0 163 IRQ_TYPE_LEVEL_HIGH>,
 158                              <0 164 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 160                 clock-frequency = <100000>;
 161                 status = "disabled";
 162         };
 163
 164         i2c1: i2c@fcfee400 {
 165                 #address-cells = <1>;
 166                 #size-cells = <0>;
 167                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 168                 reg = <0xfcfee400 0x44>;
 169                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
 170                              <0 166 IRQ_TYPE_EDGE_RISING>,
 171                              <0 167 IRQ_TYPE_EDGE_RISING>,
 172                              <0 168 IRQ_TYPE_LEVEL_HIGH>,
 173                              <0 169 IRQ_TYPE_LEVEL_HIGH>,
 174                              <0 170 IRQ_TYPE_LEVEL_HIGH>,
 175                              <0 171 IRQ_TYPE_LEVEL_HIGH>,
 176                              <0 172 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 178                 clock-frequency = <100000>;
 179                 status = "disabled";
 180         };
 181
 182         i2c2: i2c@fcfee800 {
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 186                 reg = <0xfcfee800 0x44>;
 187                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
 188                              <0 174 IRQ_TYPE_EDGE_RISING>,
 189                              <0 175 IRQ_TYPE_EDGE_RISING>,
 190                              <0 176 IRQ_TYPE_LEVEL_HIGH>,
 191                              <0 177 IRQ_TYPE_LEVEL_HIGH>,
 192                              <0 178 IRQ_TYPE_LEVEL_HIGH>,
 193                              <0 179 IRQ_TYPE_LEVEL_HIGH>,
 194                              <0 180 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 196                 clock-frequency = <100000>;
 197                 status = "disabled";
 198         };
 199
 200         i2c3: i2c@fcfeec00 {
 201                 #address-cells = <1>;
 202                 #size-cells = <0>;
 203                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 204                 reg = <0xfcfeec00 0x44>;
 205                 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
 206                              <0 182 IRQ_TYPE_EDGE_RISING>,
 207                              <0 183 IRQ_TYPE_EDGE_RISING>,
 208                              <0 184 IRQ_TYPE_LEVEL_HIGH>,
 209                              <0 185 IRQ_TYPE_LEVEL_HIGH>,
 210                              <0 186 IRQ_TYPE_LEVEL_HIGH>,
 211                              <0 187 IRQ_TYPE_LEVEL_HIGH>,
 212                              <0 188 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 214                 clock-frequency = <100000>;
 215                 status = "disabled";
 216         };
 217
 218         scif0: serial@e8007000 {
 219                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 220                 reg = <0xe8007000 64>;
 221                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>,
 222                              <0 191 IRQ_TYPE_LEVEL_HIGH>,
 223                              <0 192 IRQ_TYPE_LEVEL_HIGH>,
 224                              <0 189 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
 226                 clock-names = "sci_ick";
 227                 status = "disabled";
 228         };
 229
 230         scif1: serial@e8007800 {
 231                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 232                 reg = <0xe8007800 64>;
 233                 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 195 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 196 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 193 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
 238                 clock-names = "sci_ick";
 239                 status = "disabled";
 240         };
 241
 242         scif2: serial@e8008000 {
 243                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 244                 reg = <0xe8008000 64>;
 245                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
 246                              <0 199 IRQ_TYPE_LEVEL_HIGH>,
 247                              <0 200 IRQ_TYPE_LEVEL_HIGH>,
 248                              <0 197 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
 250                 clock-names = "sci_ick";
 251                 status = "disabled";
 252         };
 253
 254         scif3: serial@e8008800 {
 255                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 256                 reg = <0xe8008800 64>;
 257                 interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>,
 258                              <0 203 IRQ_TYPE_LEVEL_HIGH>,
 259                              <0 204 IRQ_TYPE_LEVEL_HIGH>,
 260                              <0 201 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
 262                 clock-names = "sci_ick";
 263                 status = "disabled";
 264         };
 265
 266         scif4: serial@e8009000 {
 267                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 268                 reg = <0xe8009000 64>;
 269                 interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>,
 270                              <0 207 IRQ_TYPE_LEVEL_HIGH>,
 271                              <0 208 IRQ_TYPE_LEVEL_HIGH>,
 272                              <0 205 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
 274                 clock-names = "sci_ick";
 275                 status = "disabled";
 276         };
 277
 278         scif5: serial@e8009800 {
 279                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 280                 reg = <0xe8009800 64>;
 281                 interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>,
 282                              <0 211 IRQ_TYPE_LEVEL_HIGH>,
 283                              <0 212 IRQ_TYPE_LEVEL_HIGH>,
 284                              <0 209 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
 286                 clock-names = "sci_ick";
 287                 status = "disabled";
 288         };
 289
 290         scif6: serial@e800a000 {
 291                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 292                 reg = <0xe800a000 64>;
 293                 interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>,
 294                              <0 215 IRQ_TYPE_LEVEL_HIGH>,
 295                              <0 216 IRQ_TYPE_LEVEL_HIGH>,
 296                              <0 213 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
 298                 clock-names = "sci_ick";
 299                 status = "disabled";
 300         };
 301
 302         scif7: serial@e800a800 {
 303                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 304                 reg = <0xe800a800 64>;
 305                 interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
 306                              <0 219 IRQ_TYPE_LEVEL_HIGH>,
 307                              <0 220 IRQ_TYPE_LEVEL_HIGH>,
 308                              <0 217 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
 310                 clock-names = "sci_ick";
 311                 status = "disabled";
 312         };
 313
 314         spi0: spi@e800c800 {
 315                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 316                 reg = <0xe800c800 0x24>;
 317                 interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
 318                              <0 239 IRQ_TYPE_LEVEL_HIGH>,
 319                              <0 240 IRQ_TYPE_LEVEL_HIGH>;
 320                 interrupt-names = "error", "rx", "tx";
 321                 num-cs = <1>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 status = "disabled";
 325         };
 326
 327         spi1: spi@e800d000 {
 328                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 329                 reg = <0xe800d000 0x24>;
 330                 interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,
 331                              <0 242 IRQ_TYPE_LEVEL_HIGH>,
 332                              <0 243 IRQ_TYPE_LEVEL_HIGH>;
 333                 interrupt-names = "error", "rx", "tx";
 334                 num-cs = <1>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 status = "disabled";
 338         };
 339
 340         spi2: spi@e800d800 {
 341                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 342                 reg = <0xe800d800 0x24>;
 343                 interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
 344                              <0 245 IRQ_TYPE_LEVEL_HIGH>,
 345                              <0 246 IRQ_TYPE_LEVEL_HIGH>;
 346                 interrupt-names = "error", "rx", "tx";
 347                 num-cs = <1>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 status = "disabled";
 351         };
 352
 353         spi3: spi@e800e000 {
 354                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 355                 reg = <0xe800e000 0x24>;
 356                 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,
 357                              <0 248 IRQ_TYPE_LEVEL_HIGH>,
 358                              <0 249 IRQ_TYPE_LEVEL_HIGH>;
 359                 interrupt-names = "error", "rx", "tx";
 360                 num-cs = <1>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 status = "disabled";
 364         };
 365
 366         spi4: spi@e800e800 {
 367                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 368                 reg = <0xe800e800 0x24>;
 369                 interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,
 370                              <0 251 IRQ_TYPE_LEVEL_HIGH>,
 371                              <0 252 IRQ_TYPE_LEVEL_HIGH>;
 372                 interrupt-names = "error", "rx", "tx";
 373                 num-cs = <1>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 status = "disabled";
 377         };
 378 };