2 * Device Tree Source for the r7s72100 SoC
4 * Copyright (C) 2013-14 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r7s72100-clock.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,r7s72100";
17 interrupt-parent = <&gic>;
39 extal_clk: extal_clk {
41 compatible = "fixed-clock";
42 /* If clk present, value must be set by board */
43 clock-frequency = <0>;
44 clock-output-names = "extal";
47 usb_x1_clk: usb_x1_clk {
49 compatible = "fixed-clock";
50 /* If clk present, value must be set by board */
51 clock-frequency = <0>;
52 clock-output-names = "usb_x1";
55 /* Special CPG clocks */
56 cpg_clocks: cpg_clocks@fcfe0000 {
58 compatible = "renesas,r7s72100-cpg-clocks",
59 "renesas,rz-cpg-clocks";
60 reg = <0xfcfe0000 0x18>;
61 clocks = <&extal_clk>, <&usb_x1_clk>;
62 clock-output-names = "pll", "i", "g";
65 /* Fixed factor clocks */
68 compatible = "fixed-factor-clock";
69 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
72 clock-output-names = "b";
76 compatible = "fixed-factor-clock";
77 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
80 clock-output-names = "p1";
84 compatible = "fixed-factor-clock";
85 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
88 clock-output-names = "p0";
92 mstp3_clks: mstp3_clks@fcfe0420 {
94 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
97 clock-indices = <R7S72100_CLK_MTU2>;
98 clock-output-names = "mtu2";
101 mstp4_clks: mstp4_clks@fcfe0424 {
103 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
104 reg = <0xfcfe0424 4>;
105 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
106 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
108 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
109 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
111 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
116 #address-cells = <1>;
121 compatible = "arm,cortex-a9";
126 gic: interrupt-controller@e8201000 {
127 compatible = "arm,cortex-a9-gic";
128 #interrupt-cells = <3>;
129 #address-cells = <0>;
130 interrupt-controller;
131 reg = <0xe8201000 0x1000>,
136 #address-cells = <1>;
138 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
139 reg = <0xfcfee000 0x44>;
140 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
141 <0 158 IRQ_TYPE_EDGE_RISING>,
142 <0 159 IRQ_TYPE_EDGE_RISING>,
143 <0 160 IRQ_TYPE_LEVEL_HIGH>,
144 <0 161 IRQ_TYPE_LEVEL_HIGH>,
145 <0 162 IRQ_TYPE_LEVEL_HIGH>,
146 <0 163 IRQ_TYPE_LEVEL_HIGH>,
147 <0 164 IRQ_TYPE_LEVEL_HIGH>;
148 clock-frequency = <100000>;
153 #address-cells = <1>;
155 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
156 reg = <0xfcfee400 0x44>;
157 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
158 <0 166 IRQ_TYPE_EDGE_RISING>,
159 <0 167 IRQ_TYPE_EDGE_RISING>,
160 <0 168 IRQ_TYPE_LEVEL_HIGH>,
161 <0 169 IRQ_TYPE_LEVEL_HIGH>,
162 <0 170 IRQ_TYPE_LEVEL_HIGH>,
163 <0 171 IRQ_TYPE_LEVEL_HIGH>,
164 <0 172 IRQ_TYPE_LEVEL_HIGH>;
165 clock-frequency = <100000>;
170 #address-cells = <1>;
172 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
173 reg = <0xfcfee800 0x44>;
174 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
175 <0 174 IRQ_TYPE_EDGE_RISING>,
176 <0 175 IRQ_TYPE_EDGE_RISING>,
177 <0 176 IRQ_TYPE_LEVEL_HIGH>,
178 <0 177 IRQ_TYPE_LEVEL_HIGH>,
179 <0 178 IRQ_TYPE_LEVEL_HIGH>,
180 <0 179 IRQ_TYPE_LEVEL_HIGH>,
181 <0 180 IRQ_TYPE_LEVEL_HIGH>;
182 clock-frequency = <100000>;
187 #address-cells = <1>;
189 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
190 reg = <0xfcfeec00 0x44>;
191 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
192 <0 182 IRQ_TYPE_EDGE_RISING>,
193 <0 183 IRQ_TYPE_EDGE_RISING>,
194 <0 184 IRQ_TYPE_LEVEL_HIGH>,
195 <0 185 IRQ_TYPE_LEVEL_HIGH>,
196 <0 186 IRQ_TYPE_LEVEL_HIGH>,
197 <0 187 IRQ_TYPE_LEVEL_HIGH>,
198 <0 188 IRQ_TYPE_LEVEL_HIGH>;
199 clock-frequency = <100000>;
203 scif0: serial@e8007000 {
204 compatible = "renesas,scif-r7s72100", "renesas,scif";
205 reg = <0xe8007000 64>;
206 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>,
207 <0 191 IRQ_TYPE_LEVEL_HIGH>,
208 <0 192 IRQ_TYPE_LEVEL_HIGH>,
209 <0 189 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
211 clock-names = "sci_ick";
215 scif1: serial@e8007800 {
216 compatible = "renesas,scif-r7s72100", "renesas,scif";
217 reg = <0xe8007800 64>;
218 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>,
219 <0 195 IRQ_TYPE_LEVEL_HIGH>,
220 <0 196 IRQ_TYPE_LEVEL_HIGH>,
221 <0 193 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
223 clock-names = "sci_ick";
227 scif2: serial@e8008000 {
228 compatible = "renesas,scif-r7s72100", "renesas,scif";
229 reg = <0xe8008000 64>;
230 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
231 <0 199 IRQ_TYPE_LEVEL_HIGH>,
232 <0 200 IRQ_TYPE_LEVEL_HIGH>,
233 <0 197 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
235 clock-names = "sci_ick";
239 scif3: serial@e8008800 {
240 compatible = "renesas,scif-r7s72100", "renesas,scif";
241 reg = <0xe8008800 64>;
242 interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>,
243 <0 203 IRQ_TYPE_LEVEL_HIGH>,
244 <0 204 IRQ_TYPE_LEVEL_HIGH>,
245 <0 201 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
247 clock-names = "sci_ick";
251 scif4: serial@e8009000 {
252 compatible = "renesas,scif-r7s72100", "renesas,scif";
253 reg = <0xe8009000 64>;
254 interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>,
255 <0 207 IRQ_TYPE_LEVEL_HIGH>,
256 <0 208 IRQ_TYPE_LEVEL_HIGH>,
257 <0 205 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
259 clock-names = "sci_ick";
263 scif5: serial@e8009800 {
264 compatible = "renesas,scif-r7s72100", "renesas,scif";
265 reg = <0xe8009800 64>;
266 interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>,
267 <0 211 IRQ_TYPE_LEVEL_HIGH>,
268 <0 212 IRQ_TYPE_LEVEL_HIGH>,
269 <0 209 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
271 clock-names = "sci_ick";
275 scif6: serial@e800a000 {
276 compatible = "renesas,scif-r7s72100", "renesas,scif";
277 reg = <0xe800a000 64>;
278 interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>,
279 <0 215 IRQ_TYPE_LEVEL_HIGH>,
280 <0 216 IRQ_TYPE_LEVEL_HIGH>,
281 <0 213 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
283 clock-names = "sci_ick";
287 scif7: serial@e800a800 {
288 compatible = "renesas,scif-r7s72100", "renesas,scif";
289 reg = <0xe800a800 64>;
290 interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
291 <0 219 IRQ_TYPE_LEVEL_HIGH>,
292 <0 220 IRQ_TYPE_LEVEL_HIGH>,
293 <0 217 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
295 clock-names = "sci_ick";
300 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
301 reg = <0xe800c800 0x24>;
302 interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
303 <0 239 IRQ_TYPE_LEVEL_HIGH>,
304 <0 240 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error", "rx", "tx";
307 #address-cells = <1>;
313 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
314 reg = <0xe800d000 0x24>;
315 interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,
316 <0 242 IRQ_TYPE_LEVEL_HIGH>,
317 <0 243 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-names = "error", "rx", "tx";
320 #address-cells = <1>;
326 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
327 reg = <0xe800d800 0x24>;
328 interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
329 <0 245 IRQ_TYPE_LEVEL_HIGH>,
330 <0 246 IRQ_TYPE_LEVEL_HIGH>;
331 interrupt-names = "error", "rx", "tx";
333 #address-cells = <1>;
339 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
340 reg = <0xe800e000 0x24>;
341 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,
342 <0 248 IRQ_TYPE_LEVEL_HIGH>,
343 <0 249 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-names = "error", "rx", "tx";
346 #address-cells = <1>;
352 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
353 reg = <0xe800e800 0x24>;
354 interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,
355 <0 251 IRQ_TYPE_LEVEL_HIGH>,
356 <0 252 IRQ_TYPE_LEVEL_HIGH>;
357 interrupt-names = "error", "rx", "tx";
359 #address-cells = <1>;