1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 model = "Qualcomm IPQ8064";
18 compatible = "qcom,ipq8064";
19 interrupt-parent = <&intc>;
26 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v1";
30 next-level-cache = <&L2>;
36 compatible = "qcom,krait";
37 enable-method = "qcom,kpss-acc-v1";
40 next-level-cache = <&L2>;
53 polling-delay-passive = <0>;
55 thermal-sensors = <&tsens 0>;
59 temperature = <105000>;
65 temperature = <95000>;
73 polling-delay-passive = <0>;
75 thermal-sensors = <&tsens 1>;
79 temperature = <105000>;
85 temperature = <95000>;
93 polling-delay-passive = <0>;
95 thermal-sensors = <&tsens 2>;
99 temperature = <105000>;
105 temperature = <95000>;
113 polling-delay-passive = <0>;
115 thermal-sensors = <&tsens 3>;
119 temperature = <105000>;
125 temperature = <95000>;
133 polling-delay-passive = <0>;
135 thermal-sensors = <&tsens 4>;
139 temperature = <105000>;
145 temperature = <95000>;
153 polling-delay-passive = <0>;
155 thermal-sensors = <&tsens 5>;
159 temperature = <105000>;
165 temperature = <95000>;
173 polling-delay-passive = <0>;
175 thermal-sensors = <&tsens 6>;
179 temperature = <105000>;
185 temperature = <95000>;
193 polling-delay-passive = <0>;
195 thermal-sensors = <&tsens 7>;
199 temperature = <105000>;
205 temperature = <95000>;
213 polling-delay-passive = <0>;
215 thermal-sensors = <&tsens 8>;
219 temperature = <105000>;
225 temperature = <95000>;
233 polling-delay-passive = <0>;
235 thermal-sensors = <&tsens 9>;
239 temperature = <105000>;
245 temperature = <95000>;
253 polling-delay-passive = <0>;
255 thermal-sensors = <&tsens 10>;
259 temperature = <105000>;
265 temperature = <95000>;
274 device_type = "memory";
279 compatible = "qcom,krait-pmu";
280 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
281 IRQ_TYPE_LEVEL_HIGH)>;
285 #address-cells = <1>;
290 reg = <0x40000000 0x1000000>;
294 smem: smem@41000000 {
295 reg = <0x41000000 0x200000>;
301 cxo_board: cxo_board {
302 compatible = "fixed-clock";
304 clock-frequency = <25000000>;
307 pxo_board: pxo_board {
308 compatible = "fixed-clock";
310 clock-frequency = <25000000>;
313 sleep_clk: sleep_clk {
314 compatible = "fixed-clock";
315 clock-frequency = <32768>;
322 compatible = "qcom,scm-ipq806x", "qcom,scm";
327 #address-cells = <1>;
330 compatible = "simple-bus";
333 compatible = "qcom,lpass-cpu";
335 clocks = <&lcc AHBIX_CLK>,
338 clock-names = "ahbix-clk",
341 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
342 interrupt-names = "lpass-irq-lpaif";
343 reg = <0x28100000 0x10000>;
344 reg-names = "lpass-lpaif";
347 qcom_pinmux: pinmux@800000 {
348 compatible = "qcom,ipq8064-pinctrl";
349 reg = <0x800000 0x4000>;
352 gpio-ranges = <&qcom_pinmux 0 0 69>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
358 pcie0_pins: pcie0_pinmux {
361 function = "pcie1_rst";
362 drive-strength = <12>;
367 pcie1_pins: pcie1_pinmux {
370 function = "pcie2_rst";
371 drive-strength = <12>;
376 pcie2_pins: pcie2_pinmux {
379 function = "pcie3_rst";
380 drive-strength = <12>;
387 pins = "gpio18", "gpio19", "gpio21";
389 drive-strength = <10>;
394 leds_pins: leds_pins {
396 pins = "gpio7", "gpio8", "gpio9",
399 drive-strength = <2>;
405 buttons_pins: buttons_pins {
408 drive-strength = <2>;
413 nand_pins: nand_pins {
415 pins = "gpio34", "gpio35", "gpio36",
416 "gpio37", "gpio38", "gpio39",
417 "gpio40", "gpio41", "gpio42",
418 "gpio43", "gpio44", "gpio45",
421 drive-strength = <10>;
431 pins = "gpio40", "gpio41", "gpio42",
432 "gpio43", "gpio44", "gpio45",
439 intc: interrupt-controller@2000000 {
440 compatible = "qcom,msm-qgic2";
441 interrupt-controller;
442 #interrupt-cells = <3>;
443 reg = <0x02000000 0x1000>,
448 compatible = "qcom,kpss-timer",
449 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
450 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
451 IRQ_TYPE_EDGE_RISING)>,
452 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
453 IRQ_TYPE_EDGE_RISING)>,
454 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
455 IRQ_TYPE_EDGE_RISING)>,
456 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
457 IRQ_TYPE_EDGE_RISING)>,
458 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
459 IRQ_TYPE_EDGE_RISING)>;
460 reg = <0x0200a000 0x100>;
461 clock-frequency = <25000000>,
463 clocks = <&sleep_clk>;
464 clock-names = "sleep";
465 cpu-offset = <0x80000>;
468 acc0: clock-controller@2088000 {
469 compatible = "qcom,kpss-acc-v1";
470 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
473 acc1: clock-controller@2098000 {
474 compatible = "qcom,kpss-acc-v1";
475 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
478 adm_dma: dma-controller@18300000 {
479 compatible = "qcom,adm";
480 reg = <0x18300000 0x100000>;
481 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
485 clock-names = "core", "iface";
487 resets = <&gcc ADM0_RESET>,
488 <&gcc ADM0_PBUS_RESET>,
489 <&gcc ADM0_C0_RESET>,
490 <&gcc ADM0_C1_RESET>,
491 <&gcc ADM0_C2_RESET>;
492 reset-names = "clk", "pbus", "c0", "c1", "c2";
498 saw0: regulator@2089000 {
499 compatible = "qcom,saw2";
500 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
504 saw1: regulator@2099000 {
505 compatible = "qcom,saw2";
506 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
510 gsbi2: gsbi@12480000 {
511 compatible = "qcom,gsbi-v1.0.0";
513 reg = <0x12480000 0x100>;
514 clocks = <&gcc GSBI2_H_CLK>;
515 clock-names = "iface";
516 #address-cells = <1>;
521 syscon-tcsr = <&tcsr>;
523 gsbi2_serial: serial@12490000 {
524 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
525 reg = <0x12490000 0x1000>,
527 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
529 clock-names = "core", "iface";
534 compatible = "qcom,i2c-qup-v1.1.1";
535 reg = <0x124a0000 0x1000>;
536 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
539 clock-names = "core", "iface";
542 #address-cells = <1>;
547 gsbi4: gsbi@16300000 {
548 compatible = "qcom,gsbi-v1.0.0";
550 reg = <0x16300000 0x100>;
551 clocks = <&gcc GSBI4_H_CLK>;
552 clock-names = "iface";
553 #address-cells = <1>;
558 syscon-tcsr = <&tcsr>;
560 gsbi4_serial: serial@16340000 {
561 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
562 reg = <0x16340000 0x1000>,
564 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
566 clock-names = "core", "iface";
571 compatible = "qcom,i2c-qup-v1.1.1";
572 reg = <0x16380000 0x1000>;
573 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
576 clock-names = "core", "iface";
579 #address-cells = <1>;
584 gsbi5: gsbi@1a200000 {
585 compatible = "qcom,gsbi-v1.0.0";
587 reg = <0x1a200000 0x100>;
588 clocks = <&gcc GSBI5_H_CLK>;
589 clock-names = "iface";
590 #address-cells = <1>;
595 syscon-tcsr = <&tcsr>;
597 gsbi5_serial: serial@1a240000 {
598 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
599 reg = <0x1a240000 0x1000>,
601 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
603 clock-names = "core", "iface";
608 compatible = "qcom,i2c-qup-v1.1.1";
609 reg = <0x1a280000 0x1000>;
610 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
613 clock-names = "core", "iface";
616 #address-cells = <1>;
621 compatible = "qcom,spi-qup-v1.1.1";
622 reg = <0x1a280000 0x1000>;
623 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
626 clock-names = "core", "iface";
629 #address-cells = <1>;
634 gsbi7: gsbi@16600000 {
636 compatible = "qcom,gsbi-v1.0.0";
638 reg = <0x16600000 0x100>;
639 clocks = <&gcc GSBI7_H_CLK>;
640 clock-names = "iface";
641 #address-cells = <1>;
644 syscon-tcsr = <&tcsr>;
646 gsbi7_serial: serial@16640000 {
647 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
648 reg = <0x16640000 0x1000>,
650 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
652 clock-names = "core", "iface";
658 compatible = "qcom,prng";
659 reg = <0x1a500000 0x200>;
660 clocks = <&gcc PRNG_CLK>;
661 clock-names = "core";
664 sata_phy: sata-phy@1b400000 {
665 compatible = "qcom,ipq806x-sata-phy";
666 reg = <0x1b400000 0x200>;
668 clocks = <&gcc SATA_PHY_CFG_CLK>;
675 nand: nand-controller@1ac00000 {
676 compatible = "qcom,ipq806x-nand";
677 reg = <0x1ac00000 0x800>;
679 pinctrl-0 = <&nand_pins>;
680 pinctrl-names = "default";
682 clocks = <&gcc EBI2_CLK>,
684 clock-names = "core", "aon";
688 qcom,cmd-crci = <15>;
689 qcom,data-crci = <3>;
691 #address-cells = <1>;
697 sata: sata@29000000 {
698 compatible = "qcom,ipq806x-ahci", "generic-ahci";
699 reg = <0x29000000 0x180>;
701 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&gcc SFAB_SATA_S_H_CLK>,
706 <&gcc SATA_RXOOB_CLK>,
707 <&gcc SATA_PMALIVE_CLK>;
708 clock-names = "slave_face", "iface", "core",
711 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
712 assigned-clock-rates = <100000000>, <100000000>;
715 phy-names = "sata-phy";
720 compatible = "qcom,ssbi";
721 reg = <0x00500000 0x1000>;
722 qcom,controller-type = "pmic-arbiter";
725 qfprom: qfprom@700000 {
726 compatible = "qcom,qfprom";
727 reg = <0x00700000 0x1000>;
728 #address-cells = <1>;
730 tsens_calib: calib@400 {
733 tsens_calib_backup: calib_backup@410 {
738 gcc: clock-controller@900000 {
739 compatible = "qcom,gcc-ipq8064", "syscon";
740 clocks = <&pxo_board>, <&cxo_board>;
741 clock-names = "pxo", "cxo";
742 reg = <0x00900000 0x4000>;
745 #power-domain-cells = <1>;
747 tsens: thermal-sensor@900000 {
748 compatible = "qcom,ipq8064-tsens";
750 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
751 nvmem-cell-names = "calib", "calib_backup";
752 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
753 interrupt-names = "uplow";
755 #qcom,sensors = <11>;
756 #thermal-sensor-cells = <1>;
761 compatible = "qcom,rpm-ipq8064";
762 reg = <0x108000 0x1000>;
763 qcom,ipc = <&l2cc 0x8 2>;
765 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
768 interrupt-names = "ack", "err", "wakeup";
770 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
773 rpmcc: clock-controller {
774 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
779 tcsr: syscon@1a400000 {
780 compatible = "qcom,tcsr-ipq8064", "syscon";
781 reg = <0x1a400000 0x100>;
784 l2cc: clock-controller@2011000 {
785 compatible = "qcom,kpss-gcc", "syscon";
786 reg = <0x2011000 0x1000>;
787 clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
788 clock-names = "pll8_vote", "pxo";
789 clock-output-names = "acpu_l2_aux";
792 lcc: clock-controller@28000000 {
793 compatible = "qcom,lcc-ipq8064";
794 reg = <0x28000000 0x1000>;
799 pcie0: pci@1b500000 {
800 compatible = "qcom,pcie-ipq8064";
801 reg = <0x1b500000 0x1000
804 0x0ff00000 0x100000>;
805 reg-names = "dbi", "elbi", "parf", "config";
807 linux,pci-domain = <0>;
808 bus-range = <0x00 0xff>;
810 #address-cells = <3>;
813 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
814 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
816 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
817 interrupt-names = "msi";
818 #interrupt-cells = <1>;
819 interrupt-map-mask = <0 0 0 0x7>;
820 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
821 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
822 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
823 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
825 clocks = <&gcc PCIE_A_CLK>,
829 <&gcc PCIE_ALT_REF_CLK>;
830 clock-names = "core", "iface", "phy", "aux", "ref";
832 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
833 assigned-clock-rates = <100000000>;
835 resets = <&gcc PCIE_ACLK_RESET>,
836 <&gcc PCIE_HCLK_RESET>,
837 <&gcc PCIE_POR_RESET>,
838 <&gcc PCIE_PCI_RESET>,
839 <&gcc PCIE_PHY_RESET>,
840 <&gcc PCIE_EXT_RESET>;
841 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
843 pinctrl-0 = <&pcie0_pins>;
844 pinctrl-names = "default";
847 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
850 pcie1: pci@1b700000 {
851 compatible = "qcom,pcie-ipq8064";
852 reg = <0x1b700000 0x1000
855 0x31f00000 0x100000>;
856 reg-names = "dbi", "elbi", "parf", "config";
858 linux,pci-domain = <1>;
859 bus-range = <0x00 0xff>;
861 #address-cells = <3>;
864 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
865 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
867 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "msi";
869 #interrupt-cells = <1>;
870 interrupt-map-mask = <0 0 0 0x7>;
871 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
872 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
873 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
874 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
876 clocks = <&gcc PCIE_1_A_CLK>,
878 <&gcc PCIE_1_PHY_CLK>,
879 <&gcc PCIE_1_AUX_CLK>,
880 <&gcc PCIE_1_ALT_REF_CLK>;
881 clock-names = "core", "iface", "phy", "aux", "ref";
883 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
884 assigned-clock-rates = <100000000>;
886 resets = <&gcc PCIE_1_ACLK_RESET>,
887 <&gcc PCIE_1_HCLK_RESET>,
888 <&gcc PCIE_1_POR_RESET>,
889 <&gcc PCIE_1_PCI_RESET>,
890 <&gcc PCIE_1_PHY_RESET>,
891 <&gcc PCIE_1_EXT_RESET>;
892 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
894 pinctrl-0 = <&pcie1_pins>;
895 pinctrl-names = "default";
898 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
901 pcie2: pci@1b900000 {
902 compatible = "qcom,pcie-ipq8064";
903 reg = <0x1b900000 0x1000
906 0x35f00000 0x100000>;
907 reg-names = "dbi", "elbi", "parf", "config";
909 linux,pci-domain = <2>;
910 bus-range = <0x00 0xff>;
912 #address-cells = <3>;
915 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
916 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
918 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
919 interrupt-names = "msi";
920 #interrupt-cells = <1>;
921 interrupt-map-mask = <0 0 0 0x7>;
922 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
923 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
924 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
925 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
927 clocks = <&gcc PCIE_2_A_CLK>,
929 <&gcc PCIE_2_PHY_CLK>,
930 <&gcc PCIE_2_AUX_CLK>,
931 <&gcc PCIE_2_ALT_REF_CLK>;
932 clock-names = "core", "iface", "phy", "aux", "ref";
934 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
935 assigned-clock-rates = <100000000>;
937 resets = <&gcc PCIE_2_ACLK_RESET>,
938 <&gcc PCIE_2_HCLK_RESET>,
939 <&gcc PCIE_2_POR_RESET>,
940 <&gcc PCIE_2_PCI_RESET>,
941 <&gcc PCIE_2_PHY_RESET>,
942 <&gcc PCIE_2_EXT_RESET>;
943 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
945 pinctrl-0 = <&pcie2_pins>;
946 pinctrl-names = "default";
949 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
952 nss_common: syscon@03000000 {
953 compatible = "syscon";
954 reg = <0x03000000 0x0000FFFF>;
957 qsgmii_csr: syscon@1bb00000 {
958 compatible = "syscon";
959 reg = <0x1bb00000 0x000001FF>;
962 stmmac_axi_setup: stmmac-axi-config {
963 snps,wr_osr_lmt = <7>;
964 snps,rd_osr_lmt = <7>;
965 snps,blen = <16 0 0 0 0 0 0>;
968 gmac0: ethernet@37000000 {
969 device_type = "network";
970 compatible = "qcom,ipq806x-gmac";
971 reg = <0x37000000 0x200000>;
972 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
973 interrupt-names = "macirq";
975 snps,axi-config = <&stmmac_axi_setup>;
979 qcom,nss-common = <&nss_common>;
980 qcom,qsgmii-csr = <&qsgmii_csr>;
982 clocks = <&gcc GMAC_CORE1_CLK>;
983 clock-names = "stmmaceth";
985 resets = <&gcc GMAC_CORE1_RESET>,
986 <&gcc GMAC_AHB_RESET>;
987 reset-names = "stmmaceth", "ahb";
992 gmac1: ethernet@37200000 {
993 device_type = "network";
994 compatible = "qcom,ipq806x-gmac";
995 reg = <0x37200000 0x200000>;
996 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
997 interrupt-names = "macirq";
999 snps,axi-config = <&stmmac_axi_setup>;
1003 qcom,nss-common = <&nss_common>;
1004 qcom,qsgmii-csr = <&qsgmii_csr>;
1006 clocks = <&gcc GMAC_CORE2_CLK>;
1007 clock-names = "stmmaceth";
1009 resets = <&gcc GMAC_CORE2_RESET>,
1010 <&gcc GMAC_AHB_RESET>;
1011 reset-names = "stmmaceth", "ahb";
1013 status = "disabled";
1016 gmac2: ethernet@37400000 {
1017 device_type = "network";
1018 compatible = "qcom,ipq806x-gmac";
1019 reg = <0x37400000 0x200000>;
1020 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1021 interrupt-names = "macirq";
1023 snps,axi-config = <&stmmac_axi_setup>;
1027 qcom,nss-common = <&nss_common>;
1028 qcom,qsgmii-csr = <&qsgmii_csr>;
1030 clocks = <&gcc GMAC_CORE3_CLK>;
1031 clock-names = "stmmaceth";
1033 resets = <&gcc GMAC_CORE3_RESET>,
1034 <&gcc GMAC_AHB_RESET>;
1035 reset-names = "stmmaceth", "ahb";
1037 status = "disabled";
1040 gmac3: ethernet@37600000 {
1041 device_type = "network";
1042 compatible = "qcom,ipq806x-gmac";
1043 reg = <0x37600000 0x200000>;
1044 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1045 interrupt-names = "macirq";
1047 snps,axi-config = <&stmmac_axi_setup>;
1051 qcom,nss-common = <&nss_common>;
1052 qcom,qsgmii-csr = <&qsgmii_csr>;
1054 clocks = <&gcc GMAC_CORE4_CLK>;
1055 clock-names = "stmmaceth";
1057 resets = <&gcc GMAC_CORE4_RESET>,
1058 <&gcc GMAC_AHB_RESET>;
1059 reset-names = "stmmaceth", "ahb";
1061 status = "disabled";
1064 hs_phy_0: phy@100f8800 {
1065 compatible = "qcom,ipq806x-usb-phy-hs";
1066 reg = <0x100f8800 0x30>;
1067 clocks = <&gcc USB30_0_UTMI_CLK>;
1068 clock-names = "ref";
1071 status = "disabled";
1074 ss_phy_0: phy@100f8830 {
1075 compatible = "qcom,ipq806x-usb-phy-ss";
1076 reg = <0x100f8830 0x30>;
1077 clocks = <&gcc USB30_0_MASTER_CLK>;
1078 clock-names = "ref";
1081 status = "disabled";
1084 usb3_0: usb3@100f8800 {
1085 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
1086 #address-cells = <1>;
1088 reg = <0x100f8800 0x8000>;
1089 clocks = <&gcc USB30_0_MASTER_CLK>;
1090 clock-names = "core";
1094 resets = <&gcc USB30_0_MASTER_RESET>;
1095 reset-names = "master";
1097 status = "disabled";
1099 dwc3_0: dwc3@10000000 {
1100 compatible = "snps,dwc3";
1101 reg = <0x10000000 0xcd00>;
1102 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1103 phys = <&hs_phy_0>, <&ss_phy_0>;
1104 phy-names = "usb2-phy", "usb3-phy";
1106 snps,dis_u3_susphy_quirk;
1110 hs_phy_1: phy@110f8800 {
1111 compatible = "qcom,ipq806x-usb-phy-hs";
1112 reg = <0x110f8800 0x30>;
1113 clocks = <&gcc USB30_1_UTMI_CLK>;
1114 clock-names = "ref";
1118 ss_phy_1: phy@110f8830 {
1119 compatible = "qcom,ipq806x-usb-phy-ss";
1120 reg = <0x110f8830 0x30>;
1121 clocks = <&gcc USB30_1_MASTER_CLK>;
1122 clock-names = "ref";
1126 usb3_1: usb3@110f8800 {
1127 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
1128 #address-cells = <1>;
1130 reg = <0x110f8800 0x8000>;
1131 clocks = <&gcc USB30_1_MASTER_CLK>;
1132 clock-names = "core";
1136 resets = <&gcc USB30_1_MASTER_RESET>;
1137 reset-names = "master";
1139 status = "disabled";
1141 dwc3_1: dwc3@11000000 {
1142 compatible = "snps,dwc3";
1143 reg = <0x11000000 0xcd00>;
1144 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1145 phys = <&hs_phy_1>, <&ss_phy_1>;
1146 phy-names = "usb2-phy", "usb3-phy";
1148 snps,dis_u3_susphy_quirk;
1152 vsdcc_fixed: vsdcc-regulator {
1153 compatible = "regulator-fixed";
1154 regulator-name = "SDCC Power";
1155 regulator-min-microvolt = <3300000>;
1156 regulator-max-microvolt = <3300000>;
1157 regulator-always-on;
1160 sdcc1bam: dma-controller@12402000 {
1161 compatible = "qcom,bam-v1.3.0";
1162 reg = <0x12402000 0x8000>;
1163 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&gcc SDC1_H_CLK>;
1165 clock-names = "bam_clk";
1170 sdcc3bam: dma-controller@12182000 {
1171 compatible = "qcom,bam-v1.3.0";
1172 reg = <0x12182000 0x8000>;
1173 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1174 clocks = <&gcc SDC3_H_CLK>;
1175 clock-names = "bam_clk";
1181 compatible = "simple-bus";
1182 #address-cells = <1>;
1186 sdcc1: mmc@12400000 {
1187 status = "disabled";
1188 compatible = "arm,pl18x", "arm,primecell";
1189 arm,primecell-periphid = <0x00051180>;
1190 reg = <0x12400000 0x2000>;
1191 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1192 interrupt-names = "cmd_irq";
1193 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1194 clock-names = "mclk", "apb_pclk";
1196 max-frequency = <96000000>;
1201 vmmc-supply = <&vsdcc_fixed>;
1202 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1203 dma-names = "tx", "rx";
1206 sdcc3: mmc@12180000 {
1207 compatible = "arm,pl18x", "arm,primecell";
1208 arm,primecell-periphid = <0x00051180>;
1209 status = "disabled";
1210 reg = <0x12180000 0x2000>;
1211 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1212 interrupt-names = "cmd_irq";
1213 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1214 clock-names = "mclk", "apb_pclk";
1218 max-frequency = <192000000>;
1221 vqmmc-supply = <&vsdcc_fixed>;
1222 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1223 dma-names = "tx", "rx";