1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Qualcomm APQ8064";
15 compatible = "qcom,apq8064";
16 interrupt-parent = <&intc>;
23 smem_region: smem@80000000 {
24 reg = <0x80000000 0x200000>;
28 wcnss_mem: wcnss@8f000000 {
29 reg = <0x8f000000 0x700000>;
39 compatible = "qcom,krait";
40 enable-method = "qcom,kpss-acc-v1";
43 next-level-cache = <&L2>;
46 cpu-idle-states = <&CPU_SPC>;
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
54 next-level-cache = <&L2>;
57 cpu-idle-states = <&CPU_SPC>;
61 compatible = "qcom,krait";
62 enable-method = "qcom,kpss-acc-v1";
65 next-level-cache = <&L2>;
68 cpu-idle-states = <&CPU_SPC>;
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v1";
76 next-level-cache = <&L2>;
79 cpu-idle-states = <&CPU_SPC>;
89 compatible = "qcom,idle-state-spc",
91 entry-latency-us = <400>;
92 exit-latency-us = <900>;
93 min-residency-us = <3000>;
99 device_type = "memory";
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
108 thermal-sensors = <&gcc 7>;
109 coefficients = <1199 0>;
113 temperature = <75000>;
118 temperature = <110000>;
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
129 thermal-sensors = <&gcc 8>;
130 coefficients = <1132 0>;
134 temperature = <75000>;
139 temperature = <110000>;
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
150 thermal-sensors = <&gcc 9>;
151 coefficients = <1199 0>;
155 temperature = <75000>;
160 temperature = <110000>;
168 polling-delay-passive = <250>;
169 polling-delay = <1000>;
171 thermal-sensors = <&gcc 10>;
172 coefficients = <1132 0>;
176 temperature = <75000>;
181 temperature = <110000>;
190 compatible = "qcom,krait-pmu";
191 interrupts = <1 10 0x304>;
195 cxo_board: cxo_board {
196 compatible = "fixed-clock";
198 clock-frequency = <19200000>;
201 pxo_board: pxo_board {
202 compatible = "fixed-clock";
204 clock-frequency = <27000000>;
207 sleep_clk: sleep_clk {
208 compatible = "fixed-clock";
210 clock-frequency = <32768>;
214 sfpb_mutex: hwmutex {
215 compatible = "qcom,sfpb-mutex";
216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
221 compatible = "qcom,smem";
222 memory-region = <&smem_region>;
224 hwlocks = <&sfpb_mutex 3>;
228 compatible = "qcom,smd";
231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
233 qcom,ipc = <&l2cc 8 3>;
240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
242 qcom,ipc = <&l2cc 8 15>;
249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
260 qcom,ipc = <&l2cc 8 25>;
268 compatible = "qcom,smsm";
270 #address-cells = <1>;
273 qcom,ipc-1 = <&l2cc 8 4>;
274 qcom,ipc-2 = <&l2cc 8 14>;
275 qcom,ipc-3 = <&l2cc 8 23>;
276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
280 #qcom,smem-state-cells = <1>;
283 modem_smsm: modem@1 {
285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
299 wcnss_smsm: wcnss@3 {
301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
318 compatible = "qcom,scm-apq8064";
320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
321 clock-names = "core";
327 * These channels from the ADC are simply hardware monitors.
328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
332 compatible = "iio-hwmon";
333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
334 <&xoadc 0x00 0x02>, /* DC in (charger) */
335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
336 <&xoadc 0x00 0x0b>, /* Die temperature */
337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
339 <&xoadc 0x00 0x0e>; /* Charger temperature */
343 #address-cells = <1>;
346 compatible = "simple-bus";
348 tlmm_pinmux: pinctrl@800000 {
349 compatible = "qcom,apq8064-pinctrl";
350 reg = <0x800000 0x4000>;
353 gpio-ranges = <&tlmm_pinmux 0 0 90>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&ps_hold>;
363 sfpb_wrapper_mutex: syscon@1200000 {
364 compatible = "syscon";
365 reg = <0x01200000 0x8000>;
368 intc: interrupt-controller@2000000 {
369 compatible = "qcom,msm-qgic2";
370 interrupt-controller;
371 #interrupt-cells = <3>;
372 reg = <0x02000000 0x1000>,
377 compatible = "qcom,kpss-timer",
378 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
379 interrupts = <1 1 0x301>,
382 reg = <0x0200a000 0x100>;
383 clock-frequency = <27000000>,
385 cpu-offset = <0x80000>;
388 acc0: clock-controller@2088000 {
389 compatible = "qcom,kpss-acc-v1";
390 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
393 acc1: clock-controller@2098000 {
394 compatible = "qcom,kpss-acc-v1";
395 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
398 acc2: clock-controller@20a8000 {
399 compatible = "qcom,kpss-acc-v1";
400 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
403 acc3: clock-controller@20b8000 {
404 compatible = "qcom,kpss-acc-v1";
405 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
408 saw0: power-controller@2089000 {
409 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
410 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
414 saw1: power-controller@2099000 {
415 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
416 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
420 saw2: power-controller@20a9000 {
421 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
422 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
426 saw3: power-controller@20b9000 {
427 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
428 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
432 sps_sic_non_secure: sps-sic-non-secure@12100000 {
433 compatible = "syscon";
434 reg = <0x12100000 0x10000>;
437 gsbi1: gsbi@12440000 {
439 compatible = "qcom,gsbi-v1.0.0";
441 reg = <0x12440000 0x100>;
442 clocks = <&gcc GSBI1_H_CLK>;
443 clock-names = "iface";
444 #address-cells = <1>;
448 syscon-tcsr = <&tcsr>;
450 gsbi1_serial: serial@12450000 {
451 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
452 reg = <0x12450000 0x100>,
454 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
456 clock-names = "core", "iface";
460 gsbi1_i2c: i2c@12460000 {
461 compatible = "qcom,i2c-qup-v1.1.1";
462 pinctrl-0 = <&i2c1_pins>;
463 pinctrl-1 = <&i2c1_pins_sleep>;
464 pinctrl-names = "default", "sleep";
465 reg = <0x12460000 0x1000>;
466 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
468 clock-names = "core", "iface";
469 #address-cells = <1>;
476 gsbi2: gsbi@12480000 {
478 compatible = "qcom,gsbi-v1.0.0";
480 reg = <0x12480000 0x100>;
481 clocks = <&gcc GSBI2_H_CLK>;
482 clock-names = "iface";
483 #address-cells = <1>;
487 syscon-tcsr = <&tcsr>;
489 gsbi2_i2c: i2c@124a0000 {
490 compatible = "qcom,i2c-qup-v1.1.1";
491 reg = <0x124a0000 0x1000>;
492 pinctrl-0 = <&i2c2_pins>;
493 pinctrl-1 = <&i2c2_pins_sleep>;
494 pinctrl-names = "default", "sleep";
495 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
497 clock-names = "core", "iface";
498 #address-cells = <1>;
504 gsbi3: gsbi@16200000 {
506 compatible = "qcom,gsbi-v1.0.0";
508 reg = <0x16200000 0x100>;
509 clocks = <&gcc GSBI3_H_CLK>;
510 clock-names = "iface";
511 #address-cells = <1>;
514 gsbi3_i2c: i2c@16280000 {
515 compatible = "qcom,i2c-qup-v1.1.1";
516 pinctrl-0 = <&i2c3_pins>;
517 pinctrl-1 = <&i2c3_pins_sleep>;
518 pinctrl-names = "default", "sleep";
519 reg = <0x16280000 0x1000>;
520 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&gcc GSBI3_QUP_CLK>,
523 clock-names = "core", "iface";
524 #address-cells = <1>;
530 gsbi4: gsbi@16300000 {
532 compatible = "qcom,gsbi-v1.0.0";
534 reg = <0x16300000 0x03>;
535 clocks = <&gcc GSBI4_H_CLK>;
536 clock-names = "iface";
537 #address-cells = <1>;
541 gsbi4_i2c: i2c@16380000 {
542 compatible = "qcom,i2c-qup-v1.1.1";
543 pinctrl-0 = <&i2c4_pins>;
544 pinctrl-1 = <&i2c4_pins_sleep>;
545 pinctrl-names = "default", "sleep";
546 reg = <0x16380000 0x1000>;
547 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&gcc GSBI4_QUP_CLK>,
550 clock-names = "core", "iface";
555 gsbi5: gsbi@1a200000 {
557 compatible = "qcom,gsbi-v1.0.0";
559 reg = <0x1a200000 0x03>;
560 clocks = <&gcc GSBI5_H_CLK>;
561 clock-names = "iface";
562 #address-cells = <1>;
566 gsbi5_serial: serial@1a240000 {
567 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
568 reg = <0x1a240000 0x100>,
570 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
572 clock-names = "core", "iface";
576 gsbi5_spi: spi@1a280000 {
577 compatible = "qcom,spi-qup-v1.1.1";
578 reg = <0x1a280000 0x1000>;
579 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-0 = <&spi5_default>;
581 pinctrl-1 = <&spi5_sleep>;
582 pinctrl-names = "default", "sleep";
583 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
584 clock-names = "core", "iface";
586 #address-cells = <1>;
591 gsbi6: gsbi@16500000 {
593 compatible = "qcom,gsbi-v1.0.0";
595 reg = <0x16500000 0x03>;
596 clocks = <&gcc GSBI6_H_CLK>;
597 clock-names = "iface";
598 #address-cells = <1>;
602 gsbi6_serial: serial@16540000 {
603 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
604 reg = <0x16540000 0x100>,
606 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
608 clock-names = "core", "iface";
612 gsbi6_i2c: i2c@16580000 {
613 compatible = "qcom,i2c-qup-v1.1.1";
614 pinctrl-0 = <&i2c6_pins>;
615 pinctrl-1 = <&i2c6_pins_sleep>;
616 pinctrl-names = "default", "sleep";
617 reg = <0x16580000 0x1000>;
618 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&gcc GSBI6_QUP_CLK>,
621 clock-names = "core", "iface";
626 gsbi7: gsbi@16600000 {
628 compatible = "qcom,gsbi-v1.0.0";
630 reg = <0x16600000 0x100>;
631 clocks = <&gcc GSBI7_H_CLK>;
632 clock-names = "iface";
633 #address-cells = <1>;
636 syscon-tcsr = <&tcsr>;
638 gsbi7_serial: serial@16640000 {
639 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
640 reg = <0x16640000 0x1000>,
642 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
644 clock-names = "core", "iface";
648 gsbi7_i2c: i2c@16680000 {
649 compatible = "qcom,i2c-qup-v1.1.1";
650 pinctrl-0 = <&i2c7_pins>;
651 pinctrl-1 = <&i2c7_pins_sleep>;
652 pinctrl-names = "default", "sleep";
653 reg = <0x16680000 0x1000>;
654 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&gcc GSBI7_QUP_CLK>,
657 clock-names = "core", "iface";
663 compatible = "qcom,prng";
664 reg = <0x1a500000 0x200>;
665 clocks = <&gcc PRNG_CLK>;
666 clock-names = "core";
670 compatible = "qcom,ssbi";
671 reg = <0x00c00000 0x1000>;
672 qcom,controller-type = "pmic-arbiter";
675 compatible = "qcom,pm8821";
676 interrupt-parent = <&tlmm_pinmux>;
677 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
678 #interrupt-cells = <2>;
679 interrupt-controller;
680 #address-cells = <1>;
683 pm8821_mpps: mpps@50 {
684 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
686 interrupt-controller;
687 #interrupt-cells = <2>;
690 gpio-ranges = <&pm8821_mpps 0 0 4>;
696 compatible = "qcom,ssbi";
697 reg = <0x00500000 0x1000>;
698 qcom,controller-type = "pmic-arbiter";
701 compatible = "qcom,pm8921";
702 interrupt-parent = <&tlmm_pinmux>;
704 #interrupt-cells = <2>;
705 interrupt-controller;
706 #address-cells = <1>;
709 pm8921_gpio: gpio@150 {
711 compatible = "qcom,pm8921-gpio",
714 interrupt-controller;
715 #interrupt-cells = <2>;
717 gpio-ranges = <&pm8921_gpio 0 0 44>;
722 pm8921_mpps: mpps@50 {
723 compatible = "qcom,pm8921-mpp",
728 gpio-ranges = <&pm8921_mpps 0 0 12>;
729 interrupt-controller;
730 #interrupt-cells = <2>;
734 compatible = "qcom,pm8921-rtc";
735 interrupt-parent = <&pmicintc>;
742 compatible = "qcom,pm8921-pwrkey";
744 interrupt-parent = <&pmicintc>;
745 interrupts = <50 1>, <51 1>;
751 compatible = "qcom,pm8921-adc";
753 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
754 #address-cells = <2>;
756 #io-channel-cells = <2>;
758 vcoin: adc-channel@0 {
761 vbat: adc-channel@1 {
764 dcin: adc-channel@2 {
767 vph_pwr: adc-channel@4 {
770 batt_therm: adc-channel@8 {
773 batt_id: adc-channel@9 {
776 usb_vbus: adc-channel@a {
779 die_temp: adc-channel@b {
782 ref_625mv: adc-channel@c {
785 ref_1250mv: adc-channel@d {
788 chg_temp: adc-channel@e {
791 ref_muxoff: adc-channel@f {
798 qfprom: qfprom@700000 {
799 compatible = "qcom,qfprom";
800 reg = <0x00700000 0x1000>;
801 #address-cells = <1>;
807 tsens_backup: backup_calib {
812 gcc: clock-controller@900000 {
813 compatible = "qcom,gcc-apq8064";
814 reg = <0x00900000 0x4000>;
815 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
816 nvmem-cell-names = "calib", "calib_backup";
819 #thermal-sensor-cells = <1>;
822 lcc: clock-controller@28000000 {
823 compatible = "qcom,lcc-apq8064";
824 reg = <0x28000000 0x1000>;
829 mmcc: clock-controller@4000000 {
830 compatible = "qcom,mmcc-apq8064";
831 reg = <0x4000000 0x1000>;
836 l2cc: clock-controller@2011000 {
837 compatible = "syscon";
838 reg = <0x2011000 0x1000>;
842 compatible = "qcom,rpm-apq8064";
843 reg = <0x108000 0x1000>;
844 qcom,ipc = <&l2cc 0x8 2>;
846 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
847 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
848 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
849 interrupt-names = "ack", "err", "wakeup";
851 rpmcc: clock-controller {
852 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
857 compatible = "qcom,rpm-pm8921-regulators";
893 pm8921_lvs1: lvs1 {};
894 pm8921_lvs2: lvs2 {};
895 pm8921_lvs3: lvs3 {};
896 pm8921_lvs4: lvs4 {};
897 pm8921_lvs5: lvs5 {};
898 pm8921_lvs6: lvs6 {};
899 pm8921_lvs7: lvs7 {};
901 pm8921_usb_switch: usb-switch {};
903 pm8921_hdmi_switch: hdmi-switch {
912 compatible = "qcom,ci-hdrc";
913 reg = <0x12500000 0x200>,
915 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
917 clock-names = "core", "iface";
918 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
919 assigned-clock-rates = <60000000>;
920 resets = <&gcc USB_HS1_RESET>;
921 reset-names = "core";
923 ahb-burst-config = <0>;
924 phys = <&usb_hs1_phy>;
925 phy-names = "usb-phy";
931 compatible = "qcom,usb-hs-phy-apq8064",
933 clocks = <&sleep_clk>, <&cxo_board>;
934 clock-names = "sleep", "ref";
943 compatible = "qcom,ci-hdrc";
944 reg = <0x12520000 0x200>,
946 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
948 clock-names = "core", "iface";
949 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
950 assigned-clock-rates = <60000000>;
951 resets = <&gcc USB_HS3_RESET>;
952 reset-names = "core";
954 ahb-burst-config = <0>;
955 phys = <&usb_hs3_phy>;
956 phy-names = "usb-phy";
962 compatible = "qcom,usb-hs-phy-apq8064",
965 clocks = <&sleep_clk>, <&cxo_board>;
966 clock-names = "sleep", "ref";
974 compatible = "qcom,ci-hdrc";
975 reg = <0x12530000 0x200>,
977 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
979 clock-names = "core", "iface";
980 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
981 assigned-clock-rates = <60000000>;
982 resets = <&gcc USB_HS4_RESET>;
983 reset-names = "core";
985 ahb-burst-config = <0>;
986 phys = <&usb_hs4_phy>;
987 phy-names = "usb-phy";
993 compatible = "qcom,usb-hs-phy-apq8064",
996 clocks = <&sleep_clk>, <&cxo_board>;
997 clock-names = "sleep", "ref";
1004 sata_phy0: phy@1b400000 {
1005 compatible = "qcom,apq8064-sata-phy";
1006 status = "disabled";
1007 reg = <0x1b400000 0x200>;
1008 reg-names = "phy_mem";
1009 clocks = <&gcc SATA_PHY_CFG_CLK>;
1010 clock-names = "cfg";
1014 sata0: sata@29000000 {
1015 compatible = "qcom,apq8064-ahci", "generic-ahci";
1016 status = "disabled";
1017 reg = <0x29000000 0x180>;
1018 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1023 <&gcc SATA_RXOOB_CLK>,
1024 <&gcc SATA_PMALIVE_CLK>;
1025 clock-names = "slave_iface",
1031 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1032 <&gcc SATA_PMALIVE_CLK>;
1033 assigned-clock-rates = <100000000>, <100000000>;
1035 phys = <&sata_phy0>;
1036 phy-names = "sata-phy";
1037 ports-implemented = <0x1>;
1040 /* Temporary fixed regulator */
1041 sdcc1bam:dma@12402000{
1042 compatible = "qcom,bam-v1.3.0";
1043 reg = <0x12402000 0x8000>;
1044 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&gcc SDC1_H_CLK>;
1046 clock-names = "bam_clk";
1051 sdcc3bam:dma@12182000{
1052 compatible = "qcom,bam-v1.3.0";
1053 reg = <0x12182000 0x8000>;
1054 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&gcc SDC3_H_CLK>;
1056 clock-names = "bam_clk";
1061 sdcc4bam:dma@121c2000{
1062 compatible = "qcom,bam-v1.3.0";
1063 reg = <0x121c2000 0x8000>;
1064 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&gcc SDC4_H_CLK>;
1066 clock-names = "bam_clk";
1072 compatible = "simple-bus";
1073 #address-cells = <1>;
1076 sdcc1: mmc@12400000 {
1077 status = "disabled";
1078 compatible = "arm,pl18x", "arm,primecell";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&sdcc1_pins>;
1081 arm,primecell-periphid = <0x00051180>;
1082 reg = <0x12400000 0x2000>;
1083 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1084 interrupt-names = "cmd_irq";
1085 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1086 clock-names = "mclk", "apb_pclk";
1088 max-frequency = <96000000>;
1092 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1093 dma-names = "tx", "rx";
1096 sdcc3: mmc@12180000 {
1097 compatible = "arm,pl18x", "arm,primecell";
1098 arm,primecell-periphid = <0x00051180>;
1099 status = "disabled";
1100 reg = <0x12180000 0x2000>;
1101 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1102 interrupt-names = "cmd_irq";
1103 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1104 clock-names = "mclk", "apb_pclk";
1108 max-frequency = <192000000>;
1110 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1111 dma-names = "tx", "rx";
1114 sdcc4: mmc@121c0000 {
1115 compatible = "arm,pl18x", "arm,primecell";
1116 arm,primecell-periphid = <0x00051180>;
1117 status = "disabled";
1118 reg = <0x121c0000 0x2000>;
1119 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1120 interrupt-names = "cmd_irq";
1121 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1122 clock-names = "mclk", "apb_pclk";
1126 max-frequency = <48000000>;
1127 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1128 dma-names = "tx", "rx";
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&sdc4_gpios>;
1134 tcsr: syscon@1a400000 {
1135 compatible = "qcom,tcsr-apq8064", "syscon";
1136 reg = <0x1a400000 0x100>;
1139 gpu: adreno-3xx@4300000 {
1140 compatible = "qcom,adreno-320.2", "qcom,adreno";
1141 reg = <0x04300000 0x20000>;
1142 reg-names = "kgsl_3d0_reg_memory";
1143 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1144 interrupt-names = "kgsl_3d0_irq";
1152 <&mmcc GFX3D_AHB_CLK>,
1153 <&mmcc GFX3D_AXI_CLK>,
1154 <&mmcc MMSS_IMEM_AHB_CLK>;
1221 operating-points-v2 = <&gpu_opp_table>;
1223 gpu_opp_table: opp-table {
1224 compatible = "operating-points-v2";
1227 opp-hz = /bits/ 64 <450000000>;
1231 opp-hz = /bits/ 64 <27000000>;
1236 mmss_sfpb: syscon@5700000 {
1237 compatible = "syscon";
1238 reg = <0x5700000 0x70>;
1241 dsi0: mdss_dsi@4700000 {
1242 compatible = "qcom,mdss-dsi-ctrl";
1243 label = "MDSS DSI CTRL->0";
1244 #address-cells = <1>;
1246 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1247 reg = <0x04700000 0x200>;
1248 reg-names = "dsi_ctrl";
1250 clocks = <&mmcc DSI_M_AHB_CLK>,
1251 <&mmcc DSI_S_AHB_CLK>,
1252 <&mmcc AMP_AHB_CLK>,
1254 <&mmcc DSI1_BYTE_CLK>,
1255 <&mmcc DSI_PIXEL_CLK>,
1256 <&mmcc DSI1_ESC_CLK>;
1257 clock-names = "iface", "bus", "core_mmss",
1258 "src", "byte", "pixel",
1261 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1262 <&mmcc DSI1_ESC_SRC>,
1264 <&mmcc DSI_PIXEL_SRC>;
1265 assigned-clock-parents = <&dsi0_phy 0>,
1269 syscon-sfpb = <&mmss_sfpb>;
1272 #address-cells = <1>;
1283 dsi0_out: endpoint {
1290 dsi0_phy: dsi-phy@4700200 {
1291 compatible = "qcom,dsi-phy-28nm-8960";
1295 reg = <0x04700200 0x100>,
1298 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1299 clock-names = "iface_clk", "ref";
1300 clocks = <&mmcc DSI_M_AHB_CLK>,
1305 mdp_port0: iommu@7500000 {
1306 compatible = "qcom,apq8064-iommu";
1312 <&mmcc SMMU_AHB_CLK>,
1313 <&mmcc MDP_AXI_CLK>;
1314 reg = <0x07500000 0x100000>;
1316 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1321 mdp_port1: iommu@7600000 {
1322 compatible = "qcom,apq8064-iommu";
1328 <&mmcc SMMU_AHB_CLK>,
1329 <&mmcc MDP_AXI_CLK>;
1330 reg = <0x07600000 0x100000>;
1332 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1337 gfx3d: iommu@7c00000 {
1338 compatible = "qcom,apq8064-iommu";
1344 <&mmcc SMMU_AHB_CLK>,
1345 <&mmcc GFX3D_AXI_CLK>;
1346 reg = <0x07c00000 0x100000>;
1348 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1353 gfx3d1: iommu@7d00000 {
1354 compatible = "qcom,apq8064-iommu";
1360 <&mmcc SMMU_AHB_CLK>,
1361 <&mmcc GFX3D_AXI_CLK>;
1362 reg = <0x07d00000 0x100000>;
1364 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1369 pcie: pci@1b500000 {
1370 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1371 reg = <0x1b500000 0x1000
1374 0x0ff00000 0x100000>;
1375 reg-names = "dbi", "elbi", "parf", "config";
1376 device_type = "pci";
1377 linux,pci-domain = <0>;
1378 bus-range = <0x00 0xff>;
1380 #address-cells = <3>;
1382 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1383 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
1384 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1385 interrupt-names = "msi";
1386 #interrupt-cells = <1>;
1387 interrupt-map-mask = <0 0 0 0x7>;
1388 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1389 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1390 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1391 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1392 clocks = <&gcc PCIE_A_CLK>,
1394 <&gcc PCIE_PHY_REF_CLK>;
1395 clock-names = "core", "iface", "phy";
1396 resets = <&gcc PCIE_ACLK_RESET>,
1397 <&gcc PCIE_HCLK_RESET>,
1398 <&gcc PCIE_POR_RESET>,
1399 <&gcc PCIE_PCI_RESET>,
1400 <&gcc PCIE_PHY_RESET>;
1401 reset-names = "axi", "ahb", "por", "pci", "phy";
1402 status = "disabled";
1405 hdmi: hdmi-tx@4a00000 {
1406 compatible = "qcom,hdmi-tx-8960";
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&hdmi_pinctrl>;
1409 reg = <0x04a00000 0x2f0>;
1410 reg-names = "core_physical";
1411 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1412 clocks = <&mmcc HDMI_APP_CLK>,
1413 <&mmcc HDMI_M_AHB_CLK>,
1414 <&mmcc HDMI_S_AHB_CLK>;
1415 clock-names = "core",
1420 phy-names = "hdmi-phy";
1423 #address-cells = <1>;
1434 hdmi_out: endpoint {
1440 hdmi_phy: hdmi-phy@4a00400 {
1441 compatible = "qcom,hdmi-phy-8960";
1442 reg = <0x4a00400 0x60>,
1444 reg-names = "hdmi_phy",
1447 clocks = <&mmcc HDMI_S_AHB_CLK>;
1448 clock-names = "slave_iface";
1453 compatible = "qcom,mdp4";
1454 reg = <0x05100000 0xf0000>;
1455 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1456 clocks = <&mmcc MDP_CLK>,
1457 <&mmcc MDP_AHB_CLK>,
1458 <&mmcc MDP_AXI_CLK>,
1459 <&mmcc MDP_LUT_CLK>,
1460 <&mmcc HDMI_TV_CLK>,
1462 clock-names = "core_clk",
1469 iommus = <&mdp_port0 0
1475 #address-cells = <1>;
1480 mdp_lvds_out: endpoint {
1486 mdp_dsi1_out: endpoint {
1492 mdp_dsi2_out: endpoint {
1498 mdp_dtv_out: endpoint {
1504 riva: riva-pil@3204000 {
1505 compatible = "qcom,riva-pil";
1507 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1508 reg-names = "ccu", "dxe", "pmu";
1510 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1511 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1512 interrupt-names = "wdog", "fatal";
1514 memory-region = <&wcnss_mem>;
1516 vddcx-supply = <&pm8921_s3>;
1517 vddmx-supply = <&pm8921_l24>;
1518 vddpx-supply = <&pm8921_s4>;
1520 status = "disabled";
1523 compatible = "qcom,wcn3660";
1525 clocks = <&cxo_board>;
1528 vddxo-supply = <&pm8921_l4>;
1529 vddrfa-supply = <&pm8921_s2>;
1530 vddpa-supply = <&pm8921_l10>;
1531 vdddig-supply = <&pm8921_lvs2>;
1535 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1537 qcom,ipc = <&l2cc 8 25>;
1538 qcom,smd-edge = <6>;
1543 compatible = "qcom,wcnss";
1544 qcom,smd-channels = "WCNSS_CTRL";
1546 qcom,mmio = <&riva>;
1549 compatible = "qcom,wcnss-bt";
1553 compatible = "qcom,wcnss-wlan";
1555 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1557 interrupt-names = "tx", "rx";
1559 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1560 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1567 compatible = "coresight-etb10", "arm,primecell";
1568 reg = <0x1a01000 0x1000>;
1570 clocks = <&rpmcc RPM_QDSS_CLK>;
1571 clock-names = "apb_pclk";
1576 remote-endpoint = <&replicator_out0>;
1583 compatible = "arm,coresight-tpiu", "arm,primecell";
1584 reg = <0x1a03000 0x1000>;
1586 clocks = <&rpmcc RPM_QDSS_CLK>;
1587 clock-names = "apb_pclk";
1592 remote-endpoint = <&replicator_out1>;
1599 compatible = "arm,coresight-static-replicator";
1601 clocks = <&rpmcc RPM_QDSS_CLK>;
1602 clock-names = "apb_pclk";
1605 #address-cells = <1>;
1610 replicator_out0: endpoint {
1611 remote-endpoint = <&etb_in>;
1616 replicator_out1: endpoint {
1617 remote-endpoint = <&tpiu_in>;
1624 replicator_in: endpoint {
1625 remote-endpoint = <&funnel_out>;
1632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1633 reg = <0x1a04000 0x1000>;
1635 clocks = <&rpmcc RPM_QDSS_CLK>;
1636 clock-names = "apb_pclk";
1639 #address-cells = <1>;
1643 * Not described input ports:
1644 * 2 - connected to STM component
1651 funnel_in0: endpoint {
1652 remote-endpoint = <&etm0_out>;
1657 funnel_in1: endpoint {
1658 remote-endpoint = <&etm1_out>;
1663 funnel_in4: endpoint {
1664 remote-endpoint = <&etm2_out>;
1669 funnel_in5: endpoint {
1670 remote-endpoint = <&etm3_out>;
1677 funnel_out: endpoint {
1678 remote-endpoint = <&replicator_in>;
1685 compatible = "arm,coresight-etm3x", "arm,primecell";
1686 reg = <0x1a1c000 0x1000>;
1688 clocks = <&rpmcc RPM_QDSS_CLK>;
1689 clock-names = "apb_pclk";
1695 etm0_out: endpoint {
1696 remote-endpoint = <&funnel_in0>;
1703 compatible = "arm,coresight-etm3x", "arm,primecell";
1704 reg = <0x1a1d000 0x1000>;
1706 clocks = <&rpmcc RPM_QDSS_CLK>;
1707 clock-names = "apb_pclk";
1713 etm1_out: endpoint {
1714 remote-endpoint = <&funnel_in1>;
1721 compatible = "arm,coresight-etm3x", "arm,primecell";
1722 reg = <0x1a1e000 0x1000>;
1724 clocks = <&rpmcc RPM_QDSS_CLK>;
1725 clock-names = "apb_pclk";
1731 etm2_out: endpoint {
1732 remote-endpoint = <&funnel_in4>;
1739 compatible = "arm,coresight-etm3x", "arm,primecell";
1740 reg = <0x1a1f000 0x1000>;
1742 clocks = <&rpmcc RPM_QDSS_CLK>;
1743 clock-names = "apb_pclk";
1749 etm3_out: endpoint {
1750 remote-endpoint = <&funnel_in5>;
1757 #include "qcom-apq8064-pins.dtsi"