arch/arm/boot/dts/qcom/qcom-msm8960.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
   8 #include <dt-bindings/mfd/qcom-rpm.h>
   9 #include <dt-bindings/soc/qcom,gsbi.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         model = "Qualcomm MSM8960";
  15         compatible = "qcom,msm8960";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 interrupts = <GIC_PPI 14 0x304>;
  22
  23                 cpu@0 {
  24                         compatible = "qcom,krait";
  25                         enable-method = "qcom,kpss-acc-v1";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         next-level-cache = <&L2>;
  29                         qcom,acc = <&acc0>;
  30                         qcom,saw = <&saw0>;
  31                 };
  32
  33                 cpu@1 {
  34                         compatible = "qcom,krait";
  35                         enable-method = "qcom,kpss-acc-v1";
  36                         device_type = "cpu";
  37                         reg = <1>;
  38                         next-level-cache = <&L2>;
  39                         qcom,acc = <&acc1>;
  40                         qcom,saw = <&saw1>;
  41                 };
  42
  43                 L2: l2-cache {
  44                         compatible = "cache";
  45                         cache-level = <2>;
  46                         cache-unified;
  47                 };
  48         };
  49
  50         memory {
  51                 device_type = "memory";
  52                 reg = <0x0 0x0>;
  53         };
  54
  55         cpu-pmu {
  56                 compatible = "qcom,krait-pmu";
  57                 interrupts = <GIC_PPI 10 0x304>;
  58                 qcom,no-pc-write;
  59         };
  60
  61         clocks {
  62                 cxo_board: cxo_board {
  63                         compatible = "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <19200000>;
  66                         clock-output-names = "cxo_board";
  67                 };
  68
  69                 pxo_board: pxo_board {
  70                         compatible = "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <27000000>;
  73                         clock-output-names = "pxo_board";
  74                 };
  75
  76                 sleep_clk: sleep_clk {
  77                         compatible = "fixed-clock";
  78                         #clock-cells = <0>;
  79                         clock-frequency = <32768>;
  80                         clock-output-names = "sleep_clk";
  81                 };
  82         };
  83
  84         /* Temporary fixed regulator */
  85         vsdcc_fixed: vsdcc-regulator {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "SDCC Power";
  88                 regulator-min-microvolt = <2700000>;
  89                 regulator-max-microvolt = <2700000>;
  90                 regulator-always-on;
  91         };
  92
  93         soc: soc {
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges;
  97                 compatible = "simple-bus";
  98
  99                 intc: interrupt-controller@2000000 {
 100                         compatible = "qcom,msm-qgic2";
 101                         interrupt-controller;
 102                         #interrupt-cells = <3>;
 103                         reg = <0x02000000 0x1000>,
 104                               <0x02002000 0x1000>;
 105                 };
 106
 107                 timer@200a000 {
 108                         compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
 109                                      "qcom,msm-timer";
 110                         interrupts = <GIC_PPI 1 0x301>,
 111                                      <GIC_PPI 2 0x301>,
 112                                      <GIC_PPI 3 0x301>;
 113                         reg = <0x0200a000 0x100>;
 114                         clock-frequency = <27000000>;
 115                         cpu-offset = <0x80000>;
 116                 };
 117
 118                 msmgpio: pinctrl@800000 {
 119                         compatible = "qcom,msm8960-pinctrl";
 120                         gpio-controller;
 121                         gpio-ranges = <&msmgpio 0 0 152>;
 122                         #gpio-cells = <2>;
 123                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 124                         interrupt-controller;
 125                         #interrupt-cells = <2>;
 126                         reg = <0x800000 0x4000>;
 127                 };
 128
 129                 gcc: clock-controller@900000 {
 130                         compatible = "qcom,gcc-msm8960";
 131                         #clock-cells = <1>;
 132                         #power-domain-cells = <1>;
 133                         #reset-cells = <1>;
 134                         reg = <0x900000 0x4000>;
 135                         clocks = <&cxo_board>,
 136                                  <&pxo_board>,
 137                                  <&lcc PLL4>;
 138                         clock-names = "cxo", "pxo", "pll4";
 139                 };
 140
 141                 lcc: clock-controller@28000000 {
 142                         compatible = "qcom,lcc-msm8960";
 143                         reg = <0x28000000 0x1000>;
 144                         #clock-cells = <1>;
 145                         #reset-cells = <1>;
 146                         clocks = <&pxo_board>,
 147                                  <&gcc PLL4_VOTE>,
 148                                  <0>,
 149                                  <0>, <0>,
 150                                  <0>, <0>,
 151                                  <0>;
 152                         clock-names = "pxo",
 153                                       "pll4_vote",
 154                                       "mi2s_codec_clk",
 155                                       "codec_i2s_mic_codec_clk",
 156                                       "spare_i2s_mic_codec_clk",
 157                                       "codec_i2s_spkr_codec_clk",
 158                                       "spare_i2s_spkr_codec_clk",
 159                                       "pcm_codec_clk";
 160                 };
 161
 162                 clock-controller@4000000 {
 163                         compatible = "qcom,mmcc-msm8960";
 164                         reg = <0x4000000 0x1000>;
 165                         #clock-cells = <1>;
 166                         #power-domain-cells = <1>;
 167                         #reset-cells = <1>;
 168                         clocks = <&pxo_board>,
 169                                  <&gcc PLL3>,
 170                                  <&gcc PLL8_VOTE>,
 171                                  <0>,
 172                                  <0>,
 173                                  <0>,
 174                                  <0>,
 175                                  <0>;
 176                         clock-names = "pxo",
 177                                       "pll3",
 178                                       "pll8_vote",
 179                                       "dsi1pll",
 180                                       "dsi1pllbyte",
 181                                       "dsi2pll",
 182                                       "dsi2pllbyte",
 183                                       "hdmipll";
 184                 };
 185
 186                 l2cc: clock-controller@2011000 {
 187                         compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
 188                         reg = <0x2011000 0x1000>;
 189                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 190                         clock-names = "pll8_vote", "pxo";
 191                         #clock-cells = <0>;
 192                 };
 193
 194                 rpm: rpm@108000 {
 195                         compatible = "qcom,rpm-msm8960";
 196                         reg = <0x108000 0x1000>;
 197                         qcom,ipc = <&l2cc 0x8 2>;
 198
 199                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 200                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 201                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 202                         interrupt-names = "ack", "err", "wakeup";
 203
 204                         regulators {
 205                                 compatible = "qcom,rpm-pm8921-regulators";
 206                         };
 207                 };
 208
 209                 acc0: clock-controller@2088000 {
 210                         compatible = "qcom,kpss-acc-v1";
 211                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 212                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 213                         clock-names = "pll8_vote", "pxo";
 214                         clock-output-names = "acpu0_aux";
 215                         #clock-cells = <0>;
 216                 };
 217
 218                 acc1: clock-controller@2098000 {
 219                         compatible = "qcom,kpss-acc-v1";
 220                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 221                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 222                         clock-names = "pll8_vote", "pxo";
 223                         clock-output-names = "acpu1_aux";
 224                         #clock-cells = <0>;
 225                 };
 226
 227                 saw0: regulator@2089000 {
 228                         compatible = "qcom,saw2";
 229                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 230                         regulator;
 231                 };
 232
 233                 saw1: regulator@2099000 {
 234                         compatible = "qcom,saw2";
 235                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 236                         regulator;
 237                 };
 238
 239                 gsbi5: gsbi@16400000 {
 240                         compatible = "qcom,gsbi-v1.0.0";
 241                         cell-index = <5>;
 242                         reg = <0x16400000 0x100>;
 243                         clocks = <&gcc GSBI5_H_CLK>;
 244                         clock-names = "iface";
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         ranges;
 248
 249                         syscon-tcsr = <&tcsr>;
 250
 251                         gsbi5_serial: serial@16440000 {
 252                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 253                                 reg = <0x16440000 0x1000>,
 254                                       <0x16400000 0x1000>;
 255                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 256                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 257                                 clock-names = "core", "iface";
 258                                 status = "disabled";
 259                         };
 260                 };
 261
 262                 ssbi@500000 {
 263                         compatible = "qcom,ssbi";
 264                         reg = <0x500000 0x1000>;
 265                         qcom,controller-type = "pmic-arbiter";
 266
 267                         pmicintc: pmic {
 268                                 compatible = "qcom,pm8921";
 269                                 interrupt-parent = <&msmgpio>;
 270                                 interrupts = <104 IRQ_TYPE_LEVEL_LOW>;
 271                                 #interrupt-cells = <2>;
 272                                 interrupt-controller;
 273                                 #address-cells = <1>;
 274                                 #size-cells = <0>;
 275
 276                                 pwrkey@1c {
 277                                         compatible = "qcom,pm8921-pwrkey";
 278                                         reg = <0x1c>;
 279                                         interrupt-parent = <&pmicintc>;
 280                                         interrupts = <50 IRQ_TYPE_EDGE_RISING>,
 281                                                      <51 IRQ_TYPE_EDGE_RISING>;
 282                                         debounce = <15625>;
 283                                         pull-up;
 284                                 };
 285
 286                                 keypad@148 {
 287                                         compatible = "qcom,pm8921-keypad";
 288                                         reg = <0x148>;
 289                                         interrupt-parent = <&pmicintc>;
 290                                         interrupts = <74 IRQ_TYPE_EDGE_RISING>,
 291                                                      <75 IRQ_TYPE_EDGE_RISING>;
 292                                         debounce = <15>;
 293                                         scan-delay = <32>;
 294                                         row-hold = <91500>;
 295                                 };
 296
 297                                 rtc@11d {
 298                                         compatible = "qcom,pm8921-rtc";
 299                                         interrupt-parent = <&pmicintc>;
 300                                         interrupts = <39 IRQ_TYPE_EDGE_RISING>;
 301                                         reg = <0x11d>;
 302                                         allow-set-time;
 303                                 };
 304                         };
 305                 };
 306
 307                 rng@1a500000 {
 308                         compatible = "qcom,prng";
 309                         reg = <0x1a500000 0x200>;
 310                         clocks = <&gcc PRNG_CLK>;
 311                         clock-names = "core";
 312                 };
 313
 314                 sdcc3: mmc@12180000 {
 315                         compatible = "arm,pl18x", "arm,primecell";
 316                         arm,primecell-periphid = <0x00051180>;
 317                         status = "disabled";
 318                         reg = <0x12180000 0x8000>;
 319                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 320                         clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 321                         clock-names = "mclk", "apb_pclk";
 322                         bus-width = <4>;
 323                         cap-sd-highspeed;
 324                         cap-mmc-highspeed;
 325                         max-frequency = <192000000>;
 326                         no-1-8-v;
 327                         vmmc-supply = <&vsdcc_fixed>;
 328                 };
 329
 330                 sdcc1: mmc@12400000 {
 331                         status = "disabled";
 332                         compatible = "arm,pl18x", "arm,primecell";
 333                         arm,primecell-periphid = <0x00051180>;
 334                         reg = <0x12400000 0x8000>;
 335                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 337                         clock-names = "mclk", "apb_pclk";
 338                         bus-width = <8>;
 339                         max-frequency = <96000000>;
 340                         non-removable;
 341                         cap-sd-highspeed;
 342                         cap-mmc-highspeed;
 343                         vmmc-supply = <&vsdcc_fixed>;
 344                 };
 345
 346                 tcsr: syscon@1a400000 {
 347                         compatible = "qcom,tcsr-msm8960", "syscon";
 348                         reg = <0x1a400000 0x100>;
 349                 };
 350
 351                 gsbi1: gsbi@16000000 {
 352                         compatible = "qcom,gsbi-v1.0.0";
 353                         cell-index = <1>;
 354                         reg = <0x16000000 0x100>;
 355                         clocks = <&gcc GSBI1_H_CLK>;
 356                         clock-names = "iface";
 357                         #address-cells = <1>;
 358                         #size-cells = <1>;
 359                         ranges;
 360
 361                         gsbi1_spi: spi@16080000 {
 362                                 compatible = "qcom,spi-qup-v1.1.1";
 363                                 #address-cells = <1>;
 364                                 #size-cells = <0>;
 365                                 reg = <0x16080000 0x1000>;
 366                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 367                                 spi-max-frequency = <24000000>;
 368                                 cs-gpios = <&msmgpio 8 0>;
 369
 370                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 371                                 clock-names = "core", "iface";
 372                                 status = "disabled";
 373                         };
 374                 };
 375
 376                 usb1: usb@12500000 {
 377                         compatible = "qcom,ci-hdrc";
 378                         reg = <0x12500000 0x200>,
 379                               <0x12500200 0x200>;
 380                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 381                         clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
 382                         clock-names = "core", "iface";
 383                         assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
 384                         assigned-clock-rates = <60000000>;
 385                         resets = <&gcc USB_HS1_RESET>;
 386                         reset-names = "core";
 387                         phy_type = "ulpi";
 388                         ahb-burst-config = <0>;
 389                         phys = <&usb_hs1_phy>;
 390                         phy-names = "usb-phy";
 391                         #reset-cells = <1>;
 392                         status = "disabled";
 393
 394                         ulpi {
 395                                 usb_hs1_phy: phy {
 396                                         compatible = "qcom,usb-hs-phy-msm8960",
 397                                                      "qcom,usb-hs-phy";
 398                                         clocks = <&sleep_clk>, <&cxo_board>;
 399                                         clock-names = "sleep", "ref";
 400                                         resets = <&usb1 0>;
 401                                         reset-names = "por";
 402                                         #phy-cells = <0>;
 403                                 };
 404                         };
 405                 };
 406         };
 407 };