arch/arm/boot/dts/qcom/qcom-apq8064.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/soc/qcom,gsbi.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         model = "Qualcomm APQ8064";
  16         compatible = "qcom,apq8064";
  17         interrupt-parent = <&intc>;
  18
  19         reserved-memory {
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges;
  23
  24                 smem_region: smem@80000000 {
  25                         reg = <0x80000000 0x200000>;
  26                         no-map;
  27                 };
  28
  29                 wcnss_mem: wcnss@8f000000 {
  30                         reg = <0x8f000000 0x700000>;
  31                         no-map;
  32                 };
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 CPU0: cpu@0 {
  40                         compatible = "qcom,krait";
  41                         enable-method = "qcom,kpss-acc-v1";
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         next-level-cache = <&L2>;
  45                         qcom,acc = <&acc0>;
  46                         qcom,saw = <&saw0>;
  47                         cpu-idle-states = <&CPU_SPC>;
  48                 };
  49
  50                 CPU1: cpu@1 {
  51                         compatible = "qcom,krait";
  52                         enable-method = "qcom,kpss-acc-v1";
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         next-level-cache = <&L2>;
  56                         qcom,acc = <&acc1>;
  57                         qcom,saw = <&saw1>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 CPU2: cpu@2 {
  62                         compatible = "qcom,krait";
  63                         enable-method = "qcom,kpss-acc-v1";
  64                         device_type = "cpu";
  65                         reg = <2>;
  66                         next-level-cache = <&L2>;
  67                         qcom,acc = <&acc2>;
  68                         qcom,saw = <&saw2>;
  69                         cpu-idle-states = <&CPU_SPC>;
  70                 };
  71
  72                 CPU3: cpu@3 {
  73                         compatible = "qcom,krait";
  74                         enable-method = "qcom,kpss-acc-v1";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                         qcom,acc = <&acc3>;
  79                         qcom,saw = <&saw3>;
  80                         cpu-idle-states = <&CPU_SPC>;
  81                 };
  82
  83                 L2: l2-cache {
  84                         compatible = "cache";
  85                         cache-level = <2>;
  86                         cache-unified;
  87                 };
  88
  89                 idle-states {
  90                         CPU_SPC: spc {
  91                                 compatible = "qcom,idle-state-spc",
  92                                                 "arm,idle-state";
  93                                 entry-latency-us = <400>;
  94                                 exit-latency-us = <900>;
  95                                 min-residency-us = <3000>;
  96                         };
  97                 };
  98         };
  99
 100         memory@0 {
 101                 device_type = "memory";
 102                 reg = <0x0 0x0>;
 103         };
 104
 105         thermal-zones {
 106                 cpu0-thermal {
 107                         polling-delay-passive = <250>;
 108                         polling-delay = <1000>;
 109
 110                         thermal-sensors = <&tsens 7>;
 111                         coefficients = <1199 0>;
 112
 113                         trips {
 114                                 cpu_alert0: trip0 {
 115                                         temperature = <75000>;
 116                                         hysteresis = <2000>;
 117                                         type = "passive";
 118                                 };
 119                                 cpu_crit0: trip1 {
 120                                         temperature = <110000>;
 121                                         hysteresis = <2000>;
 122                                         type = "critical";
 123                                 };
 124                         };
 125                 };
 126
 127                 cpu1-thermal {
 128                         polling-delay-passive = <250>;
 129                         polling-delay = <1000>;
 130
 131                         thermal-sensors = <&tsens 8>;
 132                         coefficients = <1132 0>;
 133
 134                         trips {
 135                                 cpu_alert1: trip0 {
 136                                         temperature = <75000>;
 137                                         hysteresis = <2000>;
 138                                         type = "passive";
 139                                 };
 140                                 cpu_crit1: trip1 {
 141                                         temperature = <110000>;
 142                                         hysteresis = <2000>;
 143                                         type = "critical";
 144                                 };
 145                         };
 146                 };
 147
 148                 cpu2-thermal {
 149                         polling-delay-passive = <250>;
 150                         polling-delay = <1000>;
 151
 152                         thermal-sensors = <&tsens 9>;
 153                         coefficients = <1199 0>;
 154
 155                         trips {
 156                                 cpu_alert2: trip0 {
 157                                         temperature = <75000>;
 158                                         hysteresis = <2000>;
 159                                         type = "passive";
 160                                 };
 161                                 cpu_crit2: trip1 {
 162                                         temperature = <110000>;
 163                                         hysteresis = <2000>;
 164                                         type = "critical";
 165                                 };
 166                         };
 167                 };
 168
 169                 cpu3-thermal {
 170                         polling-delay-passive = <250>;
 171                         polling-delay = <1000>;
 172
 173                         thermal-sensors = <&tsens 10>;
 174                         coefficients = <1132 0>;
 175
 176                         trips {
 177                                 cpu_alert3: trip0 {
 178                                         temperature = <75000>;
 179                                         hysteresis = <2000>;
 180                                         type = "passive";
 181                                 };
 182                                 cpu_crit3: trip1 {
 183                                         temperature = <110000>;
 184                                         hysteresis = <2000>;
 185                                         type = "critical";
 186                                 };
 187                         };
 188                 };
 189         };
 190
 191         cpu-pmu {
 192                 compatible = "qcom,krait-pmu";
 193                 interrupts = <1 10 0x304>;
 194         };
 195
 196         clocks {
 197                 cxo_board: cxo_board {
 198                         compatible = "fixed-clock";
 199                         #clock-cells = <0>;
 200                         clock-frequency = <19200000>;
 201                 };
 202
 203                 pxo_board: pxo_board {
 204                         compatible = "fixed-clock";
 205                         #clock-cells = <0>;
 206                         clock-frequency = <27000000>;
 207                 };
 208
 209                 sleep_clk: sleep_clk {
 210                         compatible = "fixed-clock";
 211                         #clock-cells = <0>;
 212                         clock-frequency = <32768>;
 213                 };
 214         };
 215
 216         sfpb_mutex: hwmutex {
 217                 compatible = "qcom,sfpb-mutex";
 218                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 219                 #hwlock-cells = <1>;
 220         };
 221
 222         smem {
 223                 compatible = "qcom,smem";
 224                 memory-region = <&smem_region>;
 225
 226                 hwlocks = <&sfpb_mutex 3>;
 227         };
 228
 229         smd {
 230                 compatible = "qcom,smd";
 231
 232                 modem-edge {
 233                         interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
 234
 235                         qcom,ipc = <&l2cc 8 3>;
 236                         qcom,smd-edge = <0>;
 237
 238                         status = "disabled";
 239                 };
 240
 241                 q6-edge {
 242                         interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
 243
 244                         qcom,ipc = <&l2cc 8 15>;
 245                         qcom,smd-edge = <1>;
 246
 247                         status = "disabled";
 248                 };
 249
 250                 dsps-edge {
 251                         interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
 252
 253                         qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
 254                         qcom,smd-edge = <3>;
 255
 256                         status = "disabled";
 257                 };
 258
 259                 riva-edge {
 260                         interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
 261
 262                         qcom,ipc = <&l2cc 8 25>;
 263                         qcom,smd-edge = <6>;
 264
 265                         status = "disabled";
 266                 };
 267         };
 268
 269         smsm {
 270                 compatible = "qcom,smsm";
 271
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274
 275                 qcom,ipc-1 = <&l2cc 8 4>;
 276                 qcom,ipc-2 = <&l2cc 8 14>;
 277                 qcom,ipc-3 = <&l2cc 8 23>;
 278                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
 279
 280                 apps_smsm: apps@0 {
 281                         reg = <0>;
 282                         #qcom,smem-state-cells = <1>;
 283                 };
 284
 285                 modem_smsm: modem@1 {
 286                         reg = <1>;
 287                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
 288
 289                         interrupt-controller;
 290                         #interrupt-cells = <2>;
 291                 };
 292
 293                 q6_smsm: q6@2 {
 294                         reg = <2>;
 295                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
 296
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 wcnss_smsm: wcnss@3 {
 302                         reg = <3>;
 303                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
 304
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                 };
 308
 309                 dsps_smsm: dsps@4 {
 310                         reg = <4>;
 311                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
 312
 313                         interrupt-controller;
 314                         #interrupt-cells = <2>;
 315                 };
 316         };
 317
 318         firmware {
 319                 scm {
 320                         compatible = "qcom,scm-apq8064", "qcom,scm";
 321
 322                         clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
 323                         clock-names = "core";
 324                 };
 325         };
 326
 327
 328         /*
 329          * These channels from the ADC are simply hardware monitors.
 330          * That is why the ADC is referred to as "HKADC" - HouseKeeping
 331          * ADC.
 332          */
 333         iio-hwmon {
 334                 compatible = "iio-hwmon";
 335                 io-channels = <&xoadc 0x00 0x01>, /* Battery */
 336                             <&xoadc 0x00 0x02>, /* DC in (charger) */
 337                             <&xoadc 0x00 0x04>, /* VPH the main system voltage */
 338                             <&xoadc 0x00 0x0b>, /* Die temperature */
 339                             <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
 340                             <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
 341                             <&xoadc 0x00 0x0e>; /* Charger temperature */
 342         };
 343
 344         soc: soc {
 345                 #address-cells = <1>;
 346                 #size-cells = <1>;
 347                 ranges;
 348                 compatible = "simple-bus";
 349
 350                 tlmm_pinmux: pinctrl@800000 {
 351                         compatible = "qcom,apq8064-pinctrl";
 352                         reg = <0x800000 0x4000>;
 353
 354                         gpio-controller;
 355                         gpio-ranges = <&tlmm_pinmux 0 0 90>;
 356                         #gpio-cells = <2>;
 357                         interrupt-controller;
 358                         #interrupt-cells = <2>;
 359                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 360
 361                         pinctrl-names = "default";
 362                         pinctrl-0 = <&ps_hold>;
 363                 };
 364
 365                 sfpb_wrapper_mutex: syscon@1200000 {
 366                         compatible = "syscon";
 367                         reg = <0x01200000 0x8000>;
 368                 };
 369
 370                 intc: interrupt-controller@2000000 {
 371                         compatible = "qcom,msm-qgic2";
 372                         interrupt-controller;
 373                         #interrupt-cells = <3>;
 374                         reg = <0x02000000 0x1000>,
 375                               <0x02002000 0x1000>;
 376                 };
 377
 378                 timer@200a000 {
 379                         compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
 380                                      "qcom,msm-timer";
 381                         interrupts = <1 1 0x301>,
 382                                      <1 2 0x301>,
 383                                      <1 3 0x301>;
 384                         reg = <0x0200a000 0x100>;
 385                         clock-frequency = <27000000>;
 386                         cpu-offset = <0x80000>;
 387                 };
 388
 389                 acc0: clock-controller@2088000 {
 390                         compatible = "qcom,kpss-acc-v1";
 391                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 392                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 393                         clock-names = "pll8_vote", "pxo";
 394                         clock-output-names = "acpu0_aux";
 395                         #clock-cells = <0>;
 396                 };
 397
 398                 acc1: clock-controller@2098000 {
 399                         compatible = "qcom,kpss-acc-v1";
 400                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 401                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 402                         clock-names = "pll8_vote", "pxo";
 403                         clock-output-names = "acpu1_aux";
 404                         #clock-cells = <0>;
 405                 };
 406
 407                 acc2: clock-controller@20a8000 {
 408                         compatible = "qcom,kpss-acc-v1";
 409                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 410                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 411                         clock-names = "pll8_vote", "pxo";
 412                         clock-output-names = "acpu2_aux";
 413                         #clock-cells = <0>;
 414                 };
 415
 416                 acc3: clock-controller@20b8000 {
 417                         compatible = "qcom,kpss-acc-v1";
 418                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 419                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 420                         clock-names = "pll8_vote", "pxo";
 421                         clock-output-names = "acpu3_aux";
 422                         #clock-cells = <0>;
 423                 };
 424
 425                 saw0: power-controller@2089000 {
 426                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 427                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 428                         regulator;
 429                 };
 430
 431                 saw1: power-controller@2099000 {
 432                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 433                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 434                         regulator;
 435                 };
 436
 437                 saw2: power-controller@20a9000 {
 438                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 439                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 440                         regulator;
 441                 };
 442
 443                 saw3: power-controller@20b9000 {
 444                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 445                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 446                         regulator;
 447                 };
 448
 449                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
 450                         compatible = "syscon";
 451                         reg = <0x12100000 0x10000>;
 452                 };
 453
 454                 gsbi1: gsbi@12440000 {
 455                         status = "disabled";
 456                         compatible = "qcom,gsbi-v1.0.0";
 457                         cell-index = <1>;
 458                         reg = <0x12440000 0x100>;
 459                         clocks = <&gcc GSBI1_H_CLK>;
 460                         clock-names = "iface";
 461                         #address-cells = <1>;
 462                         #size-cells = <1>;
 463                         ranges;
 464
 465                         syscon-tcsr = <&tcsr>;
 466
 467                         gsbi1_serial: serial@12450000 {
 468                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 469                                 reg = <0x12450000 0x100>,
 470                                       <0x12400000 0x03>;
 471                                 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 473                                 clock-names = "core", "iface";
 474                                 status = "disabled";
 475                         };
 476
 477                         gsbi1_i2c: i2c@12460000 {
 478                                 compatible = "qcom,i2c-qup-v1.1.1";
 479                                 pinctrl-0 = <&i2c1_pins>;
 480                                 pinctrl-1 = <&i2c1_pins_sleep>;
 481                                 pinctrl-names = "default", "sleep";
 482                                 reg = <0x12460000 0x1000>;
 483                                 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
 484                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 485                                 clock-names = "core", "iface";
 486                                 #address-cells = <1>;
 487                                 #size-cells = <0>;
 488                                 status = "disabled";
 489                         };
 490
 491                 };
 492
 493                 gsbi2: gsbi@12480000 {
 494                         status = "disabled";
 495                         compatible = "qcom,gsbi-v1.0.0";
 496                         cell-index = <2>;
 497                         reg = <0x12480000 0x100>;
 498                         clocks = <&gcc GSBI2_H_CLK>;
 499                         clock-names = "iface";
 500                         #address-cells = <1>;
 501                         #size-cells = <1>;
 502                         ranges;
 503
 504                         syscon-tcsr = <&tcsr>;
 505
 506                         gsbi2_i2c: i2c@124a0000 {
 507                                 compatible = "qcom,i2c-qup-v1.1.1";
 508                                 reg = <0x124a0000 0x1000>;
 509                                 pinctrl-0 = <&i2c2_pins>;
 510                                 pinctrl-1 = <&i2c2_pins_sleep>;
 511                                 pinctrl-names = "default", "sleep";
 512                                 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
 513                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 514                                 clock-names = "core", "iface";
 515                                 #address-cells = <1>;
 516                                 #size-cells = <0>;
 517                                 status = "disabled";
 518                         };
 519                 };
 520
 521                 gsbi3: gsbi@16200000 {
 522                         status = "disabled";
 523                         compatible = "qcom,gsbi-v1.0.0";
 524                         cell-index = <3>;
 525                         reg = <0x16200000 0x100>;
 526                         clocks = <&gcc GSBI3_H_CLK>;
 527                         clock-names = "iface";
 528                         #address-cells = <1>;
 529                         #size-cells = <1>;
 530                         ranges;
 531                         gsbi3_i2c: i2c@16280000 {
 532                                 compatible = "qcom,i2c-qup-v1.1.1";
 533                                 pinctrl-0 = <&i2c3_pins>;
 534                                 pinctrl-1 = <&i2c3_pins_sleep>;
 535                                 pinctrl-names = "default", "sleep";
 536                                 reg = <0x16280000 0x1000>;
 537                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 538                                 clocks = <&gcc GSBI3_QUP_CLK>,
 539                                          <&gcc GSBI3_H_CLK>;
 540                                 clock-names = "core", "iface";
 541                                 #address-cells = <1>;
 542                                 #size-cells = <0>;
 543                                 status = "disabled";
 544                         };
 545                 };
 546
 547                 gsbi4: gsbi@16300000 {
 548                         status = "disabled";
 549                         compatible = "qcom,gsbi-v1.0.0";
 550                         cell-index = <4>;
 551                         reg = <0x16300000 0x03>;
 552                         clocks = <&gcc GSBI4_H_CLK>;
 553                         clock-names = "iface";
 554                         #address-cells = <1>;
 555                         #size-cells = <1>;
 556                         ranges;
 557
 558                         gsbi4_i2c: i2c@16380000 {
 559                                 compatible = "qcom,i2c-qup-v1.1.1";
 560                                 pinctrl-0 = <&i2c4_pins>;
 561                                 pinctrl-1 = <&i2c4_pins_sleep>;
 562                                 pinctrl-names = "default", "sleep";
 563                                 reg = <0x16380000 0x1000>;
 564                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 565                                 clocks = <&gcc GSBI4_QUP_CLK>,
 566                                          <&gcc GSBI4_H_CLK>;
 567                                 clock-names = "core", "iface";
 568                                 status = "disabled";
 569                         };
 570                 };
 571
 572                 gsbi5: gsbi@1a200000 {
 573                         status = "disabled";
 574                         compatible = "qcom,gsbi-v1.0.0";
 575                         cell-index = <5>;
 576                         reg = <0x1a200000 0x03>;
 577                         clocks = <&gcc GSBI5_H_CLK>;
 578                         clock-names = "iface";
 579                         #address-cells = <1>;
 580                         #size-cells = <1>;
 581                         ranges;
 582
 583                         gsbi5_serial: serial@1a240000 {
 584                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 585                                 reg = <0x1a240000 0x100>,
 586                                       <0x1a200000 0x03>;
 587                                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 588                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 589                                 clock-names = "core", "iface";
 590                                 status = "disabled";
 591                         };
 592
 593                         gsbi5_spi: spi@1a280000 {
 594                                 compatible = "qcom,spi-qup-v1.1.1";
 595                                 reg = <0x1a280000 0x1000>;
 596                                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 597                                 pinctrl-0 = <&spi5_default>;
 598                                 pinctrl-1 = <&spi5_sleep>;
 599                                 pinctrl-names = "default", "sleep";
 600                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 601                                 clock-names = "core", "iface";
 602                                 status = "disabled";
 603                                 #address-cells = <1>;
 604                                 #size-cells = <0>;
 605                         };
 606                 };
 607
 608                 gsbi6: gsbi@16500000 {
 609                         status = "disabled";
 610                         compatible = "qcom,gsbi-v1.0.0";
 611                         cell-index = <6>;
 612                         reg = <0x16500000 0x03>;
 613                         clocks = <&gcc GSBI6_H_CLK>;
 614                         clock-names = "iface";
 615                         #address-cells = <1>;
 616                         #size-cells = <1>;
 617                         ranges;
 618
 619                         gsbi6_serial: serial@16540000 {
 620                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 621                                 reg = <0x16540000 0x100>,
 622                                       <0x16500000 0x03>;
 623                                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 624                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 625                                 clock-names = "core", "iface";
 626                                 status = "disabled";
 627                         };
 628
 629                         gsbi6_i2c: i2c@16580000 {
 630                                 compatible = "qcom,i2c-qup-v1.1.1";
 631                                 pinctrl-0 = <&i2c6_pins>;
 632                                 pinctrl-1 = <&i2c6_pins_sleep>;
 633                                 pinctrl-names = "default", "sleep";
 634                                 reg = <0x16580000 0x1000>;
 635                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&gcc GSBI6_QUP_CLK>,
 637                                          <&gcc GSBI6_H_CLK>;
 638                                 clock-names = "core", "iface";
 639                                 status = "disabled";
 640                         };
 641                 };
 642
 643                 gsbi7: gsbi@16600000 {
 644                         status = "disabled";
 645                         compatible = "qcom,gsbi-v1.0.0";
 646                         cell-index = <7>;
 647                         reg = <0x16600000 0x100>;
 648                         clocks = <&gcc GSBI7_H_CLK>;
 649                         clock-names = "iface";
 650                         #address-cells = <1>;
 651                         #size-cells = <1>;
 652                         ranges;
 653                         syscon-tcsr = <&tcsr>;
 654
 655                         gsbi7_serial: serial@16640000 {
 656                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 657                                 reg = <0x16640000 0x1000>,
 658                                       <0x16600000 0x1000>;
 659                                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 660                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 661                                 clock-names = "core", "iface";
 662                                 status = "disabled";
 663                         };
 664
 665                         gsbi7_i2c: i2c@16680000 {
 666                                 compatible = "qcom,i2c-qup-v1.1.1";
 667                                 pinctrl-0 = <&i2c7_pins>;
 668                                 pinctrl-1 = <&i2c7_pins_sleep>;
 669                                 pinctrl-names = "default", "sleep";
 670                                 reg = <0x16680000 0x1000>;
 671                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 672                                 clocks = <&gcc GSBI7_QUP_CLK>,
 673                                          <&gcc GSBI7_H_CLK>;
 674                                 clock-names = "core", "iface";
 675                                 status = "disabled";
 676                         };
 677                 };
 678
 679                 rng@1a500000 {
 680                         compatible = "qcom,prng";
 681                         reg = <0x1a500000 0x200>;
 682                         clocks = <&gcc PRNG_CLK>;
 683                         clock-names = "core";
 684                 };
 685
 686                 ssbi@c00000 {
 687                         compatible = "qcom,ssbi";
 688                         reg = <0x00c00000 0x1000>;
 689                         qcom,controller-type = "pmic-arbiter";
 690
 691                         pm8821: pmic {
 692                                 compatible = "qcom,pm8821";
 693                                 interrupt-parent = <&tlmm_pinmux>;
 694                                 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
 695                                 #interrupt-cells = <2>;
 696                                 interrupt-controller;
 697                                 #address-cells = <1>;
 698                                 #size-cells = <0>;
 699
 700                                 pm8821_mpps: mpps@50 {
 701                                         compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
 702                                         reg = <0x50>;
 703                                         interrupt-controller;
 704                                         #interrupt-cells = <2>;
 705                                         gpio-controller;
 706                                         #gpio-cells = <2>;
 707                                         gpio-ranges = <&pm8821_mpps 0 0 4>;
 708                                 };
 709                         };
 710                 };
 711
 712                 ssbi@500000 {
 713                         compatible = "qcom,ssbi";
 714                         reg = <0x00500000 0x1000>;
 715                         qcom,controller-type = "pmic-arbiter";
 716
 717                         pmicintc: pmic {
 718                                 compatible = "qcom,pm8921";
 719                                 interrupt-parent = <&tlmm_pinmux>;
 720                                 interrupts = <74 8>;
 721                                 #interrupt-cells = <2>;
 722                                 interrupt-controller;
 723                                 #address-cells = <1>;
 724                                 #size-cells = <0>;
 725
 726                                 pm8921_gpio: gpio@150 {
 727
 728                                         compatible = "qcom,pm8921-gpio",
 729                                                      "qcom,ssbi-gpio";
 730                                         reg = <0x150>;
 731                                         interrupt-controller;
 732                                         #interrupt-cells = <2>;
 733                                         gpio-controller;
 734                                         gpio-ranges = <&pm8921_gpio 0 0 44>;
 735                                         #gpio-cells = <2>;
 736
 737                                 };
 738
 739                                 pm8921_mpps: mpps@50 {
 740                                         compatible = "qcom,pm8921-mpp",
 741                                                      "qcom,ssbi-mpp";
 742                                         reg = <0x50>;
 743                                         gpio-controller;
 744                                         #gpio-cells = <2>;
 745                                         gpio-ranges = <&pm8921_mpps 0 0 12>;
 746                                         interrupt-controller;
 747                                         #interrupt-cells = <2>;
 748                                 };
 749
 750                                 rtc@11d {
 751                                         compatible = "qcom,pm8921-rtc";
 752                                         interrupt-parent = <&pmicintc>;
 753                                         interrupts = <39 1>;
 754                                         reg = <0x11d>;
 755                                         allow-set-time;
 756                                 };
 757
 758                                 pwrkey@1c {
 759                                         compatible = "qcom,pm8921-pwrkey";
 760                                         reg = <0x1c>;
 761                                         interrupt-parent = <&pmicintc>;
 762                                         interrupts = <50 1>, <51 1>;
 763                                         debounce = <15625>;
 764                                         pull-up;
 765                                 };
 766
 767                                 xoadc: xoadc@197 {
 768                                         compatible = "qcom,pm8921-adc";
 769                                         reg = <197>;
 770                                         interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
 771                                         #address-cells = <2>;
 772                                         #size-cells = <0>;
 773                                         #io-channel-cells = <2>;
 774
 775                                         vcoin: adc-channel@0 {
 776                                                 reg = <0x00 0x00>;
 777                                         };
 778                                         vbat: adc-channel@1 {
 779                                                 reg = <0x00 0x01>;
 780                                         };
 781                                         dcin: adc-channel@2 {
 782                                                 reg = <0x00 0x02>;
 783                                         };
 784                                         vph_pwr: adc-channel@4 {
 785                                                 reg = <0x00 0x04>;
 786                                         };
 787                                         batt_therm: adc-channel@8 {
 788                                                 reg = <0x00 0x08>;
 789                                         };
 790                                         batt_id: adc-channel@9 {
 791                                                 reg = <0x00 0x09>;
 792                                         };
 793                                         usb_vbus: adc-channel@a {
 794                                                 reg = <0x00 0x0a>;
 795                                         };
 796                                         die_temp: adc-channel@b {
 797                                                 reg = <0x00 0x0b>;
 798                                         };
 799                                         ref_625mv: adc-channel@c {
 800                                                 reg = <0x00 0x0c>;
 801                                         };
 802                                         ref_1250mv: adc-channel@d {
 803                                                 reg = <0x00 0x0d>;
 804                                         };
 805                                         chg_temp: adc-channel@e {
 806                                                 reg = <0x00 0x0e>;
 807                                         };
 808                                         ref_muxoff: adc-channel@f {
 809                                                 reg = <0x00 0x0f>;
 810                                         };
 811                                 };
 812                         };
 813                 };
 814
 815                 qfprom: qfprom@700000 {
 816                         compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
 817                         reg = <0x00700000 0x1000>;
 818                         #address-cells = <1>;
 819                         #size-cells = <1>;
 820                         ranges;
 821                         tsens_calib: calib@404 {
 822                                 reg = <0x404 0x10>;
 823                         };
 824                         tsens_backup: backup_calib@414 {
 825                                 reg = <0x414 0x10>;
 826                         };
 827                 };
 828
 829                 gcc: clock-controller@900000 {
 830                         compatible = "qcom,gcc-apq8064", "syscon";
 831                         reg = <0x00900000 0x4000>;
 832                         #clock-cells = <1>;
 833                         #power-domain-cells = <1>;
 834                         #reset-cells = <1>;
 835                         clocks = <&cxo_board>,
 836                                  <&pxo_board>,
 837                                  <&lcc PLL4>;
 838                         clock-names = "cxo", "pxo", "pll4";
 839
 840                         tsens: thermal-sensor {
 841                                 compatible = "qcom,msm8960-tsens";
 842
 843                                 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 844                                 nvmem-cell-names = "calib", "calib_backup";
 845                                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 846                                 interrupt-names = "uplow";
 847
 848                                 #qcom,sensors = <11>;
 849                                 #thermal-sensor-cells = <1>;
 850                         };
 851                 };
 852
 853                 lcc: clock-controller@28000000 {
 854                         compatible = "qcom,lcc-apq8064";
 855                         reg = <0x28000000 0x1000>;
 856                         #clock-cells = <1>;
 857                         #reset-cells = <1>;
 858                         clocks = <&pxo_board>,
 859                                  <&gcc PLL4_VOTE>,
 860                                  <0>,
 861                                  <0>, <0>,
 862                                  <0>, <0>,
 863                                  <0>;
 864                         clock-names = "pxo",
 865                                       "pll4_vote",
 866                                       "mi2s_codec_clk",
 867                                       "codec_i2s_mic_codec_clk",
 868                                       "spare_i2s_mic_codec_clk",
 869                                       "codec_i2s_spkr_codec_clk",
 870                                       "spare_i2s_spkr_codec_clk",
 871                                       "pcm_codec_clk";
 872                 };
 873
 874                 mmcc: clock-controller@4000000 {
 875                         compatible = "qcom,mmcc-apq8064";
 876                         reg = <0x4000000 0x1000>;
 877                         #clock-cells = <1>;
 878                         #power-domain-cells = <1>;
 879                         #reset-cells = <1>;
 880                         clocks = <&pxo_board>,
 881                                  <&gcc PLL3>,
 882                                  <&gcc PLL8_VOTE>,
 883                                  <&dsi0_phy 1>,
 884                                  <&dsi0_phy 0>,
 885                                  <&dsi1_phy 1>,
 886                                  <&dsi1_phy 0>,
 887                                  <&hdmi_phy>;
 888                         clock-names = "pxo",
 889                                       "pll3",
 890                                       "pll8_vote",
 891                                       "dsi1pll",
 892                                       "dsi1pllbyte",
 893                                       "dsi2pll",
 894                                       "dsi2pllbyte",
 895                                       "hdmipll";
 896                 };
 897
 898                 l2cc: clock-controller@2011000 {
 899                         compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
 900                         reg = <0x2011000 0x1000>;
 901                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
 902                         clock-names = "pll8_vote", "pxo";
 903                         #clock-cells = <0>;
 904                 };
 905
 906                 rpm: rpm@108000 {
 907                         compatible = "qcom,rpm-apq8064";
 908                         reg = <0x108000 0x1000>;
 909                         qcom,ipc = <&l2cc 0x8 2>;
 910
 911                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 912                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 913                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 914                         interrupt-names = "ack", "err", "wakeup";
 915
 916                         rpmcc: clock-controller {
 917                                 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
 918                                 #clock-cells = <1>;
 919                                 clocks = <&pxo_board>, <&cxo_board>;
 920                                 clock-names = "pxo", "cxo";
 921                         };
 922
 923                         regulators {
 924                                 compatible = "qcom,rpm-pm8921-regulators";
 925
 926                                 pm8921_s1: s1 {};
 927                                 pm8921_s2: s2 {};
 928                                 pm8921_s3: s3 {};
 929                                 pm8921_s4: s4 {};
 930                                 pm8921_s7: s7 {};
 931                                 pm8921_s8: s8 {};
 932
 933                                 pm8921_l1: l1 {};
 934                                 pm8921_l2: l2 {};
 935                                 pm8921_l3: l3 {};
 936                                 pm8921_l4: l4 {};
 937                                 pm8921_l5: l5 {};
 938                                 pm8921_l6: l6 {};
 939                                 pm8921_l7: l7 {};
 940                                 pm8921_l8: l8 {};
 941                                 pm8921_l9: l9 {};
 942                                 pm8921_l10: l10 {};
 943                                 pm8921_l11: l11 {};
 944                                 pm8921_l12: l12 {};
 945                                 pm8921_l14: l14 {};
 946                                 pm8921_l15: l15 {};
 947                                 pm8921_l16: l16 {};
 948                                 pm8921_l17: l17 {};
 949                                 pm8921_l18: l18 {};
 950                                 pm8921_l21: l21 {};
 951                                 pm8921_l22: l22 {};
 952                                 pm8921_l23: l23 {};
 953                                 pm8921_l24: l24 {};
 954                                 pm8921_l25: l25 {};
 955                                 pm8921_l26: l26 {};
 956                                 pm8921_l27: l27 {};
 957                                 pm8921_l28: l28 {};
 958                                 pm8921_l29: l29 {};
 959
 960                                 pm8921_lvs1: lvs1 {};
 961                                 pm8921_lvs2: lvs2 {};
 962                                 pm8921_lvs3: lvs3 {};
 963                                 pm8921_lvs4: lvs4 {};
 964                                 pm8921_lvs5: lvs5 {};
 965                                 pm8921_lvs6: lvs6 {};
 966                                 pm8921_lvs7: lvs7 {};
 967
 968                                 pm8921_usb_switch: usb-switch {};
 969
 970                                 pm8921_hdmi_switch: hdmi-switch {
 971                                         bias-pull-down;
 972                                 };
 973
 974                                 pm8921_ncp: ncp {};
 975                         };
 976                 };
 977
 978                 usb1: usb@12500000 {
 979                         compatible = "qcom,ci-hdrc";
 980                         reg = <0x12500000 0x200>,
 981                               <0x12500200 0x200>;
 982                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 983                         clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
 984                         clock-names = "core", "iface";
 985                         assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
 986                         assigned-clock-rates = <60000000>;
 987                         resets = <&gcc USB_HS1_RESET>;
 988                         reset-names = "core";
 989                         phy_type = "ulpi";
 990                         ahb-burst-config = <0>;
 991                         phys = <&usb_hs1_phy>;
 992                         phy-names = "usb-phy";
 993                         status = "disabled";
 994                         #reset-cells = <1>;
 995
 996                         ulpi {
 997                                 usb_hs1_phy: phy {
 998                                         compatible = "qcom,usb-hs-phy-apq8064",
 999                                                      "qcom,usb-hs-phy";
1000                                         clocks = <&sleep_clk>, <&cxo_board>;
1001                                         clock-names = "sleep", "ref";
1002                                         resets = <&usb1 0>;
1003                                         reset-names = "por";
1004                                         #phy-cells = <0>;
1005                                 };
1006                         };
1007                 };
1008
1009                 usb3: usb@12520000 {
1010                         compatible = "qcom,ci-hdrc";
1011                         reg = <0x12520000 0x200>,
1012                               <0x12520200 0x200>;
1013                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1014                         clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
1015                         clock-names = "core", "iface";
1016                         assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
1017                         assigned-clock-rates = <60000000>;
1018                         resets = <&gcc USB_HS3_RESET>;
1019                         reset-names = "core";
1020                         phy_type = "ulpi";
1021                         ahb-burst-config = <0>;
1022                         phys = <&usb_hs3_phy>;
1023                         phy-names = "usb-phy";
1024                         status = "disabled";
1025                         #reset-cells = <1>;
1026
1027                         ulpi {
1028                                 usb_hs3_phy: phy {
1029                                         compatible = "qcom,usb-hs-phy-apq8064",
1030                                                      "qcom,usb-hs-phy";
1031                                         #phy-cells = <0>;
1032                                         clocks = <&sleep_clk>, <&cxo_board>;
1033                                         clock-names = "sleep", "ref";
1034                                         resets = <&usb3 0>;
1035                                         reset-names = "por";
1036                                 };
1037                         };
1038                 };
1039
1040                 usb4: usb@12530000 {
1041                         compatible = "qcom,ci-hdrc";
1042                         reg = <0x12530000 0x200>,
1043                               <0x12530200 0x200>;
1044                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1045                         clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1046                         clock-names = "core", "iface";
1047                         assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1048                         assigned-clock-rates = <60000000>;
1049                         resets = <&gcc USB_HS4_RESET>;
1050                         reset-names = "core";
1051                         phy_type = "ulpi";
1052                         ahb-burst-config = <0>;
1053                         phys = <&usb_hs4_phy>;
1054                         phy-names = "usb-phy";
1055                         status = "disabled";
1056                         #reset-cells = <1>;
1057
1058                         ulpi {
1059                                 usb_hs4_phy: phy {
1060                                         compatible = "qcom,usb-hs-phy-apq8064",
1061                                                      "qcom,usb-hs-phy";
1062                                         #phy-cells = <0>;
1063                                         clocks = <&sleep_clk>, <&cxo_board>;
1064                                         clock-names = "sleep", "ref";
1065                                         resets = <&usb4 0>;
1066                                         reset-names = "por";
1067                                 };
1068                         };
1069                 };
1070
1071                 sata_phy0: phy@1b400000 {
1072                         compatible = "qcom,apq8064-sata-phy";
1073                         status = "disabled";
1074                         reg = <0x1b400000 0x200>;
1075                         reg-names = "phy_mem";
1076                         clocks = <&gcc SATA_PHY_CFG_CLK>;
1077                         clock-names = "cfg";
1078                         #phy-cells = <0>;
1079                 };
1080
1081                 sata0: sata@29000000 {
1082                         compatible = "qcom,apq8064-ahci", "generic-ahci";
1083                         status   = "disabled";
1084                         reg      = <0x29000000 0x180>;
1085                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1086
1087                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
1088                                  <&gcc SATA_H_CLK>,
1089                                  <&gcc SATA_A_CLK>,
1090                                  <&gcc SATA_RXOOB_CLK>,
1091                                  <&gcc SATA_PMALIVE_CLK>;
1092                         clock-names = "slave_iface",
1093                                       "iface",
1094                                       "bus",
1095                                       "rxoob",
1096                                       "core_pmalive";
1097
1098                         assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1099                                           <&gcc SATA_PMALIVE_CLK>;
1100                         assigned-clock-rates = <100000000>, <100000000>;
1101
1102                         phys = <&sata_phy0>;
1103                         phy-names = "sata-phy";
1104                         ports-implemented = <0x1>;
1105                 };
1106
1107                 sdcc3: mmc@12180000 {
1108                         compatible = "arm,pl18x", "arm,primecell";
1109                         arm,primecell-periphid = <0x00051180>;
1110                         status = "disabled";
1111                         reg = <0x12180000 0x2000>;
1112                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1113                         clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1114                         clock-names = "mclk", "apb_pclk";
1115                         bus-width = <4>;
1116                         cap-sd-highspeed;
1117                         cap-mmc-highspeed;
1118                         max-frequency = <192000000>;
1119                         no-1-8-v;
1120                         dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1121                         dma-names = "tx", "rx";
1122                 };
1123
1124                 sdcc3bam: dma-controller@12182000 {
1125                         compatible = "qcom,bam-v1.3.0";
1126                         reg = <0x12182000 0x8000>;
1127                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1128                         clocks = <&gcc SDC3_H_CLK>;
1129                         clock-names = "bam_clk";
1130                         #dma-cells = <1>;
1131                         qcom,ee = <0>;
1132                 };
1133
1134                 sdcc4: mmc@121c0000 {
1135                         compatible = "arm,pl18x", "arm,primecell";
1136                         arm,primecell-periphid = <0x00051180>;
1137                         status = "disabled";
1138                         reg = <0x121c0000 0x2000>;
1139                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1140                         clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1141                         clock-names = "mclk", "apb_pclk";
1142                         bus-width = <4>;
1143                         cap-sd-highspeed;
1144                         cap-mmc-highspeed;
1145                         max-frequency = <48000000>;
1146                         dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1147                         dma-names = "tx", "rx";
1148                         pinctrl-names = "default";
1149                         pinctrl-0 = <&sdc4_gpios>;
1150                 };
1151
1152                 sdcc4bam: dma-controller@121c2000 {
1153                         compatible = "qcom,bam-v1.3.0";
1154                         reg = <0x121c2000 0x8000>;
1155                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1156                         clocks = <&gcc SDC4_H_CLK>;
1157                         clock-names = "bam_clk";
1158                         #dma-cells = <1>;
1159                         qcom,ee = <0>;
1160                 };
1161
1162                 sdcc1: mmc@12400000 {
1163                         status = "disabled";
1164                         compatible = "arm,pl18x", "arm,primecell";
1165                         pinctrl-names = "default";
1166                         pinctrl-0 = <&sdcc1_pins>;
1167                         arm,primecell-periphid = <0x00051180>;
1168                         reg = <0x12400000 0x2000>;
1169                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1170                         clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1171                         clock-names = "mclk", "apb_pclk";
1172                         bus-width = <8>;
1173                         max-frequency = <96000000>;
1174                         non-removable;
1175                         cap-sd-highspeed;
1176                         cap-mmc-highspeed;
1177                         dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1178                         dma-names = "tx", "rx";
1179                 };
1180
1181                 sdcc1bam: dma-controller@12402000 {
1182                         compatible = "qcom,bam-v1.3.0";
1183                         reg = <0x12402000 0x8000>;
1184                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1185                         clocks = <&gcc SDC1_H_CLK>;
1186                         clock-names = "bam_clk";
1187                         #dma-cells = <1>;
1188                         qcom,ee = <0>;
1189                 };
1190
1191                 tcsr: syscon@1a400000 {
1192                         compatible = "qcom,tcsr-apq8064", "syscon";
1193                         reg = <0x1a400000 0x100>;
1194                 };
1195
1196                 gpu: adreno-3xx@4300000 {
1197                         compatible = "qcom,adreno-320.2", "qcom,adreno";
1198                         reg = <0x04300000 0x20000>;
1199                         reg-names = "kgsl_3d0_reg_memory";
1200                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1201                         interrupt-names = "kgsl_3d0_irq";
1202                         clock-names =
1203                             "core",
1204                             "iface",
1205                             "mem",
1206                             "mem_iface";
1207                         clocks =
1208                             <&mmcc GFX3D_CLK>,
1209                             <&mmcc GFX3D_AHB_CLK>,
1210                             <&mmcc GFX3D_AXI_CLK>,
1211                             <&mmcc MMSS_IMEM_AHB_CLK>;
1212
1213                         iommus = <&gfx3d 0
1214                                   &gfx3d 1
1215                                   &gfx3d 2
1216                                   &gfx3d 3
1217                                   &gfx3d 4
1218                                   &gfx3d 5
1219                                   &gfx3d 6
1220                                   &gfx3d 7
1221                                   &gfx3d 8
1222                                   &gfx3d 9
1223                                   &gfx3d 10
1224                                   &gfx3d 11
1225                                   &gfx3d 12
1226                                   &gfx3d 13
1227                                   &gfx3d 14
1228                                   &gfx3d 15
1229                                   &gfx3d 16
1230                                   &gfx3d 17
1231                                   &gfx3d 18
1232                                   &gfx3d 19
1233                                   &gfx3d 20
1234                                   &gfx3d 21
1235                                   &gfx3d 22
1236                                   &gfx3d 23
1237                                   &gfx3d 24
1238                                   &gfx3d 25
1239                                   &gfx3d 26
1240                                   &gfx3d 27
1241                                   &gfx3d 28
1242                                   &gfx3d 29
1243                                   &gfx3d 30
1244                                   &gfx3d 31
1245                                   &gfx3d1 0
1246                                   &gfx3d1 1
1247                                   &gfx3d1 2
1248                                   &gfx3d1 3
1249                                   &gfx3d1 4
1250                                   &gfx3d1 5
1251                                   &gfx3d1 6
1252                                   &gfx3d1 7
1253                                   &gfx3d1 8
1254                                   &gfx3d1 9
1255                                   &gfx3d1 10
1256                                   &gfx3d1 11
1257                                   &gfx3d1 12
1258                                   &gfx3d1 13
1259                                   &gfx3d1 14
1260                                   &gfx3d1 15
1261                                   &gfx3d1 16
1262                                   &gfx3d1 17
1263                                   &gfx3d1 18
1264                                   &gfx3d1 19
1265                                   &gfx3d1 20
1266                                   &gfx3d1 21
1267                                   &gfx3d1 22
1268                                   &gfx3d1 23
1269                                   &gfx3d1 24
1270                                   &gfx3d1 25
1271                                   &gfx3d1 26
1272                                   &gfx3d1 27
1273                                   &gfx3d1 28
1274                                   &gfx3d1 29
1275                                   &gfx3d1 30
1276                                   &gfx3d1 31>;
1277
1278                         operating-points-v2 = <&gpu_opp_table>;
1279
1280                         gpu_opp_table: opp-table {
1281                                 compatible = "operating-points-v2";
1282
1283                                 opp-450000000 {
1284                                         opp-hz = /bits/ 64 <450000000>;
1285                                 };
1286
1287                                 opp-27000000 {
1288                                         opp-hz = /bits/ 64 <27000000>;
1289                                 };
1290                         };
1291                 };
1292
1293                 mmss_sfpb: syscon@5700000 {
1294                         compatible = "syscon";
1295                         reg = <0x5700000 0x70>;
1296                 };
1297
1298                 dsi0: dsi@4700000 {
1299                         compatible = "qcom,apq8064-dsi-ctrl",
1300                                      "qcom,mdss-dsi-ctrl";
1301                         label = "MDSS DSI CTRL->0";
1302                         #address-cells = <1>;
1303                         #size-cells = <0>;
1304                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1305                         reg = <0x04700000 0x200>;
1306                         reg-names = "dsi_ctrl";
1307
1308                         clocks = <&mmcc DSI_M_AHB_CLK>,
1309                                 <&mmcc DSI_S_AHB_CLK>,
1310                                 <&mmcc AMP_AHB_CLK>,
1311                                 <&mmcc DSI_CLK>,
1312                                 <&mmcc DSI1_BYTE_CLK>,
1313                                 <&mmcc DSI_PIXEL_CLK>,
1314                                 <&mmcc DSI1_ESC_CLK>;
1315                         clock-names = "iface", "bus", "core_mmss",
1316                                         "src", "byte", "pixel",
1317                                         "core";
1318
1319                         assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1320                                         <&mmcc DSI1_ESC_SRC>,
1321                                         <&mmcc DSI_SRC>,
1322                                         <&mmcc DSI_PIXEL_SRC>;
1323                         assigned-clock-parents = <&dsi0_phy 0>,
1324                                                 <&dsi0_phy 0>,
1325                                                 <&dsi0_phy 1>,
1326                                                 <&dsi0_phy 1>;
1327                         syscon-sfpb = <&mmss_sfpb>;
1328                         phys = <&dsi0_phy>;
1329                         status = "disabled";
1330
1331                         ports {
1332                                 #address-cells = <1>;
1333                                 #size-cells = <0>;
1334
1335                                 port@0 {
1336                                         reg = <0>;
1337                                         dsi0_in: endpoint {
1338                                         };
1339                                 };
1340
1341                                 port@1 {
1342                                         reg = <1>;
1343                                         dsi0_out: endpoint {
1344                                         };
1345                                 };
1346                         };
1347                 };
1348
1349
1350                 dsi0_phy: phy@4700200 {
1351                         compatible = "qcom,dsi-phy-28nm-8960";
1352                         #clock-cells = <1>;
1353                         #phy-cells = <0>;
1354
1355                         reg = <0x04700200 0x100>,
1356                                 <0x04700300 0x200>,
1357                                 <0x04700500 0x5c>;
1358                         reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1359                         clock-names = "iface", "ref";
1360                         clocks = <&mmcc DSI_M_AHB_CLK>,
1361                                  <&pxo_board>;
1362                         status = "disabled";
1363                 };
1364
1365                 dsi1: dsi@5800000 {
1366                         compatible = "qcom,mdss-dsi-ctrl";
1367                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1368                         reg = <0x05800000 0x200>;
1369                         reg-names = "dsi_ctrl";
1370
1371                         clocks = <&mmcc DSI2_M_AHB_CLK>,
1372                                  <&mmcc DSI2_S_AHB_CLK>,
1373                                  <&mmcc AMP_AHB_CLK>,
1374                                  <&mmcc DSI2_CLK>,
1375                                  <&mmcc DSI2_BYTE_CLK>,
1376                                  <&mmcc DSI2_PIXEL_CLK>,
1377                                  <&mmcc DSI2_ESC_CLK>;
1378                         clock-names = "iface",
1379                                       "bus",
1380                                       "core_mmss",
1381                                       "src",
1382                                       "byte",
1383                                       "pixel",
1384                                       "core";
1385
1386                         assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1387                                           <&mmcc DSI2_ESC_SRC>,
1388                                           <&mmcc DSI2_SRC>,
1389                                           <&mmcc DSI2_PIXEL_SRC>;
1390                         assigned-clock-parents = <&dsi1_phy 0>,
1391                                                  <&dsi1_phy 0>,
1392                                                  <&dsi1_phy 1>,
1393                                                  <&dsi1_phy 1>;
1394
1395                         syscon-sfpb = <&mmss_sfpb>;
1396                         phys = <&dsi1_phy>;
1397
1398                         #address-cells = <1>;
1399                         #size-cells = <0>;
1400
1401                         status = "disabled";
1402
1403                         ports {
1404                                 #address-cells = <1>;
1405                                 #size-cells = <0>;
1406
1407                                 port@0 {
1408                                         reg = <0>;
1409                                         dsi1_in: endpoint {
1410                                         };
1411                                 };
1412
1413                                 port@1 {
1414                                         reg = <1>;
1415                                         dsi1_out: endpoint {
1416                                         };
1417                                 };
1418                         };
1419                 };
1420
1421
1422                 dsi1_phy: dsi-phy@5800200 {
1423                         compatible = "qcom,dsi-phy-28nm-8960";
1424                         reg = <0x05800200 0x100>,
1425                               <0x05800300 0x200>,
1426                               <0x05800500 0x5c>;
1427                         reg-names = "dsi_pll",
1428                                     "dsi_phy",
1429                                     "dsi_phy_regulator";
1430                         clock-names = "iface",
1431                                       "ref";
1432                         clocks = <&mmcc DSI2_M_AHB_CLK>,
1433                                  <&pxo_board>;
1434                         #clock-cells = <1>;
1435                         #phy-cells = <0>;
1436
1437                         status = "disabled";
1438                 };
1439
1440                 mdp_port0: iommu@7500000 {
1441                         compatible = "qcom,apq8064-iommu";
1442                         #iommu-cells = <1>;
1443                         clock-names =
1444                             "smmu_pclk",
1445                             "iommu_clk";
1446                         clocks =
1447                             <&mmcc SMMU_AHB_CLK>,
1448                             <&mmcc MDP_AXI_CLK>;
1449                         reg = <0x07500000 0x100000>;
1450                         interrupts =
1451                             <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1452                             <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1453                         qcom,ncb = <2>;
1454                 };
1455
1456                 mdp_port1: iommu@7600000 {
1457                         compatible = "qcom,apq8064-iommu";
1458                         #iommu-cells = <1>;
1459                         clock-names =
1460                             "smmu_pclk",
1461                             "iommu_clk";
1462                         clocks =
1463                             <&mmcc SMMU_AHB_CLK>,
1464                             <&mmcc MDP_AXI_CLK>;
1465                         reg = <0x07600000 0x100000>;
1466                         interrupts =
1467                             <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1468                             <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1469                         qcom,ncb = <2>;
1470                 };
1471
1472                 gfx3d: iommu@7c00000 {
1473                         compatible = "qcom,apq8064-iommu";
1474                         #iommu-cells = <1>;
1475                         clock-names =
1476                             "smmu_pclk",
1477                             "iommu_clk";
1478                         clocks =
1479                             <&mmcc SMMU_AHB_CLK>,
1480                             <&mmcc GFX3D_AXI_CLK>;
1481                         reg = <0x07c00000 0x100000>;
1482                         interrupts =
1483                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1484                             <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1485                         qcom,ncb = <3>;
1486                 };
1487
1488                 gfx3d1: iommu@7d00000 {
1489                         compatible = "qcom,apq8064-iommu";
1490                         #iommu-cells = <1>;
1491                         clock-names =
1492                             "smmu_pclk",
1493                             "iommu_clk";
1494                         clocks =
1495                             <&mmcc SMMU_AHB_CLK>,
1496                             <&mmcc GFX3D_AXI_CLK>;
1497                         reg = <0x07d00000 0x100000>;
1498                         interrupts =
1499                             <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1500                             <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1501                         qcom,ncb = <3>;
1502                 };
1503
1504                 pcie: pci@1b500000 {
1505                         compatible = "qcom,pcie-apq8064";
1506                         reg = <0x1b500000 0x1000>,
1507                               <0x1b502000 0x80>,
1508                               <0x1b600000 0x100>,
1509                               <0x0ff00000 0x100000>;
1510                         reg-names = "dbi", "elbi", "parf", "config";
1511                         device_type = "pci";
1512                         linux,pci-domain = <0>;
1513                         bus-range = <0x00 0xff>;
1514                         num-lanes = <1>;
1515                         #address-cells = <3>;
1516                         #size-cells = <2>;
1517                         ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1518                                  <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1519                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1520                         interrupt-names = "msi";
1521                         #interrupt-cells = <1>;
1522                         interrupt-map-mask = <0 0 0 0x7>;
1523                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1524                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1525                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1526                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1527                         clocks = <&gcc PCIE_A_CLK>,
1528                                  <&gcc PCIE_H_CLK>,
1529                                  <&gcc PCIE_PHY_REF_CLK>;
1530                         clock-names = "core", "iface", "phy";
1531                         resets = <&gcc PCIE_ACLK_RESET>,
1532                                  <&gcc PCIE_HCLK_RESET>,
1533                                  <&gcc PCIE_POR_RESET>,
1534                                  <&gcc PCIE_PCI_RESET>,
1535                                  <&gcc PCIE_PHY_RESET>;
1536                         reset-names = "axi", "ahb", "por", "pci", "phy";
1537                         status = "disabled";
1538                 };
1539
1540                 hdmi: hdmi-tx@4a00000 {
1541                         compatible = "qcom,hdmi-tx-8960";
1542                         pinctrl-names = "default";
1543                         pinctrl-0 = <&hdmi_pinctrl>;
1544                         reg = <0x04a00000 0x2f0>;
1545                         reg-names = "core_physical";
1546                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1547                         clocks = <&mmcc HDMI_APP_CLK>,
1548                                  <&mmcc HDMI_M_AHB_CLK>,
1549                                  <&mmcc HDMI_S_AHB_CLK>;
1550                         clock-names = "core",
1551                                       "master_iface",
1552                                       "slave_iface";
1553
1554                         phys = <&hdmi_phy>;
1555
1556                         status = "disabled";
1557
1558                         ports {
1559                                 #address-cells = <1>;
1560                                 #size-cells = <0>;
1561
1562                                 port@0 {
1563                                         reg = <0>;
1564                                         hdmi_in: endpoint {
1565                                         };
1566                                 };
1567
1568                                 port@1 {
1569                                         reg = <1>;
1570                                         hdmi_out: endpoint {
1571                                         };
1572                                 };
1573                         };
1574                 };
1575
1576                 hdmi_phy: phy@4a00400 {
1577                         compatible = "qcom,hdmi-phy-8960";
1578                         reg = <0x4a00400 0x60>,
1579                               <0x4a00500 0x100>;
1580                         reg-names = "hdmi_phy",
1581                                     "hdmi_pll";
1582
1583                         clocks = <&mmcc HDMI_S_AHB_CLK>;
1584                         clock-names = "slave_iface";
1585                         #phy-cells = <0>;
1586                         #clock-cells = <0>;
1587
1588                         status = "disabled";
1589                 };
1590
1591                 mdp: display-controller@5100000 {
1592                         compatible = "qcom,mdp4";
1593                         reg = <0x05100000 0xf0000>;
1594                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1595                         clocks = <&mmcc MDP_CLK>,
1596                                  <&mmcc MDP_AHB_CLK>,
1597                                  <&mmcc MDP_AXI_CLK>,
1598                                  <&mmcc MDP_LUT_CLK>,
1599                                  <&mmcc HDMI_TV_CLK>,
1600                                  <&mmcc MDP_TV_CLK>;
1601                         clock-names = "core_clk",
1602                                       "iface_clk",
1603                                       "bus_clk",
1604                                       "lut_clk",
1605                                       "hdmi_clk",
1606                                       "tv_clk";
1607
1608                         iommus = <&mdp_port0 0
1609                                   &mdp_port0 2
1610                                   &mdp_port1 0
1611                                   &mdp_port1 2>;
1612
1613                         ports {
1614                                 #address-cells = <1>;
1615                                 #size-cells = <0>;
1616
1617                                 port@0 {
1618                                         reg = <0>;
1619                                         mdp_lvds_out: endpoint {
1620                                         };
1621                                 };
1622
1623                                 port@1 {
1624                                         reg = <1>;
1625                                         mdp_dsi1_out: endpoint {
1626                                         };
1627                                 };
1628
1629                                 port@2 {
1630                                         reg = <2>;
1631                                         mdp_dsi2_out: endpoint {
1632                                         };
1633                                 };
1634
1635                                 port@3 {
1636                                         reg = <3>;
1637                                         mdp_dtv_out: endpoint {
1638                                         };
1639                                 };
1640                         };
1641                 };
1642
1643                 riva: riva-pil@3200800 {
1644                         compatible = "qcom,riva-pil";
1645
1646                         reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1647                         reg-names = "ccu", "dxe", "pmu";
1648
1649                         interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1650                                               <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1651                         interrupt-names = "wdog", "fatal";
1652
1653                         memory-region = <&wcnss_mem>;
1654
1655                         vddcx-supply = <&pm8921_s3>;
1656                         vddmx-supply = <&pm8921_l24>;
1657                         vddpx-supply = <&pm8921_s4>;
1658
1659                         status = "disabled";
1660
1661                         iris {
1662                                 compatible = "qcom,wcn3660";
1663
1664                                 clocks = <&cxo_board>;
1665                                 clock-names = "xo";
1666
1667                                 vddxo-supply = <&pm8921_l4>;
1668                                 vddrfa-supply = <&pm8921_s2>;
1669                                 vddpa-supply = <&pm8921_l10>;
1670                                 vdddig-supply = <&pm8921_lvs2>;
1671                         };
1672
1673                         smd-edge {
1674                                 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1675
1676                                 qcom,ipc = <&l2cc 8 25>;
1677                                 qcom,smd-edge = <6>;
1678
1679                                 label = "riva";
1680
1681                                 wcnss {
1682                                         compatible = "qcom,wcnss";
1683                                         qcom,smd-channels = "WCNSS_CTRL";
1684
1685                                         qcom,mmio = <&riva>;
1686
1687                                         bluetooth {
1688                                                 compatible = "qcom,wcnss-bt";
1689                                         };
1690
1691                                         wifi {
1692                                                 compatible = "qcom,wcnss-wlan";
1693
1694                                                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1695                                                              <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1696                                                 interrupt-names = "tx", "rx";
1697
1698                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1699                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1700                                         };
1701                                 };
1702                         };
1703                 };
1704
1705                 etb@1a01000 {
1706                         compatible = "arm,coresight-etb10", "arm,primecell";
1707                         reg = <0x1a01000 0x1000>;
1708
1709                         clocks = <&rpmcc RPM_QDSS_CLK>;
1710                         clock-names = "apb_pclk";
1711
1712                         in-ports {
1713                                 port {
1714                                         etb_in: endpoint {
1715                                                 remote-endpoint = <&replicator_out0>;
1716                                         };
1717                                 };
1718                         };
1719                 };
1720
1721                 tpiu@1a03000 {
1722                         compatible = "arm,coresight-tpiu", "arm,primecell";
1723                         reg = <0x1a03000 0x1000>;
1724
1725                         clocks = <&rpmcc RPM_QDSS_CLK>;
1726                         clock-names = "apb_pclk";
1727
1728                         in-ports {
1729                                 port {
1730                                         tpiu_in: endpoint {
1731                                                 remote-endpoint = <&replicator_out1>;
1732                                         };
1733                                 };
1734                         };
1735                 };
1736
1737                 replicator {
1738                         compatible = "arm,coresight-static-replicator";
1739
1740                         clocks = <&rpmcc RPM_QDSS_CLK>;
1741                         clock-names = "apb_pclk";
1742
1743                         out-ports {
1744                                 #address-cells = <1>;
1745                                 #size-cells = <0>;
1746
1747                                 port@0 {
1748                                         reg = <0>;
1749                                         replicator_out0: endpoint {
1750                                                 remote-endpoint = <&etb_in>;
1751                                         };
1752                                 };
1753                                 port@1 {
1754                                         reg = <1>;
1755                                         replicator_out1: endpoint {
1756                                                 remote-endpoint = <&tpiu_in>;
1757                                         };
1758                                 };
1759                         };
1760
1761                         in-ports {
1762                                 port {
1763                                         replicator_in: endpoint {
1764                                                 remote-endpoint = <&funnel_out>;
1765                                         };
1766                                 };
1767                         };
1768                 };
1769
1770                 funnel@1a04000 {
1771                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1772                         reg = <0x1a04000 0x1000>;
1773
1774                         clocks = <&rpmcc RPM_QDSS_CLK>;
1775                         clock-names = "apb_pclk";
1776
1777                         in-ports {
1778                                 #address-cells = <1>;
1779                                 #size-cells = <0>;
1780
1781                                 /*
1782                                  * Not described input ports:
1783                                  * 2 - connected to STM component
1784                                  * 3 - not-connected
1785                                  * 6 - not-connected
1786                                  * 7 - not-connected
1787                                  */
1788                                 port@0 {
1789                                         reg = <0>;
1790                                         funnel_in0: endpoint {
1791                                                 remote-endpoint = <&etm0_out>;
1792                                         };
1793                                 };
1794                                 port@1 {
1795                                         reg = <1>;
1796                                         funnel_in1: endpoint {
1797                                                 remote-endpoint = <&etm1_out>;
1798                                         };
1799                                 };
1800                                 port@4 {
1801                                         reg = <4>;
1802                                         funnel_in4: endpoint {
1803                                                 remote-endpoint = <&etm2_out>;
1804                                         };
1805                                 };
1806                                 port@5 {
1807                                         reg = <5>;
1808                                         funnel_in5: endpoint {
1809                                                 remote-endpoint = <&etm3_out>;
1810                                         };
1811                                 };
1812                         };
1813
1814                         out-ports {
1815                                 port {
1816                                         funnel_out: endpoint {
1817                                                 remote-endpoint = <&replicator_in>;
1818                                         };
1819                                 };
1820                         };
1821                 };
1822
1823                 etm@1a1c000 {
1824                         compatible = "arm,coresight-etm3x", "arm,primecell";
1825                         reg = <0x1a1c000 0x1000>;
1826
1827                         clocks = <&rpmcc RPM_QDSS_CLK>;
1828                         clock-names = "apb_pclk";
1829
1830                         cpu = <&CPU0>;
1831
1832                         out-ports {
1833                                 port {
1834                                         etm0_out: endpoint {
1835                                                 remote-endpoint = <&funnel_in0>;
1836                                         };
1837                                 };
1838                         };
1839                 };
1840
1841                 etm@1a1d000 {
1842                         compatible = "arm,coresight-etm3x", "arm,primecell";
1843                         reg = <0x1a1d000 0x1000>;
1844
1845                         clocks = <&rpmcc RPM_QDSS_CLK>;
1846                         clock-names = "apb_pclk";
1847
1848                         cpu = <&CPU1>;
1849
1850                         out-ports {
1851                                 port {
1852                                         etm1_out: endpoint {
1853                                                 remote-endpoint = <&funnel_in1>;
1854                                         };
1855                                 };
1856                         };
1857                 };
1858
1859                 etm@1a1e000 {
1860                         compatible = "arm,coresight-etm3x", "arm,primecell";
1861                         reg = <0x1a1e000 0x1000>;
1862
1863                         clocks = <&rpmcc RPM_QDSS_CLK>;
1864                         clock-names = "apb_pclk";
1865
1866                         cpu = <&CPU2>;
1867
1868                         out-ports {
1869                                 port {
1870                                         etm2_out: endpoint {
1871                                                 remote-endpoint = <&funnel_in4>;
1872                                         };
1873                                 };
1874                         };
1875                 };
1876
1877                 etm@1a1f000 {
1878                         compatible = "arm,coresight-etm3x", "arm,primecell";
1879                         reg = <0x1a1f000 0x1000>;
1880
1881                         clocks = <&rpmcc RPM_QDSS_CLK>;
1882                         clock-names = "apb_pclk";
1883
1884                         cpu = <&CPU3>;
1885
1886                         out-ports {
1887                                 port {
1888                                         etm3_out: endpoint {
1889                                                 remote-endpoint = <&funnel_in5>;
1890                                         };
1891                                 };
1892                         };
1893                 };
1894         };
1895 };
1896 #include "qcom-apq8064-pins.dtsi"