arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts

   1 // redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=26,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=16
   2
   3 // Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm
   4 // in "Mode A" (default) configuration
   5 // for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT
   6
   7 /dts-v1/;
   8 /plugin/;
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/pinctrl/bcm2835.h>
  13
  14 / {
  15         compatible = "brcm,bcm2835";
  16         fragment@0 {
  17                 target = <&gpio>;
  18                 __overlay__ {
  19                         spi1_pins: spi1_pins {
  20                                 brcm,pins = <19 20 21>;
  21                                 brcm,function = <3>;
  22                         };
  23                         spi1_cs_pins: spi1_cs_pins {
  24                                 brcm,pins = <26>;
  25                                 brcm,function = <1>;
  26                         };
  27                 };
  28         };
  29         fragment@1 {
  30                 target = <&spi1>;
  31                 __overlay__ {
  32                         #address-cells = <1>;
  33                         #size-cells = <0>;
  34                         pinctrl-names = "default";
  35                         pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
  36                         cs-gpios = <&gpio 26 1>;
  37                         status = "okay";
  38                         spidev@0 {
  39                                 compatible = "spidev";
  40                                 reg = <0>;
  41                                 #address-cells = <1>;
  42                                 #size-cells = <0>;
  43                                 spi-max-frequency = <125000000>;
  44                                 status = "disabled";
  45                         };
  46                 };
  47         };
  48         fragment@2 {
  49                 target = <&aux>;
  50                 __overlay__ {
  51                         status = "okay";
  52                 };
  53         };
  54         fragment@3 {
  55                 target = <&spidev0>;
  56                 __overlay__ {
  57                         status = "disabled";
  58                 };
  59         };
  60         fragment@4 {
  61                 target = <&gpio>;
  62                 __overlay__ {
  63                         mcp251xfd_pins: mcp251xfd_spi0_0_pins {
  64                                 brcm,pins = <25>;
  65                                 brcm,function = <BCM2835_FSEL_GPIO_IN>;
  66                         };
  67                 };
  68         };
  69         fragment@5 {
  70                 target-path = "/clocks";
  71                 __overlay__ {
  72                         clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {
  73                                 #clock-cells = <0>;
  74                                 compatible = "fixed-clock";
  75                                 clock-frequency = <40000000>;
  76                         };
  77                 };
  78         };
  79         fragment@6 {
  80                 target = <&spi0>;
  81                 __overlay__ {
  82                         status = "okay";
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85                         mcp251xfd@0 {
  86                                 compatible = "microchip,mcp251xfd";
  87                                 reg = <0>;
  88                                 pinctrl-names = "default";
  89                                 pinctrl-0 = <&mcp251xfd_pins>;
  90                                 spi-max-frequency = <20000000>;
  91                                 interrupt-parent = <&gpio>;
  92                                 interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
  93                                 clocks = <&clk_mcp251xfd_osc>;
  94                         };
  95                 };
  96         };
  97         fragment@7 {
  98                 target-path = "spi1/spidev@0";
  99                 __overlay__ {
 100                         status = "disabled";
 101                 };
 102         };
 103         fragment@8 {
 104                 target = <&gpio>;
 105                 __overlay__ {
 106                         mcp251xfd_pins_1: mcp251xfd_spi1_0_pins {
 107                                 brcm,pins = <16>;
 108                                 brcm,function = <BCM2835_FSEL_GPIO_IN>;
 109                         };
 110                 };
 111         };
 112         fragment@9 {
 113                 target-path = "/clocks";
 114                 __overlay__ {
 115                         clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc {
 116                                 #clock-cells = <0>;
 117                                 compatible = "fixed-clock";
 118                                 clock-frequency = <40000000>;
 119                         };
 120                 };
 121         };
 122         fragment@10 {
 123                 target = <&spi1>;
 124                 __overlay__ {
 125                         status = "okay";
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         mcp251xfd@0 {
 129                                 compatible = "microchip,mcp251xfd";
 130                                 reg = <0>;
 131                                 pinctrl-names = "default";
 132                                 pinctrl-0 = <&mcp251xfd_pins_1>;
 133                                 spi-max-frequency = <20000000>;
 134                                 interrupt-parent = <&gpio>;
 135                                 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 136                                 clocks = <&clk_mcp251xfd_osc_1>;
 137                         };
 138                 };
 139         };
 140 };