1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on "omap4.dtsi"
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
42 compatible = "arm,cortex-a15";
51 clocks = <&dpll_mpu_ck>;
54 clock-latency = <300000>; /* From omap-cpufreq driver */
57 #cooling-cells = <2>; /* min followed by max */
61 compatible = "arm,cortex-a15";
70 clocks = <&dpll_mpu_ck>;
73 clock-latency = <300000>; /* From omap-cpufreq driver */
76 #cooling-cells = <2>; /* min followed by max */
81 #include "omap4-cpu-thermal.dtsi"
82 #include "omap5-gpu-thermal.dtsi"
83 #include "omap5-core-thermal.dtsi"
87 compatible = "arm,armv7-timer";
88 /* PPI secure/nonsecure IRQ */
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
93 interrupt-parent = <&gic>;
97 compatible = "arm,cortex-a15-pmu";
98 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
102 gic: interrupt-controller@48211000 {
103 compatible = "arm,cortex-a15-gic";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0 0x48211000 0 0x1000>,
107 <0 0x48212000 0 0x2000>,
108 <0 0x48214000 0 0x2000>,
109 <0 0x48216000 0 0x2000>;
110 interrupt-parent = <&gic>;
113 wakeupgen: interrupt-controller@48281000 {
114 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
115 interrupt-controller;
116 #interrupt-cells = <3>;
117 reg = <0 0x48281000 0 0x1000>;
118 interrupt-parent = <&gic>;
122 * The soc node represents the soc top level view. It is used for IPs
123 * that are not memory mapped in the MPU view or for the MPU itself.
126 compatible = "ti,omap-infra";
128 compatible = "ti,omap4-mpu";
135 * XXX: Use a flat representation of the OMAP3 interconnect.
136 * The real OMAP interconnect network is quite complex.
137 * Since it will not bring real advantage to represent that in DT for
138 * the moment, just use a fake OCP bus entry to represent the whole bus
142 compatible = "ti,omap5-l3-noc", "simple-bus";
143 #address-cells = <1>;
145 ranges = <0 0 0 0xc0000000>;
146 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
147 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
148 reg = <0 0x44000000 0 0x2000>,
149 <0 0x44800000 0 0x3000>,
150 <0 0x45000000 0 0x4000>;
151 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
154 l4_wkup: interconnect@4ae00000 {
157 l4_cfg: interconnect@4a000000 {
160 l4_per: interconnect@48000000 {
163 l4_abe: interconnect@40100000 {
166 ocmcram: sram@40300000 {
167 compatible = "mmio-sram";
168 reg = <0x40300000 0x20000>; /* 128k */
171 gpmc: gpmc@50000000 {
172 compatible = "ti,omap4430-gpmc";
173 reg = <0x50000000 0x1000>;
174 #address-cells = <2>;
176 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
180 gpmc,num-waitpins = <4>;
182 clocks = <&l3_iclk_div>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
190 target-module@55082000 {
191 compatible = "ti,sysc-omap2", "ti,sysc";
192 reg = <0x55082000 0x4>,
195 reg-names = "rev", "sysc", "syss";
196 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
199 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
200 SYSC_OMAP2_SOFTRESET |
201 SYSC_OMAP2_AUTOIDLE)>;
202 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
204 resets = <&prm_core 2>;
205 reset-names = "rstctrl";
206 ranges = <0x0 0x55082000 0x100>;
208 #address-cells = <1>;
211 compatible = "ti,omap4-iommu";
213 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
215 ti,iommu-bus-err-back;
220 compatible = "ti,omap5-dmm";
221 reg = <0x4e000000 0x800>;
222 interrupts = <0 113 0x4>;
226 emif1: emif@4c000000 {
227 compatible = "ti,emif-4d5";
230 phy-type = <2>; /* DDR PHY type: Intelli PHY */
231 reg = <0x4c000000 0x400>;
232 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
233 hw-caps-read-idle-ctrl;
234 hw-caps-ll-interface;
238 emif2: emif@4d000000 {
239 compatible = "ti,emif-4d5";
242 phy-type = <2>; /* DDR PHY type: Intelli PHY */
243 reg = <0x4d000000 0x400>;
244 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
245 hw-caps-read-idle-ctrl;
246 hw-caps-ll-interface;
250 aes1_target: target-module@4b501000 {
251 compatible = "ti,sysc-omap2", "ti,sysc";
252 reg = <0x4b501080 0x4>,
255 reg-names = "rev", "sysc", "syss";
256 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
257 SYSC_OMAP2_AUTOIDLE)>;
258 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
261 <SYSC_IDLE_SMART_WKUP>;
263 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
264 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
266 #address-cells = <1>;
268 ranges = <0x0 0x4b501000 0x1000>;
271 compatible = "ti,omap4-aes";
273 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
274 dmas = <&sdma 111>, <&sdma 110>;
275 dma-names = "tx", "rx";
279 aes2_target: target-module@4b701000 {
280 compatible = "ti,sysc-omap2", "ti,sysc";
281 reg = <0x4b701080 0x4>,
284 reg-names = "rev", "sysc", "syss";
285 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
286 SYSC_OMAP2_AUTOIDLE)>;
287 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
290 <SYSC_IDLE_SMART_WKUP>;
292 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
293 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
295 #address-cells = <1>;
297 ranges = <0x0 0x4b701000 0x1000>;
300 compatible = "ti,omap4-aes";
302 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
303 dmas = <&sdma 114>, <&sdma 113>;
304 dma-names = "tx", "rx";
308 sham_target: target-module@4b100000 {
309 compatible = "ti,sysc-omap3-sham", "ti,sysc";
310 reg = <0x4b100100 0x4>,
313 reg-names = "rev", "sysc", "syss";
314 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
315 SYSC_OMAP2_AUTOIDLE)>;
316 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
320 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
321 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
323 #address-cells = <1>;
325 ranges = <0x0 0x4b100000 0x1000>;
328 compatible = "ti,omap4-sham";
330 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
336 bandgap: bandgap@4a0021e0 {
337 reg = <0x4a0021e0 0xc
341 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
342 compatible = "ti,omap5430-bandgap";
344 #thermal-sensor-cells = <1>;
348 sata: sata@4a141100 {
349 compatible = "snps,dwc-ahci";
350 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
351 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
353 phy-names = "sata-phy";
354 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
356 ports-implemented = <0x1>;
359 target-module@56000000 {
360 compatible = "ti,sysc-omap4", "ti,sysc";
361 reg = <0x5600fe00 0x4>,
363 reg-names = "rev", "sysc";
364 ti,sysc-midle = <SYSC_IDLE_FORCE>,
367 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
370 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
372 #address-cells = <1>;
374 ranges = <0 0x56000000 0x2000000>;
377 * Closed source PowerVR driver, no child device
378 * binding or driver in mainline
382 target-module@58000000 {
383 compatible = "ti,sysc-omap2", "ti,sysc";
384 reg = <0x58000000 4>,
386 reg-names = "rev", "syss";
388 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
389 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
390 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
391 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
392 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
393 #address-cells = <1>;
395 ranges = <0 0x58000000 0x1000000>;
398 compatible = "ti,omap5-dss";
401 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
403 #address-cells = <1>;
405 ranges = <0 0 0x1000000>;
408 compatible = "ti,sysc-omap2", "ti,sysc";
412 reg-names = "rev", "sysc", "syss";
413 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
416 ti,sysc-midle = <SYSC_IDLE_FORCE>,
419 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
420 SYSC_OMAP2_ENAWAKEUP |
421 SYSC_OMAP2_SOFTRESET |
422 SYSC_OMAP2_AUTOIDLE)>;
424 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
426 #address-cells = <1>;
428 ranges = <0 0x1000 0x1000>;
431 compatible = "ti,omap5-dispc";
433 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
440 compatible = "ti,sysc-omap2", "ti,sysc";
444 reg-names = "rev", "sysc", "syss";
445 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
448 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
449 SYSC_OMAP2_AUTOIDLE)>;
451 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
453 #address-cells = <1>;
455 ranges = <0 0x2000 0x1000>;
458 compatible = "ti,omap5-rfbi";
461 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
462 clock-names = "fck", "ick";
467 compatible = "ti,sysc-omap2", "ti,sysc";
471 reg-names = "rev", "sysc", "syss";
472 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
475 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
476 SYSC_OMAP2_ENAWAKEUP |
477 SYSC_OMAP2_SOFTRESET |
478 SYSC_OMAP2_AUTOIDLE)>;
480 #address-cells = <1>;
482 ranges = <0 0x5000 0x1000>;
485 compatible = "ti,omap5-dsi";
489 reg-names = "proto", "phy", "pll";
490 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
498 compatible = "ti,sysc-omap2", "ti,sysc";
502 reg-names = "rev", "sysc", "syss";
503 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
506 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
507 SYSC_OMAP2_ENAWAKEUP |
508 SYSC_OMAP2_SOFTRESET |
509 SYSC_OMAP2_AUTOIDLE)>;
511 #address-cells = <1>;
513 ranges = <0 0x9000 0x1000>;
516 compatible = "ti,omap5-dsi";
520 reg-names = "proto", "phy", "pll";
521 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
528 target-module@40000 {
529 compatible = "ti,sysc-omap4", "ti,sysc";
532 reg-names = "rev", "sysc";
533 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
536 <SYSC_IDLE_SMART_WKUP>;
537 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
538 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
539 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
540 clock-names = "fck", "dss_clk";
541 #address-cells = <1>;
543 ranges = <0 0x40000 0x40000>;
546 compatible = "ti,omap5-hdmi";
551 reg-names = "wp", "pll", "phy", "core";
552 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
555 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
556 clock-names = "fck", "sys_clk";
558 dma-names = "audio_tx";
564 abb_mpu: regulator-abb-mpu {
565 compatible = "ti,abb-v2";
566 regulator-name = "abb_mpu";
567 #address-cells = <0>;
569 clocks = <&sys_clkin>;
570 ti,settling-time = <50>;
571 ti,clock-cycles = <16>;
573 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
574 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
575 reg-names = "base-address", "int-address",
576 "efuse-address", "ldo-address";
577 ti,tranxdone-status-mask = <0x80>;
578 /* LDOVBBMPU_MUX_CTRL */
579 ti,ldovbb-override-mask = <0x400>;
580 /* LDOVBBMPU_VSET_OUT */
581 ti,ldovbb-vset-mask = <0x1F>;
584 * NOTE: only FBB mode used but actual vset will
585 * determine final biasing
588 /*uV ABB efuse rbb_m fbb_m vset_m*/
589 1060000 0 0x0 0 0x02000000 0x01F00000
590 1250000 0 0x4 0 0x02000000 0x01F00000
594 abb_mm: regulator-abb-mm {
595 compatible = "ti,abb-v2";
596 regulator-name = "abb_mm";
597 #address-cells = <0>;
599 clocks = <&sys_clkin>;
600 ti,settling-time = <50>;
601 ti,clock-cycles = <16>;
603 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
604 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
605 reg-names = "base-address", "int-address",
606 "efuse-address", "ldo-address";
607 ti,tranxdone-status-mask = <0x80000000>;
608 /* LDOVBBMM_MUX_CTRL */
609 ti,ldovbb-override-mask = <0x400>;
610 /* LDOVBBMM_VSET_OUT */
611 ti,ldovbb-vset-mask = <0x1F>;
614 * NOTE: only FBB mode used but actual vset will
615 * determine final biasing
618 /*uV ABB efuse rbb_m fbb_m vset_m*/
619 1025000 0 0x0 0 0x02000000 0x01F00000
620 1120000 0 0x4 0 0x02000000 0x01F00000
627 polling-delay = <500>; /* milliseconds */
628 coefficients = <65 (-1791)>;
631 #include "omap5-l4.dtsi"
632 #include "omap54xx-clocks.dtsi"
635 coefficients = <117 (-2992)>;
639 coefficients = <0 2000>;
642 #include "omap5-l4-abe.dtsi"
643 #include "omap54xx-clocks.dtsi"
647 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
653 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
659 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
660 reg = <0x1200 0x100>;
664 prm_device: prm@1c00 {
665 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
666 reg = <0x1c00 0x100>;
671 /* Preferred always-on timer for clockevent */
676 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
677 assigned-clock-parents = <&sys_32k_ck>;