arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 500000  880000
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52                         /* cooling options */
  53                         cooling-min-level = <0>;
  54                         cooling-max-level = <2>;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                 };
  57                 cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x1>;
  61                 };
  62         };
  63
  64         thermal-zones {
  65                 #include "omap4-cpu-thermal.dtsi"
  66                 #include "omap5-gpu-thermal.dtsi"
  67                 #include "omap5-core-thermal.dtsi"
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 /* PPI secure/nonsecure IRQ */
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  77         };
  78
  79         gic: interrupt-controller@48211000 {
  80                 compatible = "arm,cortex-a15-gic";
  81                 interrupt-controller;
  82                 #interrupt-cells = <3>;
  83                 reg = <0x48211000 0x1000>,
  84                       <0x48212000 0x1000>,
  85                       <0x48214000 0x2000>,
  86                       <0x48216000 0x2000>;
  87         };
  88
  89         /*
  90          * The soc node represents the soc top level view. It is uses for IPs
  91          * that are not memory mapped in the MPU view or for the MPU itself.
  92          */
  93         soc {
  94                 compatible = "ti,omap-infra";
  95                 mpu {
  96                         compatible = "ti,omap5-mpu";
  97                         ti,hwmods = "mpu";
  98                 };
  99         };
 100
 101         /*
 102          * XXX: Use a flat representation of the OMAP3 interconnect.
 103          * The real OMAP interconnect network is quite complex.
 104          * Since that will not bring real advantage to represent that in DT for
 105          * the moment, just use a fake OCP bus entry to represent the whole bus
 106          * hierarchy.
 107          */
 108         ocp {
 109                 compatible = "ti,omap4-l3-noc", "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges;
 113                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 114                 reg = <0x44000000 0x2000>,
 115                       <0x44800000 0x3000>,
 116                       <0x45000000 0x4000>;
 117                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 119
 120                 prm: prm@4ae06000 {
 121                         compatible = "ti,omap5-prm";
 122                         reg = <0x4ae06000 0x3000>;
 123
 124                         prm_clocks: clocks {
 125                                 #address-cells = <1>;
 126                                 #size-cells = <0>;
 127                         };
 128
 129                         prm_clockdomains: clockdomains {
 130                         };
 131                 };
 132
 133                 cm_core_aon: cm_core_aon@4a004000 {
 134                         compatible = "ti,omap5-cm-core-aon";
 135                         reg = <0x4a004000 0x2000>;
 136
 137                         cm_core_aon_clocks: clocks {
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140                         };
 141
 142                         cm_core_aon_clockdomains: clockdomains {
 143                         };
 144                 };
 145
 146                 scrm: scrm@4ae0a000 {
 147                         compatible = "ti,omap5-scrm";
 148                         reg = <0x4ae0a000 0x2000>;
 149
 150                         scrm_clocks: clocks {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153                         };
 154
 155                         scrm_clockdomains: clockdomains {
 156                         };
 157                 };
 158
 159                 cm_core: cm_core@4a008000 {
 160                         compatible = "ti,omap5-cm-core";
 161                         reg = <0x4a008000 0x3000>;
 162
 163                         cm_core_clocks: clocks {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                         };
 167
 168                         cm_core_clockdomains: clockdomains {
 169                         };
 170                 };
 171
 172                 counter32k: counter@4ae04000 {
 173                         compatible = "ti,omap-counter32k";
 174                         reg = <0x4ae04000 0x40>;
 175                         ti,hwmods = "counter_32k";
 176                 };
 177
 178                 omap5_pmx_core: pinmux@4a002840 {
 179                         compatible = "ti,omap4-padconf", "pinctrl-single";
 180                         reg = <0x4a002840 0x01b6>;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         pinctrl-single,register-width = <16>;
 184                         pinctrl-single,function-mask = <0x7fff>;
 185                 };
 186                 omap5_pmx_wkup: pinmux@4ae0c840 {
 187                         compatible = "ti,omap4-padconf", "pinctrl-single";
 188                         reg = <0x4ae0c840 0x0038>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         pinctrl-single,register-width = <16>;
 192                         pinctrl-single,function-mask = <0x7fff>;
 193                 };
 194
 195                 sdma: dma-controller@4a056000 {
 196                         compatible = "ti,omap4430-sdma";
 197                         reg = <0x4a056000 0x1000>;
 198                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 202                         #dma-cells = <1>;
 203                         #dma-channels = <32>;
 204                         #dma-requests = <127>;
 205                 };
 206
 207                 gpio1: gpio@4ae10000 {
 208                         compatible = "ti,omap4-gpio";
 209                         reg = <0x4ae10000 0x200>;
 210                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 211                         ti,hwmods = "gpio1";
 212                         ti,gpio-always-on;
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <2>;
 217                 };
 218
 219                 gpio2: gpio@48055000 {
 220                         compatible = "ti,omap4-gpio";
 221                         reg = <0x48055000 0x200>;
 222                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 223                         ti,hwmods = "gpio2";
 224                         gpio-controller;
 225                         #gpio-cells = <2>;
 226                         interrupt-controller;
 227                         #interrupt-cells = <2>;
 228                 };
 229
 230                 gpio3: gpio@48057000 {
 231                         compatible = "ti,omap4-gpio";
 232                         reg = <0x48057000 0x200>;
 233                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 234                         ti,hwmods = "gpio3";
 235                         gpio-controller;
 236                         #gpio-cells = <2>;
 237                         interrupt-controller;
 238                         #interrupt-cells = <2>;
 239                 };
 240
 241                 gpio4: gpio@48059000 {
 242                         compatible = "ti,omap4-gpio";
 243                         reg = <0x48059000 0x200>;
 244                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 245                         ti,hwmods = "gpio4";
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248                         interrupt-controller;
 249                         #interrupt-cells = <2>;
 250                 };
 251
 252                 gpio5: gpio@4805b000 {
 253                         compatible = "ti,omap4-gpio";
 254                         reg = <0x4805b000 0x200>;
 255                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 256                         ti,hwmods = "gpio5";
 257                         gpio-controller;
 258                         #gpio-cells = <2>;
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 gpio6: gpio@4805d000 {
 264                         compatible = "ti,omap4-gpio";
 265                         reg = <0x4805d000 0x200>;
 266                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 267                         ti,hwmods = "gpio6";
 268                         gpio-controller;
 269                         #gpio-cells = <2>;
 270                         interrupt-controller;
 271                         #interrupt-cells = <2>;
 272                 };
 273
 274                 gpio7: gpio@48051000 {
 275                         compatible = "ti,omap4-gpio";
 276                         reg = <0x48051000 0x200>;
 277                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 278                         ti,hwmods = "gpio7";
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         interrupt-controller;
 282                         #interrupt-cells = <2>;
 283                 };
 284
 285                 gpio8: gpio@48053000 {
 286                         compatible = "ti,omap4-gpio";
 287                         reg = <0x48053000 0x200>;
 288                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 289                         ti,hwmods = "gpio8";
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpmc: gpmc@50000000 {
 297                         compatible = "ti,omap4430-gpmc";
 298                         reg = <0x50000000 0x1000>;
 299                         #address-cells = <2>;
 300                         #size-cells = <1>;
 301                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 302                         gpmc,num-cs = <8>;
 303                         gpmc,num-waitpins = <4>;
 304                         ti,hwmods = "gpmc";
 305                         clocks = <&l3_iclk_div>;
 306                         clock-names = "fck";
 307                 };
 308
 309                 i2c1: i2c@48070000 {
 310                         compatible = "ti,omap4-i2c";
 311                         reg = <0x48070000 0x100>;
 312                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         ti,hwmods = "i2c1";
 316                 };
 317
 318                 i2c2: i2c@48072000 {
 319                         compatible = "ti,omap4-i2c";
 320                         reg = <0x48072000 0x100>;
 321                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         ti,hwmods = "i2c2";
 325                 };
 326
 327                 i2c3: i2c@48060000 {
 328                         compatible = "ti,omap4-i2c";
 329                         reg = <0x48060000 0x100>;
 330                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         ti,hwmods = "i2c3";
 334                 };
 335
 336                 i2c4: i2c@4807a000 {
 337                         compatible = "ti,omap4-i2c";
 338                         reg = <0x4807a000 0x100>;
 339                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         ti,hwmods = "i2c4";
 343                 };
 344
 345                 i2c5: i2c@4807c000 {
 346                         compatible = "ti,omap4-i2c";
 347                         reg = <0x4807c000 0x100>;
 348                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         ti,hwmods = "i2c5";
 352                 };
 353
 354                 hwspinlock: spinlock@4a0f6000 {
 355                         compatible = "ti,omap4-hwspinlock";
 356                         reg = <0x4a0f6000 0x1000>;
 357                         ti,hwmods = "spinlock";
 358                 };
 359
 360                 mcspi1: spi@48098000 {
 361                         compatible = "ti,omap4-mcspi";
 362                         reg = <0x48098000 0x200>;
 363                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         ti,hwmods = "mcspi1";
 367                         ti,spi-num-cs = <4>;
 368                         dmas = <&sdma 35>,
 369                                <&sdma 36>,
 370                                <&sdma 37>,
 371                                <&sdma 38>,
 372                                <&sdma 39>,
 373                                <&sdma 40>,
 374                                <&sdma 41>,
 375                                <&sdma 42>;
 376                         dma-names = "tx0", "rx0", "tx1", "rx1",
 377                                     "tx2", "rx2", "tx3", "rx3";
 378                 };
 379
 380                 mcspi2: spi@4809a000 {
 381                         compatible = "ti,omap4-mcspi";
 382                         reg = <0x4809a000 0x200>;
 383                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         ti,hwmods = "mcspi2";
 387                         ti,spi-num-cs = <2>;
 388                         dmas = <&sdma 43>,
 389                                <&sdma 44>,
 390                                <&sdma 45>,
 391                                <&sdma 46>;
 392                         dma-names = "tx0", "rx0", "tx1", "rx1";
 393                 };
 394
 395                 mcspi3: spi@480b8000 {
 396                         compatible = "ti,omap4-mcspi";
 397                         reg = <0x480b8000 0x200>;
 398                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         ti,hwmods = "mcspi3";
 402                         ti,spi-num-cs = <2>;
 403                         dmas = <&sdma 15>, <&sdma 16>;
 404                         dma-names = "tx0", "rx0";
 405                 };
 406
 407                 mcspi4: spi@480ba000 {
 408                         compatible = "ti,omap4-mcspi";
 409                         reg = <0x480ba000 0x200>;
 410                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         ti,hwmods = "mcspi4";
 414                         ti,spi-num-cs = <1>;
 415                         dmas = <&sdma 70>, <&sdma 71>;
 416                         dma-names = "tx0", "rx0";
 417                 };
 418
 419                 uart1: serial@4806a000 {
 420                         compatible = "ti,omap4-uart";
 421                         reg = <0x4806a000 0x100>;
 422                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 423                         ti,hwmods = "uart1";
 424                         clock-frequency = <48000000>;
 425                 };
 426
 427                 uart2: serial@4806c000 {
 428                         compatible = "ti,omap4-uart";
 429                         reg = <0x4806c000 0x100>;
 430                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 431                         ti,hwmods = "uart2";
 432                         clock-frequency = <48000000>;
 433                 };
 434
 435                 uart3: serial@48020000 {
 436                         compatible = "ti,omap4-uart";
 437                         reg = <0x48020000 0x100>;
 438                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 439                         ti,hwmods = "uart3";
 440                         clock-frequency = <48000000>;
 441                 };
 442
 443                 uart4: serial@4806e000 {
 444                         compatible = "ti,omap4-uart";
 445                         reg = <0x4806e000 0x100>;
 446                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 447                         ti,hwmods = "uart4";
 448                         clock-frequency = <48000000>;
 449                 };
 450
 451                 uart5: serial@48066000 {
 452                         compatible = "ti,omap4-uart";
 453                         reg = <0x48066000 0x100>;
 454                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 455                         ti,hwmods = "uart5";
 456                         clock-frequency = <48000000>;
 457                 };
 458
 459                 uart6: serial@48068000 {
 460                         compatible = "ti,omap4-uart";
 461                         reg = <0x48068000 0x100>;
 462                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 463                         ti,hwmods = "uart6";
 464                         clock-frequency = <48000000>;
 465                 };
 466
 467                 mmc1: mmc@4809c000 {
 468                         compatible = "ti,omap4-hsmmc";
 469                         reg = <0x4809c000 0x400>;
 470                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 471                         ti,hwmods = "mmc1";
 472                         ti,dual-volt;
 473                         ti,needs-special-reset;
 474                         dmas = <&sdma 61>, <&sdma 62>;
 475                         dma-names = "tx", "rx";
 476                 };
 477
 478                 mmc2: mmc@480b4000 {
 479                         compatible = "ti,omap4-hsmmc";
 480                         reg = <0x480b4000 0x400>;
 481                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 482                         ti,hwmods = "mmc2";
 483                         ti,needs-special-reset;
 484                         dmas = <&sdma 47>, <&sdma 48>;
 485                         dma-names = "tx", "rx";
 486                 };
 487
 488                 mmc3: mmc@480ad000 {
 489                         compatible = "ti,omap4-hsmmc";
 490                         reg = <0x480ad000 0x400>;
 491                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 492                         ti,hwmods = "mmc3";
 493                         ti,needs-special-reset;
 494                         dmas = <&sdma 77>, <&sdma 78>;
 495                         dma-names = "tx", "rx";
 496                 };
 497
 498                 mmc4: mmc@480d1000 {
 499                         compatible = "ti,omap4-hsmmc";
 500                         reg = <0x480d1000 0x400>;
 501                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 502                         ti,hwmods = "mmc4";
 503                         ti,needs-special-reset;
 504                         dmas = <&sdma 57>, <&sdma 58>;
 505                         dma-names = "tx", "rx";
 506                 };
 507
 508                 mmc5: mmc@480d5000 {
 509                         compatible = "ti,omap4-hsmmc";
 510                         reg = <0x480d5000 0x400>;
 511                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 512                         ti,hwmods = "mmc5";
 513                         ti,needs-special-reset;
 514                         dmas = <&sdma 59>, <&sdma 60>;
 515                         dma-names = "tx", "rx";
 516                 };
 517
 518                 keypad: keypad@4ae1c000 {
 519                         compatible = "ti,omap4-keypad";
 520                         reg = <0x4ae1c000 0x400>;
 521                         ti,hwmods = "kbd";
 522                 };
 523
 524                 mcpdm: mcpdm@40132000 {
 525                         compatible = "ti,omap4-mcpdm";
 526                         reg = <0x40132000 0x7f>, /* MPU private access */
 527                               <0x49032000 0x7f>; /* L3 Interconnect */
 528                         reg-names = "mpu", "dma";
 529                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 530                         ti,hwmods = "mcpdm";
 531                         dmas = <&sdma 65>,
 532                                <&sdma 66>;
 533                         dma-names = "up_link", "dn_link";
 534                 };
 535
 536                 dmic: dmic@4012e000 {
 537                         compatible = "ti,omap4-dmic";
 538                         reg = <0x4012e000 0x7f>, /* MPU private access */
 539                               <0x4902e000 0x7f>; /* L3 Interconnect */
 540                         reg-names = "mpu", "dma";
 541                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 542                         ti,hwmods = "dmic";
 543                         dmas = <&sdma 67>;
 544                         dma-names = "up_link";
 545                 };
 546
 547                 mcbsp1: mcbsp@40122000 {
 548                         compatible = "ti,omap4-mcbsp";
 549                         reg = <0x40122000 0xff>, /* MPU private access */
 550                               <0x49022000 0xff>; /* L3 Interconnect */
 551                         reg-names = "mpu", "dma";
 552                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 553                         interrupt-names = "common";
 554                         ti,buffer-size = <128>;
 555                         ti,hwmods = "mcbsp1";
 556                         dmas = <&sdma 33>,
 557                                <&sdma 34>;
 558                         dma-names = "tx", "rx";
 559                 };
 560
 561                 mcbsp2: mcbsp@40124000 {
 562                         compatible = "ti,omap4-mcbsp";
 563                         reg = <0x40124000 0xff>, /* MPU private access */
 564                               <0x49024000 0xff>; /* L3 Interconnect */
 565                         reg-names = "mpu", "dma";
 566                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 567                         interrupt-names = "common";
 568                         ti,buffer-size = <128>;
 569                         ti,hwmods = "mcbsp2";
 570                         dmas = <&sdma 17>,
 571                                <&sdma 18>;
 572                         dma-names = "tx", "rx";
 573                 };
 574
 575                 mcbsp3: mcbsp@40126000 {
 576                         compatible = "ti,omap4-mcbsp";
 577                         reg = <0x40126000 0xff>, /* MPU private access */
 578                               <0x49026000 0xff>; /* L3 Interconnect */
 579                         reg-names = "mpu", "dma";
 580                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 581                         interrupt-names = "common";
 582                         ti,buffer-size = <128>;
 583                         ti,hwmods = "mcbsp3";
 584                         dmas = <&sdma 19>,
 585                                <&sdma 20>;
 586                         dma-names = "tx", "rx";
 587                 };
 588
 589                 timer1: timer@4ae18000 {
 590                         compatible = "ti,omap5430-timer";
 591                         reg = <0x4ae18000 0x80>;
 592                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 593                         ti,hwmods = "timer1";
 594                         ti,timer-alwon;
 595                 };
 596
 597                 timer2: timer@48032000 {
 598                         compatible = "ti,omap5430-timer";
 599                         reg = <0x48032000 0x80>;
 600                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 601                         ti,hwmods = "timer2";
 602                 };
 603
 604                 timer3: timer@48034000 {
 605                         compatible = "ti,omap5430-timer";
 606                         reg = <0x48034000 0x80>;
 607                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 608                         ti,hwmods = "timer3";
 609                 };
 610
 611                 timer4: timer@48036000 {
 612                         compatible = "ti,omap5430-timer";
 613                         reg = <0x48036000 0x80>;
 614                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 615                         ti,hwmods = "timer4";
 616                 };
 617
 618                 timer5: timer@40138000 {
 619                         compatible = "ti,omap5430-timer";
 620                         reg = <0x40138000 0x80>,
 621                               <0x49038000 0x80>;
 622                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "timer5";
 624                         ti,timer-dsp;
 625                         ti,timer-pwm;
 626                 };
 627
 628                 timer6: timer@4013a000 {
 629                         compatible = "ti,omap5430-timer";
 630                         reg = <0x4013a000 0x80>,
 631                               <0x4903a000 0x80>;
 632                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 633                         ti,hwmods = "timer6";
 634                         ti,timer-dsp;
 635                         ti,timer-pwm;
 636                 };
 637
 638                 timer7: timer@4013c000 {
 639                         compatible = "ti,omap5430-timer";
 640                         reg = <0x4013c000 0x80>,
 641                               <0x4903c000 0x80>;
 642                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 643                         ti,hwmods = "timer7";
 644                         ti,timer-dsp;
 645                 };
 646
 647                 timer8: timer@4013e000 {
 648                         compatible = "ti,omap5430-timer";
 649                         reg = <0x4013e000 0x80>,
 650                               <0x4903e000 0x80>;
 651                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 652                         ti,hwmods = "timer8";
 653                         ti,timer-dsp;
 654                         ti,timer-pwm;
 655                 };
 656
 657                 timer9: timer@4803e000 {
 658                         compatible = "ti,omap5430-timer";
 659                         reg = <0x4803e000 0x80>;
 660                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 661                         ti,hwmods = "timer9";
 662                         ti,timer-pwm;
 663                 };
 664
 665                 timer10: timer@48086000 {
 666                         compatible = "ti,omap5430-timer";
 667                         reg = <0x48086000 0x80>;
 668                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 669                         ti,hwmods = "timer10";
 670                         ti,timer-pwm;
 671                 };
 672
 673                 timer11: timer@48088000 {
 674                         compatible = "ti,omap5430-timer";
 675                         reg = <0x48088000 0x80>;
 676                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 677                         ti,hwmods = "timer11";
 678                         ti,timer-pwm;
 679                 };
 680
 681                 wdt2: wdt@4ae14000 {
 682                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 683                         reg = <0x4ae14000 0x80>;
 684                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 685                         ti,hwmods = "wd_timer2";
 686                 };
 687
 688                 emif1: emif@4c000000 {
 689                         compatible      = "ti,emif-4d5";
 690                         ti,hwmods       = "emif1";
 691                         ti,no-idle-on-init;
 692                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 693                         reg = <0x4c000000 0x400>;
 694                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 695                         hw-caps-read-idle-ctrl;
 696                         hw-caps-ll-interface;
 697                         hw-caps-temp-alert;
 698                 };
 699
 700                 emif2: emif@4d000000 {
 701                         compatible      = "ti,emif-4d5";
 702                         ti,hwmods       = "emif2";
 703                         ti,no-idle-on-init;
 704                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 705                         reg = <0x4d000000 0x400>;
 706                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 707                         hw-caps-read-idle-ctrl;
 708                         hw-caps-ll-interface;
 709                         hw-caps-temp-alert;
 710                 };
 711
 712                 omap_control_usb2phy: control-phy@4a002300 {
 713                         compatible = "ti,control-phy-usb2";
 714                         reg = <0x4a002300 0x4>;
 715                         reg-names = "power";
 716                 };
 717
 718                 omap_control_usb3phy: control-phy@4a002370 {
 719                         compatible = "ti,control-phy-pipe3";
 720                         reg = <0x4a002370 0x4>;
 721                         reg-names = "power";
 722                 };
 723
 724                 usb3: omap_dwc3@4a020000 {
 725                         compatible = "ti,dwc3";
 726                         ti,hwmods = "usb_otg_ss";
 727                         reg = <0x4a020000 0x10000>;
 728                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 729                         #address-cells = <1>;
 730                         #size-cells = <1>;
 731                         utmi-mode = <2>;
 732                         ranges;
 733                         dwc3@4a030000 {
 734                                 compatible = "snps,dwc3";
 735                                 reg = <0x4a030000 0x10000>;
 736                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 737                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
 738                                 dr_mode = "peripheral";
 739                                 tx-fifo-resize;
 740                         };
 741                 };
 742
 743                 ocp2scp@4a080000 {
 744                         compatible = "ti,omap-ocp2scp";
 745                         #address-cells = <1>;
 746                         #size-cells = <1>;
 747                         reg = <0x4a080000 0x20>;
 748                         ranges;
 749                         ti,hwmods = "ocp2scp1";
 750                         usb2_phy: usb2phy@4a084000 {
 751                                 compatible = "ti,omap-usb2";
 752                                 reg = <0x4a084000 0x7c>;
 753                                 ctrl-module = <&omap_control_usb2phy>;
 754                         };
 755
 756                         usb3_phy: usb3phy@4a084400 {
 757                                 compatible = "ti,omap-usb3";
 758                                 reg = <0x4a084400 0x80>,
 759                                       <0x4a084800 0x64>,
 760                                       <0x4a084c00 0x40>;
 761                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 762                                 ctrl-module = <&omap_control_usb3phy>;
 763                         };
 764                 };
 765
 766                 usbhstll: usbhstll@4a062000 {
 767                         compatible = "ti,usbhs-tll";
 768                         reg = <0x4a062000 0x1000>;
 769                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 770                         ti,hwmods = "usb_tll_hs";
 771                 };
 772
 773                 usbhshost: usbhshost@4a064000 {
 774                         compatible = "ti,usbhs-host";
 775                         reg = <0x4a064000 0x800>;
 776                         ti,hwmods = "usb_host_hs";
 777                         #address-cells = <1>;
 778                         #size-cells = <1>;
 779                         ranges;
 780
 781                         usbhsohci: ohci@4a064800 {
 782                                 compatible = "ti,ohci-omap3", "usb-ohci";
 783                                 reg = <0x4a064800 0x400>;
 784                                 interrupt-parent = <&gic>;
 785                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 786                         };
 787
 788                         usbhsehci: ehci@4a064c00 {
 789                                 compatible = "ti,ehci-omap", "usb-ehci";
 790                                 reg = <0x4a064c00 0x400>;
 791                                 interrupt-parent = <&gic>;
 792                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 793                         };
 794                 };
 795
 796                 bandgap: bandgap@4a0021e0 {
 797                         reg = <0x4a0021e0 0xc
 798                                0x4a00232c 0xc
 799                                0x4a002380 0x2c
 800                                0x4a0023C0 0x3c>;
 801                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 802                         compatible = "ti,omap5430-bandgap";
 803
 804                         #thermal-sensor-cells = <1>;
 805                 };
 806         };
 807 };
 808
 809 /include/ "omap54xx-clocks.dtsi"