arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <2>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                 };
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 #include "omap4-cpu-thermal.dtsi"
  71                 #include "omap5-gpu-thermal.dtsi"
  72                 #include "omap5-core-thermal.dtsi"
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 /* PPI secure/nonsecure IRQ */
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  82         };
  83
  84         pmu {
  85                 compatible = "arm,cortex-a15-pmu";
  86                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  88         };
  89
  90         gic: interrupt-controller@48211000 {
  91                 compatible = "arm,cortex-a15-gic";
  92                 interrupt-controller;
  93                 #interrupt-cells = <3>;
  94                 reg = <0x48211000 0x1000>,
  95                       <0x48212000 0x1000>,
  96                       <0x48214000 0x2000>,
  97                       <0x48216000 0x2000>;
  98         };
  99
 100         /*
 101          * The soc node represents the soc top level view. It is used for IPs
 102          * that are not memory mapped in the MPU view or for the MPU itself.
 103          */
 104         soc {
 105                 compatible = "ti,omap-infra";
 106                 mpu {
 107                         compatible = "ti,omap4-mpu";
 108                         ti,hwmods = "mpu";
 109                         sram = <&ocmcram>;
 110                 };
 111         };
 112
 113         /*
 114          * XXX: Use a flat representation of the OMAP3 interconnect.
 115          * The real OMAP interconnect network is quite complex.
 116          * Since it will not bring real advantage to represent that in DT for
 117          * the moment, just use a fake OCP bus entry to represent the whole bus
 118          * hierarchy.
 119          */
 120         ocp {
 121                 compatible = "ti,omap4-l3-noc", "simple-bus";
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 ranges;
 125                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 126                 reg = <0x44000000 0x2000>,
 127                       <0x44800000 0x3000>,
 128                       <0x45000000 0x4000>;
 129                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 130                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 131
 132                 l4_cfg: l4@4a000000 {
 133                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 134                         #address-cells = <1>;
 135                         #size-cells = <1>;
 136                         ranges = <0 0x4a000000 0x22a000>;
 137
 138                         scm_core: scm@2000 {
 139                                 compatible = "ti,omap5-scm-core", "simple-bus";
 140                                 reg = <0x2000 0x1000>;
 141                                 #address-cells = <1>;
 142                                 #size-cells = <1>;
 143                                 ranges = <0 0x2000 0x800>;
 144
 145                                 scm_conf: scm_conf@0 {
 146                                         compatible = "syscon";
 147                                         reg = <0x0 0x800>;
 148                                         #address-cells = <1>;
 149                                         #size-cells = <1>;
 150                                 };
 151                         };
 152
 153                         scm_padconf_core: scm@2800 {
 154                                 compatible = "ti,omap5-scm-padconf-core",
 155                                              "simple-bus";
 156                                 #address-cells = <1>;
 157                                 #size-cells = <1>;
 158                                 ranges = <0 0x2800 0x800>;
 159
 160                                 omap5_pmx_core: pinmux@40 {
 161                                         compatible = "ti,omap5-padconf",
 162                                                      "pinctrl-single";
 163                                         reg = <0x40 0x01b6>;
 164                                         #address-cells = <1>;
 165                                         #size-cells = <0>;
 166                                         #interrupt-cells = <1>;
 167                                         interrupt-controller;
 168                                         pinctrl-single,register-width = <16>;
 169                                         pinctrl-single,function-mask = <0x7fff>;
 170                                 };
 171
 172                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 173                                         compatible = "syscon";
 174                                         reg = <0x5a0 0xec>;
 175                                         #address-cells = <1>;
 176                                         #size-cells = <1>;
 177
 178                                         pbias_regulator: pbias_regulator {
 179                                                 compatible = "ti,pbias-omap";
 180                                                 reg = <0x60 0x4>;
 181                                                 syscon = <&omap5_padconf_global>;
 182                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 183                                                         regulator-name = "pbias_mmc_omap5";
 184                                                         regulator-min-microvolt = <1800000>;
 185                                                         regulator-max-microvolt = <3000000>;
 186                                                 };
 187                                         };
 188                                 };
 189                         };
 190
 191                         cm_core_aon: cm_core_aon@4000 {
 192                                 compatible = "ti,omap5-cm-core-aon";
 193                                 reg = <0x4000 0x2000>;
 194
 195                                 cm_core_aon_clocks: clocks {
 196                                         #address-cells = <1>;
 197                                         #size-cells = <0>;
 198                                 };
 199
 200                                 cm_core_aon_clockdomains: clockdomains {
 201                                 };
 202                         };
 203
 204                         cm_core: cm_core@8000 {
 205                                 compatible = "ti,omap5-cm-core";
 206                                 reg = <0x8000 0x3000>;
 207
 208                                 cm_core_clocks: clocks {
 209                                         #address-cells = <1>;
 210                                         #size-cells = <0>;
 211                                 };
 212
 213                                 cm_core_clockdomains: clockdomains {
 214                                 };
 215                         };
 216                 };
 217
 218                 l4_wkup: l4@4ae00000 {
 219                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222                         ranges = <0 0x4ae00000 0x2b000>;
 223
 224                         counter32k: counter@4000 {
 225                                 compatible = "ti,omap-counter32k";
 226                                 reg = <0x4000 0x40>;
 227                                 ti,hwmods = "counter_32k";
 228                         };
 229
 230                         prm: prm@6000 {
 231                                 compatible = "ti,omap5-prm";
 232                                 reg = <0x6000 0x3000>;
 233                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 234
 235                                 prm_clocks: clocks {
 236                                         #address-cells = <1>;
 237                                         #size-cells = <0>;
 238                                 };
 239
 240                                 prm_clockdomains: clockdomains {
 241                                 };
 242                         };
 243
 244                         scrm: scrm@a000 {
 245                                 compatible = "ti,omap5-scrm";
 246                                 reg = <0xa000 0x2000>;
 247
 248                                 scrm_clocks: clocks {
 249                                         #address-cells = <1>;
 250                                         #size-cells = <0>;
 251                                 };
 252
 253                                 scrm_clockdomains: clockdomains {
 254                                 };
 255                         };
 256
 257                         omap5_pmx_wkup: pinmux@c840 {
 258                                 compatible = "ti,omap5-padconf",
 259                                              "pinctrl-single";
 260                                 reg = <0xc840 0x0038>;
 261                                 #address-cells = <1>;
 262                                 #size-cells = <0>;
 263                                 #interrupt-cells = <1>;
 264                                 interrupt-controller;
 265                                 pinctrl-single,register-width = <16>;
 266                                 pinctrl-single,function-mask = <0x7fff>;
 267                         };
 268                 };
 269
 270                 ocmcram: ocmcram@40300000 {
 271                         compatible = "mmio-sram";
 272                         reg = <0x40300000 0x20000>; /* 128k */
 273                 };
 274
 275                 sdma: dma-controller@4a056000 {
 276                         compatible = "ti,omap4430-sdma";
 277                         reg = <0x4a056000 0x1000>;
 278                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 282                         #dma-cells = <1>;
 283                         dma-channels = <32>;
 284                         dma-requests = <127>;
 285                 };
 286
 287                 gpio1: gpio@4ae10000 {
 288                         compatible = "ti,omap4-gpio";
 289                         reg = <0x4ae10000 0x200>;
 290                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 291                         ti,hwmods = "gpio1";
 292                         ti,gpio-always-on;
 293                         gpio-controller;
 294                         #gpio-cells = <2>;
 295                         interrupt-controller;
 296                         #interrupt-cells = <2>;
 297                 };
 298
 299                 gpio2: gpio@48055000 {
 300                         compatible = "ti,omap4-gpio";
 301                         reg = <0x48055000 0x200>;
 302                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 303                         ti,hwmods = "gpio2";
 304                         gpio-controller;
 305                         #gpio-cells = <2>;
 306                         interrupt-controller;
 307                         #interrupt-cells = <2>;
 308                 };
 309
 310                 gpio3: gpio@48057000 {
 311                         compatible = "ti,omap4-gpio";
 312                         reg = <0x48057000 0x200>;
 313                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 314                         ti,hwmods = "gpio3";
 315                         gpio-controller;
 316                         #gpio-cells = <2>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                 };
 320
 321                 gpio4: gpio@48059000 {
 322                         compatible = "ti,omap4-gpio";
 323                         reg = <0x48059000 0x200>;
 324                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 325                         ti,hwmods = "gpio4";
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <2>;
 330                 };
 331
 332                 gpio5: gpio@4805b000 {
 333                         compatible = "ti,omap4-gpio";
 334                         reg = <0x4805b000 0x200>;
 335                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 336                         ti,hwmods = "gpio5";
 337                         gpio-controller;
 338                         #gpio-cells = <2>;
 339                         interrupt-controller;
 340                         #interrupt-cells = <2>;
 341                 };
 342
 343                 gpio6: gpio@4805d000 {
 344                         compatible = "ti,omap4-gpio";
 345                         reg = <0x4805d000 0x200>;
 346                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 347                         ti,hwmods = "gpio6";
 348                         gpio-controller;
 349                         #gpio-cells = <2>;
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                 };
 353
 354                 gpio7: gpio@48051000 {
 355                         compatible = "ti,omap4-gpio";
 356                         reg = <0x48051000 0x200>;
 357                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 358                         ti,hwmods = "gpio7";
 359                         gpio-controller;
 360                         #gpio-cells = <2>;
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                 };
 364
 365                 gpio8: gpio@48053000 {
 366                         compatible = "ti,omap4-gpio";
 367                         reg = <0x48053000 0x200>;
 368                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 369                         ti,hwmods = "gpio8";
 370                         gpio-controller;
 371                         #gpio-cells = <2>;
 372                         interrupt-controller;
 373                         #interrupt-cells = <2>;
 374                 };
 375
 376                 gpmc: gpmc@50000000 {
 377                         compatible = "ti,omap4430-gpmc";
 378                         reg = <0x50000000 0x1000>;
 379                         #address-cells = <2>;
 380                         #size-cells = <1>;
 381                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 382                         gpmc,num-cs = <8>;
 383                         gpmc,num-waitpins = <4>;
 384                         ti,hwmods = "gpmc";
 385                         clocks = <&l3_iclk_div>;
 386                         clock-names = "fck";
 387                 };
 388
 389                 i2c1: i2c@48070000 {
 390                         compatible = "ti,omap4-i2c";
 391                         reg = <0x48070000 0x100>;
 392                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         ti,hwmods = "i2c1";
 396                 };
 397
 398                 i2c2: i2c@48072000 {
 399                         compatible = "ti,omap4-i2c";
 400                         reg = <0x48072000 0x100>;
 401                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         ti,hwmods = "i2c2";
 405                 };
 406
 407                 i2c3: i2c@48060000 {
 408                         compatible = "ti,omap4-i2c";
 409                         reg = <0x48060000 0x100>;
 410                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         ti,hwmods = "i2c3";
 414                 };
 415
 416                 i2c4: i2c@4807a000 {
 417                         compatible = "ti,omap4-i2c";
 418                         reg = <0x4807a000 0x100>;
 419                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         ti,hwmods = "i2c4";
 423                 };
 424
 425                 i2c5: i2c@4807c000 {
 426                         compatible = "ti,omap4-i2c";
 427                         reg = <0x4807c000 0x100>;
 428                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         ti,hwmods = "i2c5";
 432                 };
 433
 434                 hwspinlock: spinlock@4a0f6000 {
 435                         compatible = "ti,omap4-hwspinlock";
 436                         reg = <0x4a0f6000 0x1000>;
 437                         ti,hwmods = "spinlock";
 438                         #hwlock-cells = <1>;
 439                 };
 440
 441                 mcspi1: spi@48098000 {
 442                         compatible = "ti,omap4-mcspi";
 443                         reg = <0x48098000 0x200>;
 444                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         ti,hwmods = "mcspi1";
 448                         ti,spi-num-cs = <4>;
 449                         dmas = <&sdma 35>,
 450                                <&sdma 36>,
 451                                <&sdma 37>,
 452                                <&sdma 38>,
 453                                <&sdma 39>,
 454                                <&sdma 40>,
 455                                <&sdma 41>,
 456                                <&sdma 42>;
 457                         dma-names = "tx0", "rx0", "tx1", "rx1",
 458                                     "tx2", "rx2", "tx3", "rx3";
 459                 };
 460
 461                 mcspi2: spi@4809a000 {
 462                         compatible = "ti,omap4-mcspi";
 463                         reg = <0x4809a000 0x200>;
 464                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         ti,hwmods = "mcspi2";
 468                         ti,spi-num-cs = <2>;
 469                         dmas = <&sdma 43>,
 470                                <&sdma 44>,
 471                                <&sdma 45>,
 472                                <&sdma 46>;
 473                         dma-names = "tx0", "rx0", "tx1", "rx1";
 474                 };
 475
 476                 mcspi3: spi@480b8000 {
 477                         compatible = "ti,omap4-mcspi";
 478                         reg = <0x480b8000 0x200>;
 479                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         ti,hwmods = "mcspi3";
 483                         ti,spi-num-cs = <2>;
 484                         dmas = <&sdma 15>, <&sdma 16>;
 485                         dma-names = "tx0", "rx0";
 486                 };
 487
 488                 mcspi4: spi@480ba000 {
 489                         compatible = "ti,omap4-mcspi";
 490                         reg = <0x480ba000 0x200>;
 491                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         ti,hwmods = "mcspi4";
 495                         ti,spi-num-cs = <1>;
 496                         dmas = <&sdma 70>, <&sdma 71>;
 497                         dma-names = "tx0", "rx0";
 498                 };
 499
 500                 uart1: serial@4806a000 {
 501                         compatible = "ti,omap4-uart";
 502                         reg = <0x4806a000 0x100>;
 503                         interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 504                         ti,hwmods = "uart1";
 505                         clock-frequency = <48000000>;
 506                 };
 507
 508                 uart2: serial@4806c000 {
 509                         compatible = "ti,omap4-uart";
 510                         reg = <0x4806c000 0x100>;
 511                         interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 512                         ti,hwmods = "uart2";
 513                         clock-frequency = <48000000>;
 514                 };
 515
 516                 uart3: serial@48020000 {
 517                         compatible = "ti,omap4-uart";
 518                         reg = <0x48020000 0x100>;
 519                         interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "uart3";
 521                         clock-frequency = <48000000>;
 522                 };
 523
 524                 uart4: serial@4806e000 {
 525                         compatible = "ti,omap4-uart";
 526                         reg = <0x4806e000 0x100>;
 527                         interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 528                         ti,hwmods = "uart4";
 529                         clock-frequency = <48000000>;
 530                 };
 531
 532                 uart5: serial@48066000 {
 533                         compatible = "ti,omap4-uart";
 534                         reg = <0x48066000 0x100>;
 535                         interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 536                         ti,hwmods = "uart5";
 537                         clock-frequency = <48000000>;
 538                 };
 539
 540                 uart6: serial@48068000 {
 541                         compatible = "ti,omap4-uart";
 542                         reg = <0x48068000 0x100>;
 543                         interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 544                         ti,hwmods = "uart6";
 545                         clock-frequency = <48000000>;
 546                 };
 547
 548                 mmc1: mmc@4809c000 {
 549                         compatible = "ti,omap4-hsmmc";
 550                         reg = <0x4809c000 0x400>;
 551                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 552                         ti,hwmods = "mmc1";
 553                         ti,dual-volt;
 554                         ti,needs-special-reset;
 555                         dmas = <&sdma 61>, <&sdma 62>;
 556                         dma-names = "tx", "rx";
 557                         pbias-supply = <&pbias_mmc_reg>;
 558                 };
 559
 560                 mmc2: mmc@480b4000 {
 561                         compatible = "ti,omap4-hsmmc";
 562                         reg = <0x480b4000 0x400>;
 563                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 564                         ti,hwmods = "mmc2";
 565                         ti,needs-special-reset;
 566                         dmas = <&sdma 47>, <&sdma 48>;
 567                         dma-names = "tx", "rx";
 568                 };
 569
 570                 mmc3: mmc@480ad000 {
 571                         compatible = "ti,omap4-hsmmc";
 572                         reg = <0x480ad000 0x400>;
 573                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 574                         ti,hwmods = "mmc3";
 575                         ti,needs-special-reset;
 576                         dmas = <&sdma 77>, <&sdma 78>;
 577                         dma-names = "tx", "rx";
 578                 };
 579
 580                 mmc4: mmc@480d1000 {
 581                         compatible = "ti,omap4-hsmmc";
 582                         reg = <0x480d1000 0x400>;
 583                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 584                         ti,hwmods = "mmc4";
 585                         ti,needs-special-reset;
 586                         dmas = <&sdma 57>, <&sdma 58>;
 587                         dma-names = "tx", "rx";
 588                 };
 589
 590                 mmc5: mmc@480d5000 {
 591                         compatible = "ti,omap4-hsmmc";
 592                         reg = <0x480d5000 0x400>;
 593                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 594                         ti,hwmods = "mmc5";
 595                         ti,needs-special-reset;
 596                         dmas = <&sdma 59>, <&sdma 60>;
 597                         dma-names = "tx", "rx";
 598                 };
 599
 600                 mmu_dsp: mmu@4a066000 {
 601                         compatible = "ti,omap4-iommu";
 602                         reg = <0x4a066000 0x100>;
 603                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 604                         ti,hwmods = "mmu_dsp";
 605                 };
 606
 607                 mmu_ipu: mmu@55082000 {
 608                         compatible = "ti,omap4-iommu";
 609                         reg = <0x55082000 0x100>;
 610                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 611                         ti,hwmods = "mmu_ipu";
 612                         ti,iommu-bus-err-back;
 613                 };
 614
 615                 keypad: keypad@4ae1c000 {
 616                         compatible = "ti,omap4-keypad";
 617                         reg = <0x4ae1c000 0x400>;
 618                         ti,hwmods = "kbd";
 619                 };
 620
 621                 mcpdm: mcpdm@40132000 {
 622                         compatible = "ti,omap4-mcpdm";
 623                         reg = <0x40132000 0x7f>, /* MPU private access */
 624                               <0x49032000 0x7f>; /* L3 Interconnect */
 625                         reg-names = "mpu", "dma";
 626                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 627                         ti,hwmods = "mcpdm";
 628                         dmas = <&sdma 65>,
 629                                <&sdma 66>;
 630                         dma-names = "up_link", "dn_link";
 631                         status = "disabled";
 632                 };
 633
 634                 dmic: dmic@4012e000 {
 635                         compatible = "ti,omap4-dmic";
 636                         reg = <0x4012e000 0x7f>, /* MPU private access */
 637                               <0x4902e000 0x7f>; /* L3 Interconnect */
 638                         reg-names = "mpu", "dma";
 639                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 640                         ti,hwmods = "dmic";
 641                         dmas = <&sdma 67>;
 642                         dma-names = "up_link";
 643                         status = "disabled";
 644                 };
 645
 646                 mcbsp1: mcbsp@40122000 {
 647                         compatible = "ti,omap4-mcbsp";
 648                         reg = <0x40122000 0xff>, /* MPU private access */
 649                               <0x49022000 0xff>; /* L3 Interconnect */
 650                         reg-names = "mpu", "dma";
 651                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 652                         interrupt-names = "common";
 653                         ti,buffer-size = <128>;
 654                         ti,hwmods = "mcbsp1";
 655                         dmas = <&sdma 33>,
 656                                <&sdma 34>;
 657                         dma-names = "tx", "rx";
 658                         status = "disabled";
 659                 };
 660
 661                 mcbsp2: mcbsp@40124000 {
 662                         compatible = "ti,omap4-mcbsp";
 663                         reg = <0x40124000 0xff>, /* MPU private access */
 664                               <0x49024000 0xff>; /* L3 Interconnect */
 665                         reg-names = "mpu", "dma";
 666                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 667                         interrupt-names = "common";
 668                         ti,buffer-size = <128>;
 669                         ti,hwmods = "mcbsp2";
 670                         dmas = <&sdma 17>,
 671                                <&sdma 18>;
 672                         dma-names = "tx", "rx";
 673                         status = "disabled";
 674                 };
 675
 676                 mcbsp3: mcbsp@40126000 {
 677                         compatible = "ti,omap4-mcbsp";
 678                         reg = <0x40126000 0xff>, /* MPU private access */
 679                               <0x49026000 0xff>; /* L3 Interconnect */
 680                         reg-names = "mpu", "dma";
 681                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 682                         interrupt-names = "common";
 683                         ti,buffer-size = <128>;
 684                         ti,hwmods = "mcbsp3";
 685                         dmas = <&sdma 19>,
 686                                <&sdma 20>;
 687                         dma-names = "tx", "rx";
 688                         status = "disabled";
 689                 };
 690
 691                 mailbox: mailbox@4a0f4000 {
 692                         compatible = "ti,omap4-mailbox";
 693                         reg = <0x4a0f4000 0x200>;
 694                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 695                         ti,hwmods = "mailbox";
 696                         #mbox-cells = <1>;
 697                         ti,mbox-num-users = <3>;
 698                         ti,mbox-num-fifos = <8>;
 699                         mbox_ipu: mbox_ipu {
 700                                 ti,mbox-tx = <0 0 0>;
 701                                 ti,mbox-rx = <1 0 0>;
 702                         };
 703                         mbox_dsp: mbox_dsp {
 704                                 ti,mbox-tx = <3 0 0>;
 705                                 ti,mbox-rx = <2 0 0>;
 706                         };
 707                 };
 708
 709                 timer1: timer@4ae18000 {
 710                         compatible = "ti,omap5430-timer";
 711                         reg = <0x4ae18000 0x80>;
 712                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 713                         ti,hwmods = "timer1";
 714                         ti,timer-alwon;
 715                 };
 716
 717                 timer2: timer@48032000 {
 718                         compatible = "ti,omap5430-timer";
 719                         reg = <0x48032000 0x80>;
 720                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 721                         ti,hwmods = "timer2";
 722                 };
 723
 724                 timer3: timer@48034000 {
 725                         compatible = "ti,omap5430-timer";
 726                         reg = <0x48034000 0x80>;
 727                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 728                         ti,hwmods = "timer3";
 729                 };
 730
 731                 timer4: timer@48036000 {
 732                         compatible = "ti,omap5430-timer";
 733                         reg = <0x48036000 0x80>;
 734                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 735                         ti,hwmods = "timer4";
 736                 };
 737
 738                 timer5: timer@40138000 {
 739                         compatible = "ti,omap5430-timer";
 740                         reg = <0x40138000 0x80>,
 741                               <0x49038000 0x80>;
 742                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 743                         ti,hwmods = "timer5";
 744                         ti,timer-dsp;
 745                         ti,timer-pwm;
 746                 };
 747
 748                 timer6: timer@4013a000 {
 749                         compatible = "ti,omap5430-timer";
 750                         reg = <0x4013a000 0x80>,
 751                               <0x4903a000 0x80>;
 752                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 753                         ti,hwmods = "timer6";
 754                         ti,timer-dsp;
 755                         ti,timer-pwm;
 756                 };
 757
 758                 timer7: timer@4013c000 {
 759                         compatible = "ti,omap5430-timer";
 760                         reg = <0x4013c000 0x80>,
 761                               <0x4903c000 0x80>;
 762                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 763                         ti,hwmods = "timer7";
 764                         ti,timer-dsp;
 765                 };
 766
 767                 timer8: timer@4013e000 {
 768                         compatible = "ti,omap5430-timer";
 769                         reg = <0x4013e000 0x80>,
 770                               <0x4903e000 0x80>;
 771                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 772                         ti,hwmods = "timer8";
 773                         ti,timer-dsp;
 774                         ti,timer-pwm;
 775                 };
 776
 777                 timer9: timer@4803e000 {
 778                         compatible = "ti,omap5430-timer";
 779                         reg = <0x4803e000 0x80>;
 780                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 781                         ti,hwmods = "timer9";
 782                         ti,timer-pwm;
 783                 };
 784
 785                 timer10: timer@48086000 {
 786                         compatible = "ti,omap5430-timer";
 787                         reg = <0x48086000 0x80>;
 788                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 789                         ti,hwmods = "timer10";
 790                         ti,timer-pwm;
 791                 };
 792
 793                 timer11: timer@48088000 {
 794                         compatible = "ti,omap5430-timer";
 795                         reg = <0x48088000 0x80>;
 796                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 797                         ti,hwmods = "timer11";
 798                         ti,timer-pwm;
 799                 };
 800
 801                 wdt2: wdt@4ae14000 {
 802                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 803                         reg = <0x4ae14000 0x80>;
 804                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 805                         ti,hwmods = "wd_timer2";
 806                 };
 807
 808                 dmm@4e000000 {
 809                         compatible = "ti,omap5-dmm";
 810                         reg = <0x4e000000 0x800>;
 811                         interrupts = <0 113 0x4>;
 812                         ti,hwmods = "dmm";
 813                 };
 814
 815                 emif1: emif@4c000000 {
 816                         compatible      = "ti,emif-4d5";
 817                         ti,hwmods       = "emif1";
 818                         ti,no-idle-on-init;
 819                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 820                         reg = <0x4c000000 0x400>;
 821                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 822                         hw-caps-read-idle-ctrl;
 823                         hw-caps-ll-interface;
 824                         hw-caps-temp-alert;
 825                 };
 826
 827                 emif2: emif@4d000000 {
 828                         compatible      = "ti,emif-4d5";
 829                         ti,hwmods       = "emif2";
 830                         ti,no-idle-on-init;
 831                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 832                         reg = <0x4d000000 0x400>;
 833                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 834                         hw-caps-read-idle-ctrl;
 835                         hw-caps-ll-interface;
 836                         hw-caps-temp-alert;
 837                 };
 838
 839                 omap_control_usb2phy: control-phy@4a002300 {
 840                         compatible = "ti,control-phy-usb2";
 841                         reg = <0x4a002300 0x4>;
 842                         reg-names = "power";
 843                 };
 844
 845                 omap_control_usb3phy: control-phy@4a002370 {
 846                         compatible = "ti,control-phy-pipe3";
 847                         reg = <0x4a002370 0x4>;
 848                         reg-names = "power";
 849                 };
 850
 851                 usb3: omap_dwc3@4a020000 {
 852                         compatible = "ti,dwc3";
 853                         ti,hwmods = "usb_otg_ss";
 854                         reg = <0x4a020000 0x10000>;
 855                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 856                         #address-cells = <1>;
 857                         #size-cells = <1>;
 858                         utmi-mode = <2>;
 859                         ranges;
 860                         dwc3@4a030000 {
 861                                 compatible = "snps,dwc3";
 862                                 reg = <0x4a030000 0x10000>;
 863                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 864                                 phys = <&usb2_phy>, <&usb3_phy>;
 865                                 phy-names = "usb2-phy", "usb3-phy";
 866                                 dr_mode = "peripheral";
 867                                 tx-fifo-resize;
 868                         };
 869                 };
 870
 871                 ocp2scp@4a080000 {
 872                         compatible = "ti,omap-ocp2scp";
 873                         #address-cells = <1>;
 874                         #size-cells = <1>;
 875                         reg = <0x4a080000 0x20>;
 876                         ranges;
 877                         ti,hwmods = "ocp2scp1";
 878                         usb2_phy: usb2phy@4a084000 {
 879                                 compatible = "ti,omap-usb2";
 880                                 reg = <0x4a084000 0x7c>;
 881                                 ctrl-module = <&omap_control_usb2phy>;
 882                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 883                                 clock-names = "wkupclk", "refclk";
 884                                 #phy-cells = <0>;
 885                         };
 886
 887                         usb3_phy: usb3phy@4a084400 {
 888                                 compatible = "ti,omap-usb3";
 889                                 reg = <0x4a084400 0x80>,
 890                                       <0x4a084800 0x64>,
 891                                       <0x4a084c00 0x40>;
 892                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 893                                 ctrl-module = <&omap_control_usb3phy>;
 894                                 clocks = <&usb_phy_cm_clk32k>,
 895                                          <&sys_clkin>,
 896                                          <&usb_otg_ss_refclk960m>;
 897                                 clock-names =   "wkupclk",
 898                                                 "sysclk",
 899                                                 "refclk";
 900                                 #phy-cells = <0>;
 901                         };
 902                 };
 903
 904                 usbhstll: usbhstll@4a062000 {
 905                         compatible = "ti,usbhs-tll";
 906                         reg = <0x4a062000 0x1000>;
 907                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 908                         ti,hwmods = "usb_tll_hs";
 909                 };
 910
 911                 usbhshost: usbhshost@4a064000 {
 912                         compatible = "ti,usbhs-host";
 913                         reg = <0x4a064000 0x800>;
 914                         ti,hwmods = "usb_host_hs";
 915                         #address-cells = <1>;
 916                         #size-cells = <1>;
 917                         ranges;
 918                         clocks = <&l3init_60m_fclk>,
 919                                  <&xclk60mhsp1_ck>,
 920                                  <&xclk60mhsp2_ck>;
 921                         clock-names = "refclk_60m_int",
 922                                       "refclk_60m_ext_p1",
 923                                       "refclk_60m_ext_p2";
 924
 925                         usbhsohci: ohci@4a064800 {
 926                                 compatible = "ti,ohci-omap3";
 927                                 reg = <0x4a064800 0x400>;
 928                                 interrupt-parent = <&gic>;
 929                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 930                         };
 931
 932                         usbhsehci: ehci@4a064c00 {
 933                                 compatible = "ti,ehci-omap";
 934                                 reg = <0x4a064c00 0x400>;
 935                                 interrupt-parent = <&gic>;
 936                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 937                         };
 938                 };
 939
 940                 bandgap: bandgap@4a0021e0 {
 941                         reg = <0x4a0021e0 0xc
 942                                0x4a00232c 0xc
 943                                0x4a002380 0x2c
 944                                0x4a0023C0 0x3c>;
 945                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 946                         compatible = "ti,omap5430-bandgap";
 947
 948                         #thermal-sensor-cells = <1>;
 949                 };
 950
 951                 omap_control_sata: control-phy@4a002374 {
 952                         compatible = "ti,control-phy-pipe3";
 953                         reg = <0x4a002374 0x4>;
 954                         reg-names = "power";
 955                         clocks = <&sys_clkin>;
 956                         clock-names = "sysclk";
 957                 };
 958
 959                 /* OCP2SCP3 */
 960                 ocp2scp@4a090000 {
 961                         compatible = "ti,omap-ocp2scp";
 962                         #address-cells = <1>;
 963                         #size-cells = <1>;
 964                         reg = <0x4a090000 0x20>;
 965                         ranges;
 966                         ti,hwmods = "ocp2scp3";
 967                         sata_phy: phy@4a096000 {
 968                                 compatible = "ti,phy-pipe3-sata";
 969                                 reg = <0x4A096000 0x80>, /* phy_rx */
 970                                       <0x4A096400 0x64>, /* phy_tx */
 971                                       <0x4A096800 0x40>; /* pll_ctrl */
 972                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 973                                 ctrl-module = <&omap_control_sata>;
 974                                 clocks = <&sys_clkin>, <&sata_ref_clk>;
 975                                 clock-names = "sysclk", "refclk";
 976                                 #phy-cells = <0>;
 977                         };
 978                 };
 979
 980                 sata: sata@4a141100 {
 981                         compatible = "snps,dwc-ahci";
 982                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 983                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 984                         phys = <&sata_phy>;
 985                         phy-names = "sata-phy";
 986                         clocks = <&sata_ref_clk>;
 987                         ti,hwmods = "sata";
 988                 };
 989
 990                 dss: dss@58000000 {
 991                         compatible = "ti,omap5-dss";
 992                         reg = <0x58000000 0x80>;
 993                         status = "disabled";
 994                         ti,hwmods = "dss_core";
 995                         clocks = <&dss_dss_clk>;
 996                         clock-names = "fck";
 997                         #address-cells = <1>;
 998                         #size-cells = <1>;
 999                         ranges;
1000
1001                         dispc@58001000 {
1002                                 compatible = "ti,omap5-dispc";
1003                                 reg = <0x58001000 0x1000>;
1004                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1005                                 ti,hwmods = "dss_dispc";
1006                                 clocks = <&dss_dss_clk>;
1007                                 clock-names = "fck";
1008                         };
1009
1010                         rfbi: encoder@58002000  {
1011                                 compatible = "ti,omap5-rfbi";
1012                                 reg = <0x58002000 0x100>;
1013                                 status = "disabled";
1014                                 ti,hwmods = "dss_rfbi";
1015                                 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1016                                 clock-names = "fck", "ick";
1017                         };
1018
1019                         dsi1: encoder@58004000 {
1020                                 compatible = "ti,omap5-dsi";
1021                                 reg = <0x58004000 0x200>,
1022                                       <0x58004200 0x40>,
1023                                       <0x58004300 0x40>;
1024                                 reg-names = "proto", "phy", "pll";
1025                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026                                 status = "disabled";
1027                                 ti,hwmods = "dss_dsi1";
1028                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1029                                 clock-names = "fck", "sys_clk";
1030                         };
1031
1032                         dsi2: encoder@58005000 {
1033                                 compatible = "ti,omap5-dsi";
1034                                 reg = <0x58009000 0x200>,
1035                                       <0x58009200 0x40>,
1036                                       <0x58009300 0x40>;
1037                                 reg-names = "proto", "phy", "pll";
1038                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1039                                 status = "disabled";
1040                                 ti,hwmods = "dss_dsi2";
1041                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1042                                 clock-names = "fck", "sys_clk";
1043                         };
1044
1045                         hdmi: encoder@58060000 {
1046                                 compatible = "ti,omap5-hdmi";
1047                                 reg = <0x58040000 0x200>,
1048                                       <0x58040200 0x80>,
1049                                       <0x58040300 0x80>,
1050                                       <0x58060000 0x19000>;
1051                                 reg-names = "wp", "pll", "phy", "core";
1052                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1053                                 status = "disabled";
1054                                 ti,hwmods = "dss_hdmi";
1055                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1056                                 clock-names = "fck", "sys_clk";
1057                                 dmas = <&sdma 76>;
1058                                 dma-names = "audio_tx";
1059                         };
1060                 };
1061
1062                 abb_mpu: regulator-abb-mpu {
1063                         compatible = "ti,abb-v2";
1064                         regulator-name = "abb_mpu";
1065                         #address-cells = <0>;
1066                         #size-cells = <0>;
1067                         clocks = <&sys_clkin>;
1068                         ti,settling-time = <50>;
1069                         ti,clock-cycles = <16>;
1070
1071                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1072                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1073                         reg-names = "base-address", "int-address",
1074                                     "efuse-address", "ldo-address";
1075                         ti,tranxdone-status-mask = <0x80>;
1076                         /* LDOVBBMPU_MUX_CTRL */
1077                         ti,ldovbb-override-mask = <0x400>;
1078                         /* LDOVBBMPU_VSET_OUT */
1079                         ti,ldovbb-vset-mask = <0x1F>;
1080
1081                         /*
1082                          * NOTE: only FBB mode used but actual vset will
1083                          * determine final biasing
1084                          */
1085                         ti,abb_info = <
1086                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1087                         1060000         0       0x0     0 0x02000000 0x01F00000
1088                         1250000         0       0x4     0 0x02000000 0x01F00000
1089                         >;
1090                 };
1091
1092                 abb_mm: regulator-abb-mm {
1093                         compatible = "ti,abb-v2";
1094                         regulator-name = "abb_mm";
1095                         #address-cells = <0>;
1096                         #size-cells = <0>;
1097                         clocks = <&sys_clkin>;
1098                         ti,settling-time = <50>;
1099                         ti,clock-cycles = <16>;
1100
1101                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1102                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1103                         reg-names = "base-address", "int-address",
1104                                     "efuse-address", "ldo-address";
1105                         ti,tranxdone-status-mask = <0x80000000>;
1106                         /* LDOVBBMM_MUX_CTRL */
1107                         ti,ldovbb-override-mask = <0x400>;
1108                         /* LDOVBBMM_VSET_OUT */
1109                         ti,ldovbb-vset-mask = <0x1F>;
1110
1111                         /*
1112                          * NOTE: only FBB mode used but actual vset will
1113                          * determine final biasing
1114                          */
1115                         ti,abb_info = <
1116                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1117                         1025000         0       0x0     0 0x02000000 0x01F00000
1118                         1120000         0       0x4     0 0x02000000 0x01F00000
1119                         >;
1120                 };
1121         };
1122 };
1123
1124 /include/ "omap54xx-clocks.dtsi"