arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&wakeupgen>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39
  40                         clocks = <&dpll_mpu_ck>;
  41                         clock-names = "cpu";
  42
  43                         clock-latency = <300000>; /* From omap-cpufreq driver */
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@48241000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 reg = <0x48241000 0x1000>,
  58                       <0x48240100 0x0100>;
  59                 interrupt-parent = <&gic>;
  60         };
  61
  62         L2: l2-cache-controller@48242000 {
  63                 compatible = "arm,pl310-cache";
  64                 reg = <0x48242000 0x1000>;
  65                 cache-unified;
  66                 cache-level = <2>;
  67         };
  68
  69         local-timer@48240600 {
  70                 compatible = "arm,cortex-a9-twd-timer";
  71                 clocks = <&mpu_periphclk>;
  72                 reg = <0x48240600 0x20>;
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  74                 interrupt-parent = <&gic>;
  75         };
  76
  77         wakeupgen: interrupt-controller@48281000 {
  78                 compatible = "ti,omap4-wugen-mpu";
  79                 interrupt-controller;
  80                 #interrupt-cells = <3>;
  81                 reg = <0x48281000 0x1000>;
  82                 interrupt-parent = <&gic>;
  83         };
  84
  85         /*
  86          * The soc node represents the soc top level view. It is used for IPs
  87          * that are not memory mapped in the MPU view or for the MPU itself.
  88          */
  89         soc {
  90                 compatible = "ti,omap-infra";
  91                 mpu {
  92                         compatible = "ti,omap4-mpu";
  93                         ti,hwmods = "mpu";
  94                         sram = <&ocmcram>;
  95                 };
  96
  97                 dsp {
  98                         compatible = "ti,omap3-c64";
  99                         ti,hwmods = "dsp";
 100                 };
 101
 102                 iva {
 103                         compatible = "ti,ivahd";
 104                         ti,hwmods = "iva";
 105                 };
 106         };
 107
 108         /*
 109          * XXX: Use a flat representation of the OMAP4 interconnect.
 110          * The real OMAP interconnect network is quite complex.
 111          * Since it will not bring real advantage to represent that in DT for
 112          * the moment, just use a fake OCP bus entry to represent the whole bus
 113          * hierarchy.
 114          */
 115         ocp {
 116                 compatible = "ti,omap4-l3-noc", "simple-bus";
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges;
 120                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 121                 reg = <0x44000000 0x1000>,
 122                       <0x44800000 0x2000>,
 123                       <0x45000000 0x1000>;
 124                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 125                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 126
 127                 cm1: cm1@4a004000 {
 128                         compatible = "ti,omap4-cm1";
 129                         reg = <0x4a004000 0x2000>;
 130
 131                         cm1_clocks: clocks {
 132                                 #address-cells = <1>;
 133                                 #size-cells = <0>;
 134                         };
 135
 136                         cm1_clockdomains: clockdomains {
 137                         };
 138                 };
 139
 140                 prm: prm@4a306000 {
 141                         compatible = "ti,omap4-prm";
 142                         reg = <0x4a306000 0x3000>;
 143                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 144
 145                         prm_clocks: clocks {
 146                                 #address-cells = <1>;
 147                                 #size-cells = <0>;
 148                         };
 149
 150                         prm_clockdomains: clockdomains {
 151                         };
 152                 };
 153
 154                 cm2: cm2@4a008000 {
 155                         compatible = "ti,omap4-cm2";
 156                         reg = <0x4a008000 0x3000>;
 157
 158                         cm2_clocks: clocks {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                         };
 162
 163                         cm2_clockdomains: clockdomains {
 164                         };
 165                 };
 166
 167                 scrm: scrm@4a30a000 {
 168                         compatible = "ti,omap4-scrm";
 169                         reg = <0x4a30a000 0x2000>;
 170
 171                         scrm_clocks: clocks {
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174                         };
 175
 176                         scrm_clockdomains: clockdomains {
 177                         };
 178                 };
 179
 180                 counter32k: counter@4a304000 {
 181                         compatible = "ti,omap-counter32k";
 182                         reg = <0x4a304000 0x20>;
 183                         ti,hwmods = "counter_32k";
 184                 };
 185
 186                 omap4_pmx_core: pinmux@4a100040 {
 187                         compatible = "ti,omap4-padconf", "pinctrl-single";
 188                         reg = <0x4a100040 0x0196>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         #interrupt-cells = <1>;
 192                         interrupt-controller;
 193                         pinctrl-single,register-width = <16>;
 194                         pinctrl-single,function-mask = <0x7fff>;
 195                 };
 196                 omap4_pmx_wkup: pinmux@4a31e040 {
 197                         compatible = "ti,omap4-padconf", "pinctrl-single";
 198                         reg = <0x4a31e040 0x0038>;
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         #interrupt-cells = <1>;
 202                         interrupt-controller;
 203                         pinctrl-single,register-width = <16>;
 204                         pinctrl-single,function-mask = <0x7fff>;
 205                 };
 206
 207                 omap4_padconf_global: tisyscon@4a1005a0 {
 208                         compatible = "syscon";
 209                         reg = <0x4a1005a0 0x170>;
 210                 };
 211
 212                 pbias_regulator: pbias_regulator {
 213                         compatible = "ti,pbias-omap";
 214                         reg = <0x60 0x4>;
 215                         syscon = <&omap4_padconf_global>;
 216                         pbias_mmc_reg: pbias_mmc_omap4 {
 217                                 regulator-name = "pbias_mmc_omap4";
 218                                 regulator-min-microvolt = <1800000>;
 219                                 regulator-max-microvolt = <3000000>;
 220                         };
 221                 };
 222
 223                 ocmcram: ocmcram@40304000 {
 224                         compatible = "mmio-sram";
 225                         reg = <0x40304000 0xa000>; /* 40k */
 226                 };
 227
 228                 sdma: dma-controller@4a056000 {
 229                         compatible = "ti,omap4430-sdma";
 230                         reg = <0x4a056000 0x1000>;
 231                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 235                         #dma-cells = <1>;
 236                         #dma-channels = <32>;
 237                         #dma-requests = <127>;
 238                 };
 239
 240                 gpio1: gpio@4a310000 {
 241                         compatible = "ti,omap4-gpio";
 242                         reg = <0x4a310000 0x200>;
 243                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 244                         ti,hwmods = "gpio1";
 245                         ti,gpio-always-on;
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248                         interrupt-controller;
 249                         #interrupt-cells = <2>;
 250                 };
 251
 252                 gpio2: gpio@48055000 {
 253                         compatible = "ti,omap4-gpio";
 254                         reg = <0x48055000 0x200>;
 255                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 256                         ti,hwmods = "gpio2";
 257                         gpio-controller;
 258                         #gpio-cells = <2>;
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 gpio3: gpio@48057000 {
 264                         compatible = "ti,omap4-gpio";
 265                         reg = <0x48057000 0x200>;
 266                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 267                         ti,hwmods = "gpio3";
 268                         gpio-controller;
 269                         #gpio-cells = <2>;
 270                         interrupt-controller;
 271                         #interrupt-cells = <2>;
 272                 };
 273
 274                 gpio4: gpio@48059000 {
 275                         compatible = "ti,omap4-gpio";
 276                         reg = <0x48059000 0x200>;
 277                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 278                         ti,hwmods = "gpio4";
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         interrupt-controller;
 282                         #interrupt-cells = <2>;
 283                 };
 284
 285                 gpio5: gpio@4805b000 {
 286                         compatible = "ti,omap4-gpio";
 287                         reg = <0x4805b000 0x200>;
 288                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 289                         ti,hwmods = "gpio5";
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpio6: gpio@4805d000 {
 297                         compatible = "ti,omap4-gpio";
 298                         reg = <0x4805d000 0x200>;
 299                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 300                         ti,hwmods = "gpio6";
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                         interrupt-controller;
 304                         #interrupt-cells = <2>;
 305                 };
 306
 307                 gpmc: gpmc@50000000 {
 308                         compatible = "ti,omap4430-gpmc";
 309                         reg = <0x50000000 0x1000>;
 310                         #address-cells = <2>;
 311                         #size-cells = <1>;
 312                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 313                         gpmc,num-cs = <8>;
 314                         gpmc,num-waitpins = <4>;
 315                         ti,hwmods = "gpmc";
 316                         ti,no-idle-on-init;
 317                         clocks = <&l3_div_ck>;
 318                         clock-names = "fck";
 319                 };
 320
 321                 uart1: serial@4806a000 {
 322                         compatible = "ti,omap4-uart";
 323                         reg = <0x4806a000 0x100>;
 324                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 325                         ti,hwmods = "uart1";
 326                         clock-frequency = <48000000>;
 327                 };
 328
 329                 uart2: serial@4806c000 {
 330                         compatible = "ti,omap4-uart";
 331                         reg = <0x4806c000 0x100>;
 332                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 333                         ti,hwmods = "uart2";
 334                         clock-frequency = <48000000>;
 335                 };
 336
 337                 uart3: serial@48020000 {
 338                         compatible = "ti,omap4-uart";
 339                         reg = <0x48020000 0x100>;
 340                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 341                         ti,hwmods = "uart3";
 342                         clock-frequency = <48000000>;
 343                 };
 344
 345                 uart4: serial@4806e000 {
 346                         compatible = "ti,omap4-uart";
 347                         reg = <0x4806e000 0x100>;
 348                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 349                         ti,hwmods = "uart4";
 350                         clock-frequency = <48000000>;
 351                 };
 352
 353                 hwspinlock: spinlock@4a0f6000 {
 354                         compatible = "ti,omap4-hwspinlock";
 355                         reg = <0x4a0f6000 0x1000>;
 356                         ti,hwmods = "spinlock";
 357                         #hwlock-cells = <1>;
 358                 };
 359
 360                 i2c1: i2c@48070000 {
 361                         compatible = "ti,omap4-i2c";
 362                         reg = <0x48070000 0x100>;
 363                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         ti,hwmods = "i2c1";
 367                 };
 368
 369                 i2c2: i2c@48072000 {
 370                         compatible = "ti,omap4-i2c";
 371                         reg = <0x48072000 0x100>;
 372                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         ti,hwmods = "i2c2";
 376                 };
 377
 378                 i2c3: i2c@48060000 {
 379                         compatible = "ti,omap4-i2c";
 380                         reg = <0x48060000 0x100>;
 381                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         ti,hwmods = "i2c3";
 385                 };
 386
 387                 i2c4: i2c@48350000 {
 388                         compatible = "ti,omap4-i2c";
 389                         reg = <0x48350000 0x100>;
 390                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         ti,hwmods = "i2c4";
 394                 };
 395
 396                 mcspi1: spi@48098000 {
 397                         compatible = "ti,omap4-mcspi";
 398                         reg = <0x48098000 0x200>;
 399                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         ti,hwmods = "mcspi1";
 403                         ti,spi-num-cs = <4>;
 404                         dmas = <&sdma 35>,
 405                                <&sdma 36>,
 406                                <&sdma 37>,
 407                                <&sdma 38>,
 408                                <&sdma 39>,
 409                                <&sdma 40>,
 410                                <&sdma 41>,
 411                                <&sdma 42>;
 412                         dma-names = "tx0", "rx0", "tx1", "rx1",
 413                                     "tx2", "rx2", "tx3", "rx3";
 414                 };
 415
 416                 mcspi2: spi@4809a000 {
 417                         compatible = "ti,omap4-mcspi";
 418                         reg = <0x4809a000 0x200>;
 419                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         ti,hwmods = "mcspi2";
 423                         ti,spi-num-cs = <2>;
 424                         dmas = <&sdma 43>,
 425                                <&sdma 44>,
 426                                <&sdma 45>,
 427                                <&sdma 46>;
 428                         dma-names = "tx0", "rx0", "tx1", "rx1";
 429                 };
 430
 431                 mcspi3: spi@480b8000 {
 432                         compatible = "ti,omap4-mcspi";
 433                         reg = <0x480b8000 0x200>;
 434                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         ti,hwmods = "mcspi3";
 438                         ti,spi-num-cs = <2>;
 439                         dmas = <&sdma 15>, <&sdma 16>;
 440                         dma-names = "tx0", "rx0";
 441                 };
 442
 443                 mcspi4: spi@480ba000 {
 444                         compatible = "ti,omap4-mcspi";
 445                         reg = <0x480ba000 0x200>;
 446                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         ti,hwmods = "mcspi4";
 450                         ti,spi-num-cs = <1>;
 451                         dmas = <&sdma 70>, <&sdma 71>;
 452                         dma-names = "tx0", "rx0";
 453                 };
 454
 455                 mmc1: mmc@4809c000 {
 456                         compatible = "ti,omap4-hsmmc";
 457                         reg = <0x4809c000 0x400>;
 458                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 459                         ti,hwmods = "mmc1";
 460                         ti,dual-volt;
 461                         ti,needs-special-reset;
 462                         dmas = <&sdma 61>, <&sdma 62>;
 463                         dma-names = "tx", "rx";
 464                         pbias-supply = <&pbias_mmc_reg>;
 465                 };
 466
 467                 mmc2: mmc@480b4000 {
 468                         compatible = "ti,omap4-hsmmc";
 469                         reg = <0x480b4000 0x400>;
 470                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 471                         ti,hwmods = "mmc2";
 472                         ti,needs-special-reset;
 473                         dmas = <&sdma 47>, <&sdma 48>;
 474                         dma-names = "tx", "rx";
 475                 };
 476
 477                 mmc3: mmc@480ad000 {
 478                         compatible = "ti,omap4-hsmmc";
 479                         reg = <0x480ad000 0x400>;
 480                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 481                         ti,hwmods = "mmc3";
 482                         ti,needs-special-reset;
 483                         dmas = <&sdma 77>, <&sdma 78>;
 484                         dma-names = "tx", "rx";
 485                 };
 486
 487                 mmc4: mmc@480d1000 {
 488                         compatible = "ti,omap4-hsmmc";
 489                         reg = <0x480d1000 0x400>;
 490                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 491                         ti,hwmods = "mmc4";
 492                         ti,needs-special-reset;
 493                         dmas = <&sdma 57>, <&sdma 58>;
 494                         dma-names = "tx", "rx";
 495                 };
 496
 497                 mmc5: mmc@480d5000 {
 498                         compatible = "ti,omap4-hsmmc";
 499                         reg = <0x480d5000 0x400>;
 500                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 501                         ti,hwmods = "mmc5";
 502                         ti,needs-special-reset;
 503                         dmas = <&sdma 59>, <&sdma 60>;
 504                         dma-names = "tx", "rx";
 505                 };
 506
 507                 mmu_dsp: mmu@4a066000 {
 508                         compatible = "ti,omap4-iommu";
 509                         reg = <0x4a066000 0x100>;
 510                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 511                         ti,hwmods = "mmu_dsp";
 512                 };
 513
 514                 mmu_ipu: mmu@55082000 {
 515                         compatible = "ti,omap4-iommu";
 516                         reg = <0x55082000 0x100>;
 517                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 518                         ti,hwmods = "mmu_ipu";
 519                         ti,iommu-bus-err-back;
 520                 };
 521
 522                 wdt2: wdt@4a314000 {
 523                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 524                         reg = <0x4a314000 0x80>;
 525                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 526                         ti,hwmods = "wd_timer2";
 527                 };
 528
 529                 mcpdm: mcpdm@40132000 {
 530                         compatible = "ti,omap4-mcpdm";
 531                         reg = <0x40132000 0x7f>, /* MPU private access */
 532                               <0x49032000 0x7f>; /* L3 Interconnect */
 533                         reg-names = "mpu", "dma";
 534                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 535                         ti,hwmods = "mcpdm";
 536                         dmas = <&sdma 65>,
 537                                <&sdma 66>;
 538                         dma-names = "up_link", "dn_link";
 539                         status = "disabled";
 540                 };
 541
 542                 dmic: dmic@4012e000 {
 543                         compatible = "ti,omap4-dmic";
 544                         reg = <0x4012e000 0x7f>, /* MPU private access */
 545                               <0x4902e000 0x7f>; /* L3 Interconnect */
 546                         reg-names = "mpu", "dma";
 547                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "dmic";
 549                         dmas = <&sdma 67>;
 550                         dma-names = "up_link";
 551                         status = "disabled";
 552                 };
 553
 554                 mcbsp1: mcbsp@40122000 {
 555                         compatible = "ti,omap4-mcbsp";
 556                         reg = <0x40122000 0xff>, /* MPU private access */
 557                               <0x49022000 0xff>; /* L3 Interconnect */
 558                         reg-names = "mpu", "dma";
 559                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 560                         interrupt-names = "common";
 561                         ti,buffer-size = <128>;
 562                         ti,hwmods = "mcbsp1";
 563                         dmas = <&sdma 33>,
 564                                <&sdma 34>;
 565                         dma-names = "tx", "rx";
 566                         status = "disabled";
 567                 };
 568
 569                 mcbsp2: mcbsp@40124000 {
 570                         compatible = "ti,omap4-mcbsp";
 571                         reg = <0x40124000 0xff>, /* MPU private access */
 572                               <0x49024000 0xff>; /* L3 Interconnect */
 573                         reg-names = "mpu", "dma";
 574                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 575                         interrupt-names = "common";
 576                         ti,buffer-size = <128>;
 577                         ti,hwmods = "mcbsp2";
 578                         dmas = <&sdma 17>,
 579                                <&sdma 18>;
 580                         dma-names = "tx", "rx";
 581                         status = "disabled";
 582                 };
 583
 584                 mcbsp3: mcbsp@40126000 {
 585                         compatible = "ti,omap4-mcbsp";
 586                         reg = <0x40126000 0xff>, /* MPU private access */
 587                               <0x49026000 0xff>; /* L3 Interconnect */
 588                         reg-names = "mpu", "dma";
 589                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 590                         interrupt-names = "common";
 591                         ti,buffer-size = <128>;
 592                         ti,hwmods = "mcbsp3";
 593                         dmas = <&sdma 19>,
 594                                <&sdma 20>;
 595                         dma-names = "tx", "rx";
 596                         status = "disabled";
 597                 };
 598
 599                 mcbsp4: mcbsp@48096000 {
 600                         compatible = "ti,omap4-mcbsp";
 601                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 602                         reg-names = "mpu";
 603                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 604                         interrupt-names = "common";
 605                         ti,buffer-size = <128>;
 606                         ti,hwmods = "mcbsp4";
 607                         dmas = <&sdma 31>,
 608                                <&sdma 32>;
 609                         dma-names = "tx", "rx";
 610                         status = "disabled";
 611                 };
 612
 613                 keypad: keypad@4a31c000 {
 614                         compatible = "ti,omap4-keypad";
 615                         reg = <0x4a31c000 0x80>;
 616                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 617                         reg-names = "mpu";
 618                         ti,hwmods = "kbd";
 619                 };
 620
 621                 dmm@4e000000 {
 622                         compatible = "ti,omap4-dmm";
 623                         reg = <0x4e000000 0x800>;
 624                         interrupts = <0 113 0x4>;
 625                         ti,hwmods = "dmm";
 626                 };
 627
 628                 emif1: emif@4c000000 {
 629                         compatible = "ti,emif-4d";
 630                         reg = <0x4c000000 0x100>;
 631                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 632                         ti,hwmods = "emif1";
 633                         ti,no-idle-on-init;
 634                         phy-type = <1>;
 635                         hw-caps-read-idle-ctrl;
 636                         hw-caps-ll-interface;
 637                         hw-caps-temp-alert;
 638                 };
 639
 640                 emif2: emif@4d000000 {
 641                         compatible = "ti,emif-4d";
 642                         reg = <0x4d000000 0x100>;
 643                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 644                         ti,hwmods = "emif2";
 645                         ti,no-idle-on-init;
 646                         phy-type = <1>;
 647                         hw-caps-read-idle-ctrl;
 648                         hw-caps-ll-interface;
 649                         hw-caps-temp-alert;
 650                 };
 651
 652                 ocp2scp@4a0ad000 {
 653                         compatible = "ti,omap-ocp2scp";
 654                         reg = <0x4a0ad000 0x1f>;
 655                         #address-cells = <1>;
 656                         #size-cells = <1>;
 657                         ranges;
 658                         ti,hwmods = "ocp2scp_usb_phy";
 659                         usb2_phy: usb2phy@4a0ad080 {
 660                                 compatible = "ti,omap-usb2";
 661                                 reg = <0x4a0ad080 0x58>;
 662                                 ctrl-module = <&omap_control_usb2phy>;
 663                                 clocks = <&usb_phy_cm_clk32k>;
 664                                 clock-names = "wkupclk";
 665                                 #phy-cells = <0>;
 666                         };
 667                 };
 668
 669                 mailbox: mailbox@4a0f4000 {
 670                         compatible = "ti,omap4-mailbox";
 671                         reg = <0x4a0f4000 0x200>;
 672                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 673                         ti,hwmods = "mailbox";
 674                         #mbox-cells = <1>;
 675                         ti,mbox-num-users = <3>;
 676                         ti,mbox-num-fifos = <8>;
 677                         mbox_ipu: mbox_ipu {
 678                                 ti,mbox-tx = <0 0 0>;
 679                                 ti,mbox-rx = <1 0 0>;
 680                         };
 681                         mbox_dsp: mbox_dsp {
 682                                 ti,mbox-tx = <3 0 0>;
 683                                 ti,mbox-rx = <2 0 0>;
 684                         };
 685                 };
 686
 687                 timer1: timer@4a318000 {
 688                         compatible = "ti,omap3430-timer";
 689                         reg = <0x4a318000 0x80>;
 690                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 691                         ti,hwmods = "timer1";
 692                         ti,timer-alwon;
 693                 };
 694
 695                 timer2: timer@48032000 {
 696                         compatible = "ti,omap3430-timer";
 697                         reg = <0x48032000 0x80>;
 698                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 699                         ti,hwmods = "timer2";
 700                 };
 701
 702                 timer3: timer@48034000 {
 703                         compatible = "ti,omap4430-timer";
 704                         reg = <0x48034000 0x80>;
 705                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 706                         ti,hwmods = "timer3";
 707                 };
 708
 709                 timer4: timer@48036000 {
 710                         compatible = "ti,omap4430-timer";
 711                         reg = <0x48036000 0x80>;
 712                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 713                         ti,hwmods = "timer4";
 714                 };
 715
 716                 timer5: timer@40138000 {
 717                         compatible = "ti,omap4430-timer";
 718                         reg = <0x40138000 0x80>,
 719                               <0x49038000 0x80>;
 720                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 721                         ti,hwmods = "timer5";
 722                         ti,timer-dsp;
 723                 };
 724
 725                 timer6: timer@4013a000 {
 726                         compatible = "ti,omap4430-timer";
 727                         reg = <0x4013a000 0x80>,
 728                               <0x4903a000 0x80>;
 729                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 730                         ti,hwmods = "timer6";
 731                         ti,timer-dsp;
 732                 };
 733
 734                 timer7: timer@4013c000 {
 735                         compatible = "ti,omap4430-timer";
 736                         reg = <0x4013c000 0x80>,
 737                               <0x4903c000 0x80>;
 738                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 739                         ti,hwmods = "timer7";
 740                         ti,timer-dsp;
 741                 };
 742
 743                 timer8: timer@4013e000 {
 744                         compatible = "ti,omap4430-timer";
 745                         reg = <0x4013e000 0x80>,
 746                               <0x4903e000 0x80>;
 747                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 748                         ti,hwmods = "timer8";
 749                         ti,timer-pwm;
 750                         ti,timer-dsp;
 751                 };
 752
 753                 timer9: timer@4803e000 {
 754                         compatible = "ti,omap4430-timer";
 755                         reg = <0x4803e000 0x80>;
 756                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 757                         ti,hwmods = "timer9";
 758                         ti,timer-pwm;
 759                 };
 760
 761                 timer10: timer@48086000 {
 762                         compatible = "ti,omap3430-timer";
 763                         reg = <0x48086000 0x80>;
 764                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 765                         ti,hwmods = "timer10";
 766                         ti,timer-pwm;
 767                 };
 768
 769                 timer11: timer@48088000 {
 770                         compatible = "ti,omap4430-timer";
 771                         reg = <0x48088000 0x80>;
 772                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 773                         ti,hwmods = "timer11";
 774                         ti,timer-pwm;
 775                 };
 776
 777                 usbhstll: usbhstll@4a062000 {
 778                         compatible = "ti,usbhs-tll";
 779                         reg = <0x4a062000 0x1000>;
 780                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 781                         ti,hwmods = "usb_tll_hs";
 782                 };
 783
 784                 usbhshost: usbhshost@4a064000 {
 785                         compatible = "ti,usbhs-host";
 786                         reg = <0x4a064000 0x800>;
 787                         ti,hwmods = "usb_host_hs";
 788                         #address-cells = <1>;
 789                         #size-cells = <1>;
 790                         ranges;
 791                         clocks = <&init_60m_fclk>,
 792                                  <&xclk60mhsp1_ck>,
 793                                  <&xclk60mhsp2_ck>;
 794                         clock-names = "refclk_60m_int",
 795                                       "refclk_60m_ext_p1",
 796                                       "refclk_60m_ext_p2";
 797
 798                         usbhsohci: ohci@4a064800 {
 799                                 compatible = "ti,ohci-omap3";
 800                                 reg = <0x4a064800 0x400>;
 801                                 interrupt-parent = <&gic>;
 802                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 803                         };
 804
 805                         usbhsehci: ehci@4a064c00 {
 806                                 compatible = "ti,ehci-omap";
 807                                 reg = <0x4a064c00 0x400>;
 808                                 interrupt-parent = <&gic>;
 809                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 810                         };
 811                 };
 812
 813                 omap_control_usb2phy: control-phy@4a002300 {
 814                         compatible = "ti,control-phy-usb2";
 815                         reg = <0x4a002300 0x4>;
 816                         reg-names = "power";
 817                 };
 818
 819                 omap_control_usbotg: control-phy@4a00233c {
 820                         compatible = "ti,control-phy-otghs";
 821                         reg = <0x4a00233c 0x4>;
 822                         reg-names = "otghs_control";
 823                 };
 824
 825                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 826                         compatible = "ti,omap4-musb";
 827                         reg = <0x4a0ab000 0x7ff>;
 828                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 829                         interrupt-names = "mc", "dma";
 830                         ti,hwmods = "usb_otg_hs";
 831                         usb-phy = <&usb2_phy>;
 832                         phys = <&usb2_phy>;
 833                         phy-names = "usb2-phy";
 834                         multipoint = <1>;
 835                         num-eps = <16>;
 836                         ram-bits = <12>;
 837                         ctrl-module = <&omap_control_usbotg>;
 838                 };
 839
 840                 aes: aes@4b501000 {
 841                         compatible = "ti,omap4-aes";
 842                         ti,hwmods = "aes";
 843                         reg = <0x4b501000 0xa0>;
 844                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 845                         dmas = <&sdma 111>, <&sdma 110>;
 846                         dma-names = "tx", "rx";
 847                 };
 848
 849                 des: des@480a5000 {
 850                         compatible = "ti,omap4-des";
 851                         ti,hwmods = "des";
 852                         reg = <0x480a5000 0xa0>;
 853                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 854                         dmas = <&sdma 117>, <&sdma 116>;
 855                         dma-names = "tx", "rx";
 856                 };
 857
 858                 abb_mpu: regulator-abb-mpu {
 859                         compatible = "ti,abb-v2";
 860                         regulator-name = "abb_mpu";
 861                         #address-cells = <0>;
 862                         #size-cells = <0>;
 863                         ti,tranxdone-status-mask = <0x80>;
 864                         clocks = <&sys_clkin_ck>;
 865                         ti,settling-time = <50>;
 866                         ti,clock-cycles = <16>;
 867
 868                         status = "disabled";
 869                 };
 870
 871                 abb_iva: regulator-abb-iva {
 872                         compatible = "ti,abb-v2";
 873                         regulator-name = "abb_iva";
 874                         #address-cells = <0>;
 875                         #size-cells = <0>;
 876                         ti,tranxdone-status-mask = <0x80000000>;
 877                         clocks = <&sys_clkin_ck>;
 878                         ti,settling-time = <50>;
 879                         ti,clock-cycles = <16>;
 880
 881                         status = "disabled";
 882                 };
 883
 884                 dss: dss@58000000 {
 885                         compatible = "ti,omap4-dss";
 886                         reg = <0x58000000 0x80>;
 887                         status = "disabled";
 888                         ti,hwmods = "dss_core";
 889                         clocks = <&dss_dss_clk>;
 890                         clock-names = "fck";
 891                         #address-cells = <1>;
 892                         #size-cells = <1>;
 893                         ranges;
 894
 895                         dispc@58001000 {
 896                                 compatible = "ti,omap4-dispc";
 897                                 reg = <0x58001000 0x1000>;
 898                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 899                                 ti,hwmods = "dss_dispc";
 900                                 clocks = <&dss_dss_clk>;
 901                                 clock-names = "fck";
 902                         };
 903
 904                         rfbi: encoder@58002000  {
 905                                 compatible = "ti,omap4-rfbi";
 906                                 reg = <0x58002000 0x1000>;
 907                                 status = "disabled";
 908                                 ti,hwmods = "dss_rfbi";
 909                                 clocks = <&dss_dss_clk>, <&l3_div_ck>;
 910                                 clock-names = "fck", "ick";
 911                         };
 912
 913                         venc: encoder@58003000 {
 914                                 compatible = "ti,omap4-venc";
 915                                 reg = <0x58003000 0x1000>;
 916                                 status = "disabled";
 917                                 ti,hwmods = "dss_venc";
 918                                 clocks = <&dss_tv_clk>;
 919                                 clock-names = "fck";
 920                         };
 921
 922                         dsi1: encoder@58004000 {
 923                                 compatible = "ti,omap4-dsi";
 924                                 reg = <0x58004000 0x200>,
 925                                       <0x58004200 0x40>,
 926                                       <0x58004300 0x20>;
 927                                 reg-names = "proto", "phy", "pll";
 928                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 929                                 status = "disabled";
 930                                 ti,hwmods = "dss_dsi1";
 931                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 932                                 clock-names = "fck", "sys_clk";
 933                         };
 934
 935                         dsi2: encoder@58005000 {
 936                                 compatible = "ti,omap4-dsi";
 937                                 reg = <0x58005000 0x200>,
 938                                       <0x58005200 0x40>,
 939                                       <0x58005300 0x20>;
 940                                 reg-names = "proto", "phy", "pll";
 941                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 942                                 status = "disabled";
 943                                 ti,hwmods = "dss_dsi2";
 944                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 945                                 clock-names = "fck", "sys_clk";
 946                         };
 947
 948                         hdmi: encoder@58006000 {
 949                                 compatible = "ti,omap4-hdmi";
 950                                 reg = <0x58006000 0x200>,
 951                                       <0x58006200 0x100>,
 952                                       <0x58006300 0x100>,
 953                                       <0x58006400 0x1000>;
 954                                 reg-names = "wp", "pll", "phy", "core";
 955                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 956                                 status = "disabled";
 957                                 ti,hwmods = "dss_hdmi";
 958                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
 959                                 clock-names = "fck", "sys_clk";
 960                                 dmas = <&sdma 76>;
 961                                 dma-names = "audio_tx";
 962                         };
 963                 };
 964         };
 965 };
 966
 967 /include/ "omap44xx-clocks.dtsi"