arch/arm/boot/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 / {
  14         compatible = "ti,omap3430", "ti,omap3";
  15
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21         };
  22
  23         cpus {
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a8";
  26                 };
  27         };
  28
  29         /*
  30          * The soc node represents the soc top level view. It is uses for IPs
  31          * that are not memory mapped in the MPU view or for the MPU itself.
  32          */
  33         soc {
  34                 compatible = "ti,omap-infra";
  35                 mpu {
  36                         compatible = "ti,omap3-mpu";
  37                         ti,hwmods = "mpu";
  38                 };
  39
  40                 iva {
  41                         compatible = "ti,iva2.2";
  42                         ti,hwmods = "iva";
  43
  44                         dsp {
  45                                 compatible = "ti,omap3-c64";
  46                         };
  47                 };
  48         };
  49
  50         /*
  51          * XXX: Use a flat representation of the OMAP3 interconnect.
  52          * The real OMAP interconnect network is quite complex.
  53          * Since that will not bring real advantage to represent that in DT for
  54          * the moment, just use a fake OCP bus entry to represent the whole bus
  55          * hierarchy.
  56          */
  57         ocp {
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62                 ti,hwmods = "l3_main";
  63
  64                 intc: interrupt-controller@1 {
  65                         compatible = "ti,omap3-intc";
  66                         interrupt-controller;
  67                         #interrupt-cells = <1>;
  68                 };
  69
  70                 uart1: serial@0x4806a000 {
  71                         compatible = "ti,omap3-uart";
  72                         ti,hwmods = "uart1";
  73                         clock-frequency = <48000000>;
  74                 };
  75
  76                 uart2: serial@0x4806c000 {
  77                         compatible = "ti,omap3-uart";
  78                         ti,hwmods = "uart2";
  79                         clock-frequency = <48000000>;
  80                 };
  81
  82                 uart3: serial@0x49020000 {
  83                         compatible = "ti,omap3-uart";
  84                         ti,hwmods = "uart3";
  85                         clock-frequency = <48000000>;
  86                 };
  87
  88                 uart4: serial@0x49042000 {
  89                         compatible = "ti,omap3-uart";
  90                         ti,hwmods = "uart4";
  91                         clock-frequency = <48000000>;
  92                 };
  93         };
  94 };