1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
18 * The decompressor and also some bootloaders rely on a
19 * pre-existing /chosen node to be available to insert the
20 * command line and merge other ATAGS info.
59 entry-method = "psci";
61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x0010000>;
65 entry-latency-us = <100>;
66 exit-latency-us = <50>;
67 min-residency-us = <1000>;
72 compatible = "arm,cortex-a7";
75 clock-frequency = <792000000>;
76 clock-latency = <61036>; /* two CLK32 periods */
77 clocks = <&clks IMX7D_CLK_ARM>;
78 cpu-idle-states = <&cpu_sleep_wait>;
79 operating-points-v2 = <&cpu0_opp_table>;
81 nvmem-cells = <&fuse_grade>;
82 nvmem-cell-names = "speed_grade";
86 cpu0_opp_table: opp-table {
87 compatible = "operating-points-v2";
91 opp-hz = /bits/ 64 <792000000>;
92 opp-microvolt = <1000000>;
93 clock-latency-ns = <150000>;
94 opp-supported-hw = <0xf>, <0xf>;
99 compatible = "fixed-clock";
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
106 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
112 usbphynop1: usbphynop1 {
113 compatible = "usb-nop-xceiv";
114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
115 clock-names = "main_clk";
119 usbphynop3: usbphynop3 {
120 compatible = "usb-nop-xceiv";
121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
122 clock-names = "main_clk";
123 power-domains = <&pgc_hsic_phy>;
128 compatible = "arm,cortex-a7-pmu";
129 interrupt-parent = <&gpc>;
130 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-affinity = <&cpu0>;
136 * non-configurable replicators don't show up on the
137 * AMBA bus. As such no need to add "arm,primecell"
139 compatible = "arm,coresight-static-replicator";
142 #address-cells = <1>;
144 /* replicator output ports */
147 replicator_out_port0: endpoint {
148 remote-endpoint = <&tpiu_in_port>;
154 replicator_out_port1: endpoint {
155 remote-endpoint = <&etr_in_port>;
162 replicator_in_port0: endpoint {
163 remote-endpoint = <&etf_out_port>;
170 compatible = "arm,armv7-timer";
171 arm,cpu-registers-not-fw-configured;
172 interrupt-parent = <&intc>;
173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
180 #address-cells = <1>;
182 compatible = "simple-bus";
183 interrupt-parent = <&gpc>;
187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
188 reg = <0x30041000 0x1000>;
189 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
190 clock-names = "apb_pclk";
192 ca_funnel_in_ports: in-ports {
193 #address-cells = <1>;
198 ca_funnel_in_port0: endpoint {
199 remote-endpoint = <&etm0_out_port>;
203 /* the other input ports are not connect to anything */
208 ca_funnel_out_port0: endpoint {
209 remote-endpoint = <&hugo_funnel_in_port0>;
217 compatible = "arm,coresight-etm3x", "arm,primecell";
218 reg = <0x3007c000 0x1000>;
220 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
221 clock-names = "apb_pclk";
225 etm0_out_port: endpoint {
226 remote-endpoint = <&ca_funnel_in_port0>;
233 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
234 reg = <0x30083000 0x1000>;
235 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
236 clock-names = "apb_pclk";
239 #address-cells = <1>;
244 hugo_funnel_in_port0: endpoint {
245 remote-endpoint = <&ca_funnel_out_port0>;
251 hugo_funnel_in_port1: endpoint {
255 /* the other input ports are not connect to anything */
260 hugo_funnel_out_port0: endpoint {
261 remote-endpoint = <&etf_in_port>;
268 compatible = "arm,coresight-tmc", "arm,primecell";
269 reg = <0x30084000 0x1000>;
270 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
271 clock-names = "apb_pclk";
275 etf_in_port: endpoint {
276 remote-endpoint = <&hugo_funnel_out_port0>;
283 etf_out_port: endpoint {
284 remote-endpoint = <&replicator_in_port0>;
291 compatible = "arm,coresight-tmc", "arm,primecell";
292 reg = <0x30086000 0x1000>;
293 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
294 clock-names = "apb_pclk";
298 etr_in_port: endpoint {
299 remote-endpoint = <&replicator_out_port1>;
306 compatible = "arm,coresight-tpiu", "arm,primecell";
307 reg = <0x30087000 0x1000>;
308 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
309 clock-names = "apb_pclk";
313 tpiu_in_port: endpoint {
314 remote-endpoint = <&replicator_out_port0>;
320 intc: interrupt-controller@31001000 {
321 compatible = "arm,cortex-a7-gic";
322 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
323 #interrupt-cells = <3>;
324 interrupt-controller;
325 interrupt-parent = <&intc>;
326 reg = <0x31001000 0x1000>,
332 aips1: bus@30000000 {
333 compatible = "fsl,aips-bus", "simple-bus";
334 #address-cells = <1>;
336 reg = <0x30000000 0x400000>;
339 gpio1: gpio@30200000 {
340 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
341 reg = <0x30200000 0x10000>;
342 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
343 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
351 gpio2: gpio@30210000 {
352 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
353 reg = <0x30210000 0x10000>;
354 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 gpio-ranges = <&iomuxc 0 13 32>;
363 gpio3: gpio@30220000 {
364 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
365 reg = <0x30220000 0x10000>;
366 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 gpio-ranges = <&iomuxc 0 45 29>;
375 gpio4: gpio@30230000 {
376 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
377 reg = <0x30230000 0x10000>;
378 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 gpio-ranges = <&iomuxc 0 74 24>;
387 gpio5: gpio@30240000 {
388 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
389 reg = <0x30240000 0x10000>;
390 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 gpio-ranges = <&iomuxc 0 98 18>;
399 gpio6: gpio@30250000 {
400 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
401 reg = <0x30250000 0x10000>;
402 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 gpio-ranges = <&iomuxc 0 116 23>;
411 gpio7: gpio@30260000 {
412 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
413 reg = <0x30260000 0x10000>;
414 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 gpio-ranges = <&iomuxc 0 139 16>;
423 wdog1: watchdog@30280000 {
424 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
425 reg = <0x30280000 0x10000>;
426 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
430 wdog2: watchdog@30290000 {
431 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
432 reg = <0x30290000 0x10000>;
433 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
438 wdog3: watchdog@302a0000 {
439 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
440 reg = <0x302a0000 0x10000>;
441 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
446 wdog4: watchdog@302b0000 {
447 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
448 reg = <0x302b0000 0x10000>;
449 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
454 iomuxc_lpsr: pinctrl@302c0000 {
455 compatible = "fsl,imx7d-iomuxc-lpsr";
456 reg = <0x302c0000 0x10000>;
457 fsl,input-sel = <&iomuxc>;
460 gpt1: timer@302d0000 {
461 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
462 reg = <0x302d0000 0x10000>;
463 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
465 <&clks IMX7D_GPT1_ROOT_CLK>;
466 clock-names = "ipg", "per";
469 gpt2: timer@302e0000 {
470 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
471 reg = <0x302e0000 0x10000>;
472 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
474 <&clks IMX7D_GPT2_ROOT_CLK>;
475 clock-names = "ipg", "per";
479 gpt3: timer@302f0000 {
480 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
481 reg = <0x302f0000 0x10000>;
482 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
484 <&clks IMX7D_GPT3_ROOT_CLK>;
485 clock-names = "ipg", "per";
489 gpt4: timer@30300000 {
490 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
491 reg = <0x30300000 0x10000>;
492 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
494 <&clks IMX7D_GPT4_ROOT_CLK>;
495 clock-names = "ipg", "per";
499 kpp: keypad@30320000 {
500 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
501 reg = <0x30320000 0x10000>;
502 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
507 iomuxc: pinctrl@30330000 {
508 compatible = "fsl,imx7d-iomuxc";
509 reg = <0x30330000 0x10000>;
512 gpr: iomuxc-gpr@30340000 {
513 compatible = "fsl,imx7d-iomuxc-gpr",
514 "fsl,imx6q-iomuxc-gpr", "syscon",
516 reg = <0x30340000 0x10000>;
518 mux: mux-controller {
519 compatible = "mmio-mux";
520 #mux-control-cells = <1>;
521 mux-reg-masks = <0x14 0x00000010>;
525 compatible = "video-mux";
526 mux-controls = <&mux 0>;
527 #address-cells = <1>;
538 csi_mux_from_mipi_vc0: endpoint {
539 remote-endpoint = <&mipi_vc0_to_csi_mux>;
546 csi_mux_to_csi: endpoint {
547 remote-endpoint = <&csi_from_csi_mux>;
553 ocotp: efuse@30350000 {
554 #address-cells = <1>;
556 compatible = "fsl,imx7d-ocotp", "syscon";
557 reg = <0x30350000 0x10000>;
558 clocks = <&clks IMX7D_OCOTP_CLK>;
560 tempmon_calib: calib@3c {
564 fuse_grade: fuse-grade@10 {
569 anatop: anatop@30360000 {
570 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
571 "syscon", "simple-mfd";
572 reg = <0x30360000 0x10000>;
573 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
576 reg_1p0d: regulator-vdd1p0d {
577 compatible = "fsl,anatop-regulator";
578 regulator-name = "vdd1p0d";
579 regulator-min-microvolt = <800000>;
580 regulator-max-microvolt = <1200000>;
581 anatop-reg-offset = <0x210>;
582 anatop-vol-bit-shift = <8>;
583 anatop-vol-bit-width = <5>;
584 anatop-min-bit-val = <8>;
585 anatop-min-voltage = <800000>;
586 anatop-max-voltage = <1200000>;
587 anatop-enable-bit = <0>;
590 reg_1p2: regulator-vdd1p2 {
591 compatible = "fsl,anatop-regulator";
592 regulator-name = "vdd1p2";
593 regulator-min-microvolt = <1100000>;
594 regulator-max-microvolt = <1300000>;
595 anatop-reg-offset = <0x220>;
596 anatop-vol-bit-shift = <8>;
597 anatop-vol-bit-width = <5>;
598 anatop-min-bit-val = <0x14>;
599 anatop-min-voltage = <1100000>;
600 anatop-max-voltage = <1300000>;
601 anatop-enable-bit = <0>;
605 compatible = "fsl,imx7d-tempmon";
606 interrupt-parent = <&gpc>;
607 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
608 fsl,tempmon = <&anatop>;
609 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
610 nvmem-cell-names = "calib", "temp_grade";
611 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
615 snvs: snvs@30370000 {
616 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
617 reg = <0x30370000 0x10000>;
619 snvs_rtc: snvs-rtc-lp {
620 compatible = "fsl,sec-v4.0-mon-rtc-lp";
623 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks IMX7D_SNVS_CLK>;
626 clock-names = "snvs-rtc";
629 snvs_pwrkey: snvs-powerkey {
630 compatible = "fsl,sec-v4.0-pwrkey";
632 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&clks IMX7D_SNVS_CLK>;
634 clock-names = "snvs-pwrkey";
635 linux,keycode = <KEY_POWER>;
641 clks: clock-controller@30380000 {
642 compatible = "fsl,imx7d-ccm";
643 reg = <0x30380000 0x10000>;
644 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&ckil>, <&osc>;
648 clock-names = "ckil", "osc";
651 src: reset-controller@30390000 {
652 compatible = "fsl,imx7d-src", "syscon";
653 reg = <0x30390000 0x10000>;
654 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
659 compatible = "fsl,imx7d-gpc";
660 reg = <0x303a0000 0x10000>;
661 interrupt-controller;
662 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
663 #interrupt-cells = <3>;
664 interrupt-parent = <&intc>;
665 #power-domain-cells = <1>;
668 #address-cells = <1>;
671 pgc_mipi_phy: power-domain@0 {
672 #power-domain-cells = <0>;
674 power-supply = <®_1p0d>;
677 pgc_pcie_phy: power-domain@1 {
678 #power-domain-cells = <0>;
680 power-supply = <®_1p0d>;
683 pgc_hsic_phy: power-domain@2 {
684 #power-domain-cells = <0>;
686 power-supply = <®_1p2>;
692 aips2: bus@30400000 {
693 compatible = "fsl,aips-bus", "simple-bus";
694 #address-cells = <1>;
696 reg = <0x30400000 0x400000>;
700 compatible = "fsl,imx7d-adc";
701 reg = <0x30610000 0x10000>;
702 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
705 #io-channel-cells = <1>;
710 compatible = "fsl,imx7d-adc";
711 reg = <0x30620000 0x10000>;
712 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
715 #io-channel-cells = <1>;
719 ecspi4: spi@30630000 {
720 #address-cells = <1>;
722 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
723 reg = <0x30630000 0x10000>;
724 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
726 <&clks IMX7D_ECSPI4_ROOT_CLK>;
727 clock-names = "ipg", "per";
732 compatible = "fsl,vf610-ftm-pwm";
733 reg = <0x30640000 0x10000>;
735 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
736 clock-names = "ftm_sys", "ftm_ext",
737 "ftm_fix", "ftm_cnt_clk_en";
738 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
739 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
740 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
741 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
746 compatible = "fsl,vf610-ftm-pwm";
747 reg = <0x30650000 0x10000>;
749 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
750 clock-names = "ftm_sys", "ftm_ext",
751 "ftm_fix", "ftm_cnt_clk_en";
752 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
753 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
754 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
755 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
760 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
761 reg = <0x30660000 0x10000>;
762 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
764 <&clks IMX7D_PWM1_ROOT_CLK>;
765 clock-names = "ipg", "per";
771 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
772 reg = <0x30670000 0x10000>;
773 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
775 <&clks IMX7D_PWM2_ROOT_CLK>;
776 clock-names = "ipg", "per";
782 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
783 reg = <0x30680000 0x10000>;
784 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
786 <&clks IMX7D_PWM3_ROOT_CLK>;
787 clock-names = "ipg", "per";
793 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
794 reg = <0x30690000 0x10000>;
795 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
797 <&clks IMX7D_PWM4_ROOT_CLK>;
798 clock-names = "ipg", "per";
804 compatible = "fsl,imx7-csi";
805 reg = <0x30710000 0x10000>;
806 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clks IMX7D_CLK_DUMMY>,
808 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
809 <&clks IMX7D_CLK_DUMMY>;
810 clock-names = "axi", "mclk", "dcic";
814 csi_from_csi_mux: endpoint {
815 remote-endpoint = <&csi_mux_to_csi>;
820 lcdif: lcdif@30730000 {
821 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
822 reg = <0x30730000 0x10000>;
823 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
825 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
826 clock-names = "pix", "axi";
830 mipi_csi: mipi-csi@30750000 {
831 compatible = "fsl,imx7-mipi-csi2";
832 reg = <0x30750000 0x10000>;
833 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
835 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
836 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
837 clock-names = "pclk", "wrap", "phy";
838 power-domains = <&pgc_mipi_phy>;
839 phy-supply = <®_1p0d>;
840 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
844 #address-cells = <1>;
854 mipi_vc0_to_csi_mux: endpoint {
855 remote-endpoint = <&csi_mux_from_mipi_vc0>;
862 aips3: bus@30800000 {
863 compatible = "fsl,aips-bus", "simple-bus";
864 #address-cells = <1>;
866 reg = <0x30800000 0x400000>;
870 compatible = "fsl,spba-bus", "simple-bus";
871 #address-cells = <1>;
873 reg = <0x30800000 0x100000>;
876 ecspi1: spi@30820000 {
877 #address-cells = <1>;
879 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
880 reg = <0x30820000 0x10000>;
881 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
883 <&clks IMX7D_ECSPI1_ROOT_CLK>;
884 clock-names = "ipg", "per";
888 ecspi2: spi@30830000 {
889 #address-cells = <1>;
891 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
892 reg = <0x30830000 0x10000>;
893 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
895 <&clks IMX7D_ECSPI2_ROOT_CLK>;
896 clock-names = "ipg", "per";
900 ecspi3: spi@30840000 {
901 #address-cells = <1>;
903 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
904 reg = <0x30840000 0x10000>;
905 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
907 <&clks IMX7D_ECSPI3_ROOT_CLK>;
908 clock-names = "ipg", "per";
912 uart1: serial@30860000 {
913 compatible = "fsl,imx7d-uart",
915 reg = <0x30860000 0x10000>;
916 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
918 <&clks IMX7D_UART1_ROOT_CLK>;
919 clock-names = "ipg", "per";
923 uart2: serial@30890000 {
924 compatible = "fsl,imx7d-uart",
926 reg = <0x30890000 0x10000>;
927 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
929 <&clks IMX7D_UART2_ROOT_CLK>;
930 clock-names = "ipg", "per";
934 uart3: serial@30880000 {
935 compatible = "fsl,imx7d-uart",
937 reg = <0x30880000 0x10000>;
938 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
940 <&clks IMX7D_UART3_ROOT_CLK>;
941 clock-names = "ipg", "per";
946 #sound-dai-cells = <0>;
947 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
948 reg = <0x308a0000 0x10000>;
949 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
951 <&clks IMX7D_SAI1_ROOT_CLK>,
952 <&clks IMX7D_CLK_DUMMY>,
953 <&clks IMX7D_CLK_DUMMY>;
954 clock-names = "bus", "mclk1", "mclk2", "mclk3";
955 dma-names = "rx", "tx";
956 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
961 #sound-dai-cells = <0>;
962 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
963 reg = <0x308b0000 0x10000>;
964 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
966 <&clks IMX7D_SAI2_ROOT_CLK>,
967 <&clks IMX7D_CLK_DUMMY>,
968 <&clks IMX7D_CLK_DUMMY>;
969 clock-names = "bus", "mclk1", "mclk2", "mclk3";
970 dma-names = "rx", "tx";
971 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
976 #sound-dai-cells = <0>;
977 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
978 reg = <0x308c0000 0x10000>;
979 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
981 <&clks IMX7D_SAI3_ROOT_CLK>,
982 <&clks IMX7D_CLK_DUMMY>,
983 <&clks IMX7D_CLK_DUMMY>;
984 clock-names = "bus", "mclk1", "mclk2", "mclk3";
985 dma-names = "rx", "tx";
986 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
991 crypto: crypto@30900000 {
992 compatible = "fsl,sec-v4.0";
993 #address-cells = <1>;
995 reg = <0x30900000 0x40000>;
996 ranges = <0 0x30900000 0x40000>;
997 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX7D_CAAM_CLK>,
999 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1000 clock-names = "ipg", "aclk";
1003 compatible = "fsl,sec-v4.0-job-ring";
1004 reg = <0x1000 0x1000>;
1005 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1009 compatible = "fsl,sec-v4.0-job-ring";
1010 reg = <0x2000 0x1000>;
1011 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1015 compatible = "fsl,sec-v4.0-job-ring";
1016 reg = <0x3000 0x1000>;
1017 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1021 flexcan1: can@30a00000 {
1022 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1023 reg = <0x30a00000 0x10000>;
1024 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&clks IMX7D_CLK_DUMMY>,
1026 <&clks IMX7D_CAN1_ROOT_CLK>;
1027 clock-names = "ipg", "per";
1028 fsl,stop-mode = <&gpr 0x10 1>;
1029 status = "disabled";
1032 flexcan2: can@30a10000 {
1033 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1034 reg = <0x30a10000 0x10000>;
1035 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX7D_CLK_DUMMY>,
1037 <&clks IMX7D_CAN2_ROOT_CLK>;
1038 clock-names = "ipg", "per";
1039 fsl,stop-mode = <&gpr 0x10 2>;
1040 status = "disabled";
1043 i2c1: i2c@30a20000 {
1044 #address-cells = <1>;
1046 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1047 reg = <0x30a20000 0x10000>;
1048 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1050 status = "disabled";
1053 i2c2: i2c@30a30000 {
1054 #address-cells = <1>;
1056 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1057 reg = <0x30a30000 0x10000>;
1058 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1060 status = "disabled";
1063 i2c3: i2c@30a40000 {
1064 #address-cells = <1>;
1066 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1067 reg = <0x30a40000 0x10000>;
1068 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1070 status = "disabled";
1073 i2c4: i2c@30a50000 {
1074 #address-cells = <1>;
1076 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1077 reg = <0x30a50000 0x10000>;
1078 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1080 status = "disabled";
1083 uart4: serial@30a60000 {
1084 compatible = "fsl,imx7d-uart",
1086 reg = <0x30a60000 0x10000>;
1087 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1089 <&clks IMX7D_UART4_ROOT_CLK>;
1090 clock-names = "ipg", "per";
1091 status = "disabled";
1094 uart5: serial@30a70000 {
1095 compatible = "fsl,imx7d-uart",
1097 reg = <0x30a70000 0x10000>;
1098 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1100 <&clks IMX7D_UART5_ROOT_CLK>;
1101 clock-names = "ipg", "per";
1102 status = "disabled";
1105 uart6: serial@30a80000 {
1106 compatible = "fsl,imx7d-uart",
1108 reg = <0x30a80000 0x10000>;
1109 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1111 <&clks IMX7D_UART6_ROOT_CLK>;
1112 clock-names = "ipg", "per";
1113 status = "disabled";
1116 uart7: serial@30a90000 {
1117 compatible = "fsl,imx7d-uart",
1119 reg = <0x30a90000 0x10000>;
1120 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1122 <&clks IMX7D_UART7_ROOT_CLK>;
1123 clock-names = "ipg", "per";
1124 status = "disabled";
1127 mu0a: mailbox@30aa0000 {
1128 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1129 reg = <0x30aa0000 0x10000>;
1130 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1133 status = "disabled";
1136 mu0b: mailbox@30ab0000 {
1137 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1138 reg = <0x30ab0000 0x10000>;
1139 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1143 status = "disabled";
1146 usbotg1: usb@30b10000 {
1147 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1148 reg = <0x30b10000 0x200>;
1149 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1151 fsl,usbphy = <&usbphynop1>;
1152 fsl,usbmisc = <&usbmisc1 0>;
1153 phy-clkgate-delay-us = <400>;
1154 status = "disabled";
1157 usbh: usb@30b30000 {
1158 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1159 reg = <0x30b30000 0x200>;
1160 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1162 fsl,usbphy = <&usbphynop3>;
1163 fsl,usbmisc = <&usbmisc3 0>;
1166 phy-clkgate-delay-us = <400>;
1167 status = "disabled";
1170 usbmisc1: usbmisc@30b10200 {
1172 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1173 reg = <0x30b10200 0x200>;
1176 usbmisc3: usbmisc@30b30200 {
1178 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1179 reg = <0x30b30200 0x200>;
1182 usdhc1: mmc@30b40000 {
1183 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1184 reg = <0x30b40000 0x10000>;
1185 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1186 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1187 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1188 <&clks IMX7D_USDHC1_ROOT_CLK>;
1189 clock-names = "ipg", "ahb", "per";
1191 fsl,tuning-step = <2>;
1192 fsl,tuning-start-tap = <20>;
1193 status = "disabled";
1196 usdhc2: mmc@30b50000 {
1197 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1198 reg = <0x30b50000 0x10000>;
1199 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1201 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1202 <&clks IMX7D_USDHC2_ROOT_CLK>;
1203 clock-names = "ipg", "ahb", "per";
1205 fsl,tuning-step = <2>;
1206 fsl,tuning-start-tap = <20>;
1207 status = "disabled";
1210 usdhc3: mmc@30b60000 {
1211 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1212 reg = <0x30b60000 0x10000>;
1213 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1215 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1216 <&clks IMX7D_USDHC3_ROOT_CLK>;
1217 clock-names = "ipg", "ahb", "per";
1219 fsl,tuning-step = <2>;
1220 fsl,tuning-start-tap = <20>;
1221 status = "disabled";
1224 qspi: spi@30bb0000 {
1225 compatible = "fsl,imx7d-qspi";
1226 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1227 reg-names = "QuadSPI", "QuadSPI-memory";
1228 #address-cells = <1>;
1230 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1232 <&clks IMX7D_QSPI_ROOT_CLK>;
1233 clock-names = "qspi_en", "qspi";
1234 status = "disabled";
1237 sdma: dma-controller@30bd0000 {
1238 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1239 reg = <0x30bd0000 0x10000>;
1240 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1242 <&clks IMX7D_SDMA_CORE_CLK>;
1243 clock-names = "ipg", "ahb";
1245 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1248 fec1: ethernet@30be0000 {
1249 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1250 reg = <0x30be0000 0x10000>;
1251 interrupt-names = "int0", "int1", "int2", "pps";
1252 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1257 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1258 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1259 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1260 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1261 clock-names = "ipg", "ahb", "ptp",
1262 "enet_clk_ref", "enet_out";
1263 fsl,num-tx-queues = <3>;
1264 fsl,num-rx-queues = <3>;
1265 fsl,stop-mode = <&gpr 0x10 3>;
1266 status = "disabled";
1270 dma_apbh: dma-controller@33000000 {
1271 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1272 reg = <0x33000000 0x2000>;
1273 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1282 gpmi: nand-controller@33002000 {
1283 compatible = "fsl,imx7d-gpmi-nand";
1284 #address-cells = <1>;
1286 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1287 reg-names = "gpmi-nand", "bch";
1288 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1289 interrupt-names = "bch";
1290 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1291 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1292 clock-names = "gpmi_io", "gpmi_bch_apb";
1293 dmas = <&dma_apbh 0>;
1294 dma-names = "rx-tx";
1295 status = "disabled";
1296 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1297 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;