1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Marvell Technology Group Ltd.
4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0x3>;
36 axi@d4200000 { /* AXI */
37 compatible = "mrvl,axi-bus", "simple-bus";
40 reg = <0xd4200000 0x00200000>;
44 compatible = "vivante,gc";
45 reg = <0xd420d000 0x4000>;
48 clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
49 <&soc_clocks MMP2_CLK_GPU_BUS>;
50 clock-names = "core", "bus";
51 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
54 intc: interrupt-controller@d4282000 {
55 compatible = "mrvl,mmp2-intc";
57 #interrupt-cells = <1>;
58 reg = <0xd4282000 0x1000>;
59 mrvl,intc-nr-irqs = <64>;
62 intcmux4: interrupt-controller@d4282150 {
63 compatible = "mrvl,mmp2-mux-intc";
66 #interrupt-cells = <1>;
67 reg = <0x150 0x4>, <0x168 0x4>;
68 reg-names = "mux status", "mux mask";
69 mrvl,intc-nr-irqs = <2>;
72 intcmux5: interrupt-controller@d4282154 {
73 compatible = "mrvl,mmp2-mux-intc";
76 #interrupt-cells = <1>;
77 reg = <0x154 0x4>, <0x16c 0x4>;
78 reg-names = "mux status", "mux mask";
79 mrvl,intc-nr-irqs = <2>;
80 mrvl,clr-mfp-irq = <1>;
83 intcmux9: interrupt-controller@d4282180 {
84 compatible = "mrvl,mmp2-mux-intc";
87 #interrupt-cells = <1>;
88 reg = <0x180 0x4>, <0x17c 0x4>;
89 reg-names = "mux status", "mux mask";
90 mrvl,intc-nr-irqs = <3>;
93 intcmux17: interrupt-controller@d4282158 {
94 compatible = "mrvl,mmp2-mux-intc";
97 #interrupt-cells = <1>;
98 reg = <0x158 0x4>, <0x170 0x4>;
99 reg-names = "mux status", "mux mask";
100 mrvl,intc-nr-irqs = <5>;
103 intcmux35: interrupt-controller@d428215c {
104 compatible = "mrvl,mmp2-mux-intc";
106 interrupt-controller;
107 #interrupt-cells = <1>;
108 reg = <0x15c 0x4>, <0x174 0x4>;
109 reg-names = "mux status", "mux mask";
110 mrvl,intc-nr-irqs = <15>;
113 intcmux51: interrupt-controller@d4282160 {
114 compatible = "mrvl,mmp2-mux-intc";
116 interrupt-controller;
117 #interrupt-cells = <1>;
118 reg = <0x160 0x4>, <0x178 0x4>;
119 reg-names = "mux status", "mux mask";
120 mrvl,intc-nr-irqs = <2>;
123 intcmux55: interrupt-controller@d4282188 {
124 compatible = "mrvl,mmp2-mux-intc";
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 reg = <0x188 0x4>, <0x184 0x4>;
129 reg-names = "mux status", "mux mask";
130 mrvl,intc-nr-irqs = <2>;
133 usb_phy0: usb-phy@d4207000 {
134 compatible = "marvell,mmp2-usb-phy";
135 reg = <0xd4207000 0x40>;
140 usb_otg0: usb-otg@d4208000 {
141 compatible = "marvell,pxau2o-ehci";
142 reg = <0xd4208000 0x200>;
144 clocks = <&soc_clocks MMP2_CLK_USB>;
145 clock-names = "USBCLK";
152 compatible = "mrvl,pxav3-mmc";
153 reg = <0xd4280000 0x120>;
154 clocks = <&soc_clocks MMP2_CLK_SDH0>;
161 compatible = "mrvl,pxav3-mmc";
162 reg = <0xd4280800 0x120>;
163 clocks = <&soc_clocks MMP2_CLK_SDH1>;
170 compatible = "mrvl,pxav3-mmc";
171 reg = <0xd4281000 0x120>;
172 clocks = <&soc_clocks MMP2_CLK_SDH2>;
179 compatible = "mrvl,pxav3-mmc";
180 reg = <0xd4281800 0x120>;
181 clocks = <&soc_clocks MMP2_CLK_SDH3>;
187 camera0: camera@d420a000 {
188 compatible = "marvell,mmp2-ccic";
189 reg = <0xd420a000 0x800>;
191 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
194 clock-output-names = "mclk";
198 camera1: camera@d420a800 {
199 compatible = "marvell,mmp2-ccic";
200 reg = <0xd420a800 0x800>;
202 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
205 clock-output-names = "mclk";
209 adma0: dma-controller@d42a0800 {
210 compatible = "marvell,adma-1.0";
211 reg = <0xd42a0800 0x100>;
219 adma1: dma-controller@d42a0900 {
220 compatible = "marvell,adma-1.0";
221 reg = <0xd42a0900 0x100>;
227 audio_clk: clocks@d42a0c30 {
228 compatible = "marvell,mmp2-audio-clock";
229 reg = <0xd42a0c30 0x10>;
230 clock-names = "audio", "vctcxo", "i2s0", "i2s1";
231 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
232 <&soc_clocks MMP2_CLK_VCTCXO>,
233 <&soc_clocks MMP2_CLK_I2S0>,
234 <&soc_clocks MMP2_CLK_I2S1>;
235 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
240 sspa0: audio-controller@d42a0c00 {
241 compatible = "marvell,mmp-sspa";
242 reg = <0xd42a0c00 0x30>,
245 clock-names = "audio", "bitclk";
246 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
247 <&audio_clk MMP2_CLK_AUDIO_SSPA0>;
248 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
249 #sound-dai-cells = <0>;
253 sspa1: audio-controller@d42a0d00 {
254 compatible = "marvell,mmp-sspa";
255 reg = <0xd42a0d00 0x30>,
258 clock-names = "audio", "bitclk";
259 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
260 <&audio_clk MMP2_CLK_AUDIO_SSPA1>;
261 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
262 #sound-dai-cells = <0>;
267 apb@d4000000 { /* APB */
268 compatible = "mrvl,apb-bus", "simple-bus";
269 #address-cells = <1>;
271 reg = <0xd4000000 0x00200000>;
274 dma-controller@d4000000 {
275 compatible = "marvell,pdma-1.0";
276 reg = <0xd4000000 0x10000>;
278 #dma-channels = <16>;
282 timer0: timer@d4014000 {
283 compatible = "mrvl,mmp-timer";
284 reg = <0xd4014000 0x100>;
286 clocks = <&soc_clocks MMP2_CLK_TIMER>;
289 uart1: serial@d4030000 {
290 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
291 reg = <0xd4030000 0x1000>;
293 clocks = <&soc_clocks MMP2_CLK_UART0>;
294 resets = <&soc_clocks MMP2_CLK_UART0>;
299 uart2: serial@d4017000 {
300 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
301 reg = <0xd4017000 0x1000>;
303 clocks = <&soc_clocks MMP2_CLK_UART1>;
304 resets = <&soc_clocks MMP2_CLK_UART1>;
309 uart3: serial@d4018000 {
310 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
311 reg = <0xd4018000 0x1000>;
313 clocks = <&soc_clocks MMP2_CLK_UART2>;
314 resets = <&soc_clocks MMP2_CLK_UART2>;
319 uart4: serial@d4016000 {
320 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
321 reg = <0xd4016000 0x1000>;
323 clocks = <&soc_clocks MMP2_CLK_UART3>;
324 resets = <&soc_clocks MMP2_CLK_UART3>;
329 gpio: gpio@d4019000 {
330 compatible = "marvell,mmp2-gpio";
331 #address-cells = <1>;
333 reg = <0xd4019000 0x1000>;
337 interrupt-names = "gpio_mux";
338 clocks = <&soc_clocks MMP2_CLK_GPIO>;
339 resets = <&soc_clocks MMP2_CLK_GPIO>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
344 gcb0: gpio@d4019000 {
345 reg = <0xd4019000 0x4>;
348 gcb1: gpio@d4019004 {
349 reg = <0xd4019004 0x4>;
352 gcb2: gpio@d4019008 {
353 reg = <0xd4019008 0x4>;
356 gcb3: gpio@d4019100 {
357 reg = <0xd4019100 0x4>;
360 gcb4: gpio@d4019104 {
361 reg = <0xd4019104 0x4>;
364 gcb5: gpio@d4019108 {
365 reg = <0xd4019108 0x4>;
369 twsi1: i2c@d4011000 {
370 compatible = "mrvl,mmp-twsi";
371 reg = <0xd4011000 0x1000>;
373 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
374 resets = <&soc_clocks MMP2_CLK_TWSI0>;
375 #address-cells = <1>;
381 twsi2: i2c@d4031000 {
382 compatible = "mrvl,mmp-twsi";
383 reg = <0xd4031000 0x1000>;
384 interrupt-parent = <&intcmux17>;
386 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
387 resets = <&soc_clocks MMP2_CLK_TWSI1>;
388 #address-cells = <1>;
393 twsi3: i2c@d4032000 {
394 compatible = "mrvl,mmp-twsi";
395 reg = <0xd4032000 0x1000>;
396 interrupt-parent = <&intcmux17>;
398 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
399 resets = <&soc_clocks MMP2_CLK_TWSI2>;
400 #address-cells = <1>;
405 twsi4: i2c@d4033000 {
406 compatible = "mrvl,mmp-twsi";
407 reg = <0xd4033000 0x1000>;
408 interrupt-parent = <&intcmux17>;
410 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
411 resets = <&soc_clocks MMP2_CLK_TWSI3>;
412 #address-cells = <1>;
418 twsi5: i2c@d4033800 {
419 compatible = "mrvl,mmp-twsi";
420 reg = <0xd4033800 0x1000>;
421 interrupt-parent = <&intcmux17>;
423 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
424 resets = <&soc_clocks MMP2_CLK_TWSI4>;
425 #address-cells = <1>;
430 twsi6: i2c@d4034000 {
431 compatible = "mrvl,mmp-twsi";
432 reg = <0xd4034000 0x1000>;
433 interrupt-parent = <&intcmux17>;
435 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
436 resets = <&soc_clocks MMP2_CLK_TWSI5>;
437 #address-cells = <1>;
443 compatible = "mrvl,mmp-rtc";
444 reg = <0xd4010000 0x1000>;
445 interrupts = <1>, <0>;
446 interrupt-names = "rtc 1Hz", "rtc alarm";
447 interrupt-parent = <&intcmux5>;
448 clocks = <&soc_clocks MMP2_CLK_RTC>;
449 resets = <&soc_clocks MMP2_CLK_RTC>;
454 compatible = "marvell,mmp2-ssp";
455 reg = <0xd4035000 0x1000>;
456 clocks = <&soc_clocks MMP2_CLK_SSP0>;
458 #address-cells = <1>;
464 compatible = "marvell,mmp2-ssp";
465 reg = <0xd4036000 0x1000>;
466 clocks = <&soc_clocks MMP2_CLK_SSP1>;
468 #address-cells = <1>;
474 compatible = "marvell,mmp2-ssp";
475 reg = <0xd4037000 0x1000>;
476 clocks = <&soc_clocks MMP2_CLK_SSP2>;
478 #address-cells = <1>;
484 compatible = "marvell,mmp2-ssp";
485 reg = <0xd4039000 0x1000>;
486 clocks = <&soc_clocks MMP2_CLK_SSP3>;
488 #address-cells = <1>;
494 asram: sram@e0000000 {
495 compatible = "mmio-sram";
496 reg = <0xe0000000 0x10000>;
497 ranges = <0 0xe0000000 0x10000>;
498 #address-cells = <1>;
504 compatible = "marvell,mmp2-clock";
505 reg = <0xd4050000 0x2000>,
508 reg-names = "mpmu", "apmu", "apbc";
511 #power-domain-cells = <1>;