1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
23 compatible = "arm,cortex-a5";
24 next-level-cache = <&L2>;
26 enable-method = "amlogic,meson8b-smp";
27 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
28 operating-points-v2 = <&cpu_opp_table>;
29 clocks = <&clkc CLKID_CPUCLK>;
30 #cooling-cells = <2>; /* min followed by max */
35 compatible = "arm,cortex-a5";
36 next-level-cache = <&L2>;
38 enable-method = "amlogic,meson8b-smp";
39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
40 operating-points-v2 = <&cpu_opp_table>;
41 clocks = <&clkc CLKID_CPUCLK>;
42 #cooling-cells = <2>; /* min followed by max */
47 compatible = "arm,cortex-a5";
48 next-level-cache = <&L2>;
50 enable-method = "amlogic,meson8b-smp";
51 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
52 operating-points-v2 = <&cpu_opp_table>;
53 clocks = <&clkc CLKID_CPUCLK>;
54 #cooling-cells = <2>; /* min followed by max */
59 compatible = "arm,cortex-a5";
60 next-level-cache = <&L2>;
62 enable-method = "amlogic,meson8b-smp";
63 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
64 operating-points-v2 = <&cpu_opp_table>;
65 clocks = <&clkc CLKID_CPUCLK>;
66 #cooling-cells = <2>; /* min followed by max */
70 cpu_opp_table: opp-table {
71 compatible = "operating-points-v2";
75 opp-hz = /bits/ 64 <96000000>;
76 opp-microvolt = <860000>;
79 opp-hz = /bits/ 64 <192000000>;
80 opp-microvolt = <860000>;
83 opp-hz = /bits/ 64 <312000000>;
84 opp-microvolt = <860000>;
87 opp-hz = /bits/ 64 <408000000>;
88 opp-microvolt = <860000>;
91 opp-hz = /bits/ 64 <504000000>;
92 opp-microvolt = <860000>;
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <860000>;
99 opp-hz = /bits/ 64 <720000000>;
100 opp-microvolt = <860000>;
103 opp-hz = /bits/ 64 <816000000>;
104 opp-microvolt = <900000>;
107 opp-hz = /bits/ 64 <1008000000>;
108 opp-microvolt = <1140000>;
111 opp-hz = /bits/ 64 <1200000000>;
112 opp-microvolt = <1140000>;
115 opp-hz = /bits/ 64 <1320000000>;
116 opp-microvolt = <1140000>;
119 opp-hz = /bits/ 64 <1488000000>;
120 opp-microvolt = <1140000>;
123 opp-hz = /bits/ 64 <1536000000>;
124 opp-microvolt = <1140000>;
128 gpu_opp_table: opp-table-gpu {
129 compatible = "operating-points-v2";
132 opp-hz = /bits/ 64 <255000000>;
133 opp-microvolt = <1100000>;
136 opp-hz = /bits/ 64 <364285714>;
137 opp-microvolt = <1100000>;
140 opp-hz = /bits/ 64 <425000000>;
141 opp-microvolt = <1100000>;
144 opp-hz = /bits/ 64 <510000000>;
145 opp-microvolt = <1100000>;
148 opp-hz = /bits/ 64 <637500000>;
149 opp-microvolt = <1100000>;
155 compatible = "arm,cortex-a5-pmu";
156 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
164 #address-cells = <1>;
168 /* 2 MiB reserved for Hardware ROM Firmware? */
170 reg = <0x0 0x200000>;
177 polling-delay-passive = <250>; /* milliseconds */
178 polling-delay = <1000>; /* milliseconds */
179 thermal-sensors = <&thermal_sensor>;
183 trip = <&soc_passive>;
184 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
186 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
195 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
196 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
197 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
202 soc_passive: soc-passive {
203 temperature = <80000>; /* millicelsius */
204 hysteresis = <2000>; /* millicelsius */
209 temperature = <90000>; /* millicelsius */
210 hysteresis = <2000>; /* millicelsius */
214 soc_critical: soc-critical {
215 temperature = <110000>; /* millicelsius */
216 hysteresis = <2000>; /* millicelsius */
223 mmcbus: bus@c8000000 {
224 compatible = "simple-bus";
225 reg = <0xc8000000 0x8000>;
226 #address-cells = <1>;
228 ranges = <0x0 0xc8000000 0x8000>;
230 ddr_clkc: clock-controller@400 {
231 compatible = "amlogic,meson8b-ddr-clkc";
234 clock-names = "xtal";
239 compatible = "simple-bus";
240 reg = <0x6000 0x400>;
241 #address-cells = <1>;
243 ranges = <0x0 0x6000 0x400>;
245 canvas: video-lut@48 {
246 compatible = "amlogic,meson8b-canvas",
254 compatible = "simple-bus";
255 reg = <0xd0000000 0x200000>;
256 #address-cells = <1>;
258 ranges = <0x0 0xd0000000 0x200000>;
261 compatible = "amlogic,meson8b-mali", "arm,mali-450";
262 reg = <0xc0000 0x40000>;
263 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-names = "gp", "gpmmu", "pp", "pmu",
272 "pp0", "ppmmu0", "pp1", "ppmmu1";
273 resets = <&reset RESET_MALI>;
274 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
275 clock-names = "bus", "core";
276 operating-points-v2 = <&gpu_opp_table>;
277 #cooling-cells = <2>; /* min followed by max */
283 compatible = "amlogic,aiu-meson8b", "amlogic,aiu";
284 clocks = <&clkc CLKID_AIU_GLUE>,
285 <&clkc CLKID_I2S_OUT>,
286 <&clkc CLKID_AOCLK_GATE>,
287 <&clkc CLKID_CTS_AMCLK>,
288 <&clkc CLKID_MIXER_IFACE>,
289 <&clkc CLKID_IEC958>,
290 <&clkc CLKID_IEC958_GATE>,
291 <&clkc CLKID_CTS_MCLK_I958>,
292 <&clkc CLKID_CTS_I958>;
293 clock-names = "pclk",
302 resets = <&reset RESET_AIU>;
307 compatible = "amlogic,meson8b-pmu", "syscon";
311 pinctrl_aobus: pinctrl@84 {
312 compatible = "amlogic,meson8b-aobus-pinctrl";
314 #address-cells = <1>;
318 gpio_ao: ao-bank@14 {
322 reg-names = "mux", "pull", "gpio";
325 gpio-ranges = <&pinctrl_aobus 0 0 16>;
328 i2s_am_clk_pins: i2s-am-clk-out {
330 groups = "i2s_am_clk_out";
336 i2s_out_ao_clk_pins: i2s-ao-clk-out {
338 groups = "i2s_ao_clk_out";
344 i2s_out_lr_clk_pins: i2s-lr-clk-out {
346 groups = "i2s_lr_clk_out";
352 i2s_out_ch01_ao_pins: i2s-out-ch01 {
354 groups = "i2s_out_01";
360 spdif_out_1_pins: spdif-out-1 {
362 groups = "spdif_out_1";
363 function = "spdif_1";
368 uart_ao_a_pins: uart_ao_a {
370 groups = "uart_tx_ao_a", "uart_rx_ao_a";
371 function = "uart_ao";
376 ir_recv_pins: remote {
378 groups = "remote_input";
387 compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
388 amlogic,secbus2 = <&secbus2>;
389 sram = <&ao_arc_sram>;
390 resets = <&reset RESET_MEDIA_CPU>;
391 clocks = <&clkc CLKID_AO_MEDIA_CPU>;
395 reset: reset-controller@4404 {
396 compatible = "amlogic,meson8b-reset";
401 analog_top: analog-top@81a8 {
402 compatible = "amlogic,meson8b-analog-top", "syscon";
407 compatible = "amlogic,meson8b-pwm";
414 compatible = "amlogic,meson8b-clk-measure";
418 pinctrl_cbus: pinctrl@9880 {
419 compatible = "amlogic,meson8b-cbus-pinctrl";
421 #address-cells = <1>;
430 reg-names = "mux", "pull", "pull-enable", "gpio";
433 gpio-ranges = <&pinctrl_cbus 0 0 83>;
436 eth_rgmii_pins: eth-rgmii {
438 groups = "eth_tx_clk",
453 function = "ethernet";
458 eth_rmii_pins: eth-rmii {
460 groups = "eth_tx_en",
469 function = "ethernet";
476 groups = "i2c_sda_a", "i2c_sck_a";
484 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
485 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
491 sdxc_c_pins: sdxc-c {
493 groups = "sdxc_d0_c", "sdxc_d13_c",
494 "sdxc_d47_c", "sdxc_clk_c",
501 pwm_c1_pins: pwm-c1 {
517 uart_b0_pins: uart-b0 {
519 groups = "uart_tx_b0",
526 uart_b0_cts_rts_pins: uart-b0-cts-rts {
528 groups = "uart_cts_b0",
538 ao_arc_sram: ao-arc-sram@0 {
539 compatible = "amlogic,meson8b-ao-arc-sram";
545 compatible = "amlogic,meson8b-smp-sram";
552 compatible = "amlogic,meson8b-efuse";
553 clocks = <&clkc CLKID_EFUSE>;
554 clock-names = "core";
556 temperature_calib: calib@1f4 {
557 /* only the upper two bytes are relevant */
563 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
565 reg = <0xc9410000 0x10000
568 clocks = <&clkc CLKID_ETH>,
571 <&clkc CLKID_FCLK_DIV2>;
572 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
573 rx-fifo-depth = <4096>;
574 tx-fifo-depth = <2048>;
576 resets = <&reset RESET_ETHERNET>;
577 reset-names = "stmmaceth";
579 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
583 compatible = "amlogic,meson-gpio-intc",
584 "amlogic,meson8b-gpio-intc";
589 clkc: clock-controller {
590 compatible = "amlogic,meson8b-clkc";
591 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
592 clock-names = "xtal", "ddr_pll";
597 pwrc: power-controller {
598 compatible = "amlogic,meson8b-pwrc";
599 #power-domain-cells = <1>;
600 amlogic,ao-sysctrl = <&pmu>;
601 resets = <&reset RESET_DBLK>,
602 <&reset RESET_PIC_DC>,
603 <&reset RESET_HDMI_APB>,
604 <&reset RESET_HDMI_SYSTEM_RESET>,
605 <&reset RESET_VENCI>,
606 <&reset RESET_VENCP>,
607 <&reset RESET_VDAC_4>,
608 <&reset RESET_VENCL>,
612 reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
613 "venci", "vencp", "vdac", "vencl", "viu",
615 clocks = <&clkc CLKID_VPU>;
617 assigned-clocks = <&clkc CLKID_VPU>;
618 assigned-clock-rates = <182142857>;
623 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
624 clocks = <&clkc CLKID_RNG0>;
625 clock-names = "core";
629 clocks = <&clkc CLKID_CLK81>;
633 clocks = <&clkc CLKID_I2C>;
637 clocks = <&clkc CLKID_I2C>;
641 arm,data-latency = <3 3 3>;
642 arm,tag-latency = <2 2 2>;
643 arm,filter-ranges = <0x100000 0xc0000000>;
645 prefetch-instr = <1>;
646 arm,prefetch-offset = <7>;
647 arm,double-linefill = <1>;
648 arm,prefetch-drop = <1>;
654 compatible = "arm,cortex-a5-scu";
659 compatible = "arm,cortex-a5-global-timer";
661 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
662 clocks = <&clkc CLKID_PERIPH>;
665 * the arm_global_timer driver currently does not handle clock
666 * rate changes. Keep it disabled for now.
672 compatible = "arm,cortex-a5-twd-timer";
674 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
675 clocks = <&clkc CLKID_PERIPH>;
680 compatible = "amlogic,meson8b-pwm";
684 compatible = "amlogic,meson8b-pwm";
688 compatible = "amlogic,meson8b-rtc";
689 resets = <&reset RESET_RTC>;
693 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
694 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
695 clock-names = "clkin", "core";
696 amlogic,hhi-sysctrl = <&hhi>;
697 nvmem-cells = <&temperature_calib>;
698 nvmem-cell-names = "temperature_calib";
702 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
704 <&clkc CLKID_FCLK_DIV4>,
705 <&clkc CLKID_FCLK_DIV3>,
706 <&clkc CLKID_FCLK_DIV5>,
708 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
712 secbus2: system-controller@4000 {
713 compatible = "amlogic,meson8b-secbus2", "syscon";
714 reg = <0x4000 0x2000>;
719 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
720 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
721 clock-names = "core", "clkin";
725 clocks = <&xtal>, <&clkc CLKID_CLK81>;
726 clock-names = "xtal", "pclk";
730 compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
731 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
732 clock-names = "xtal", "pclk", "baud";
736 compatible = "amlogic,meson8b-uart";
737 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
738 clock-names = "xtal", "pclk", "baud";
742 compatible = "amlogic,meson8b-uart";
743 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
744 clock-names = "xtal", "pclk", "baud";
748 compatible = "amlogic,meson8b-uart";
749 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
750 clock-names = "xtal", "pclk", "baud";
754 compatible = "amlogic,meson8b-usb", "snps,dwc2";
755 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
760 compatible = "amlogic,meson8b-usb", "snps,dwc2";
761 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
766 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
767 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
768 clock-names = "usb_general", "usb";
769 resets = <&reset RESET_USB_OTG>;
773 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
774 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
775 clock-names = "usb_general", "usb";
776 resets = <&reset RESET_USB_OTG>;
780 compatible = "amlogic,meson8b-wdt";