arch/arm/boot/dts/imx7s.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4 // Copyright 2016 Toradex AG
   5
   6 #include <dt-bindings/clock/imx7d-clock.h>
   7 #include <dt-bindings/power/imx7-power.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/reset/imx7-reset.h>
  12 #include "imx7d-pinfunc.h"
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         /*
  18          * The decompressor and also some bootloaders rely on a
  19          * pre-existing /chosen node to be available to insert the
  20          * command line and merge other ATAGS info.
  21          */
  22         chosen {};
  23
  24         aliases {
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 gpio5 = &gpio6;
  31                 gpio6 = &gpio7;
  32                 i2c0 = &i2c1;
  33                 i2c1 = &i2c2;
  34                 i2c2 = &i2c3;
  35                 i2c3 = &i2c4;
  36                 mmc0 = &usdhc1;
  37                 mmc1 = &usdhc2;
  38                 mmc2 = &usdhc3;
  39                 serial0 = &uart1;
  40                 serial1 = &uart2;
  41                 serial2 = &uart3;
  42                 serial3 = &uart4;
  43                 serial4 = &uart5;
  44                 serial5 = &uart6;
  45                 serial6 = &uart7;
  46                 spi0 = &ecspi1;
  47                 spi1 = &ecspi2;
  48                 spi2 = &ecspi3;
  49                 spi3 = &ecspi4;
  50                 usb0 = &usbotg1;
  51                 usb1 = &usbh;
  52         };
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 idle-states {
  59                         entry-method = "psci";
  60
  61                         cpu_sleep_wait: cpu-sleep-wait {
  62                                 compatible = "arm,idle-state";
  63                                 arm,psci-suspend-param = <0x0010000>;
  64                                 local-timer-stop;
  65                                 entry-latency-us = <100>;
  66                                 exit-latency-us = <50>;
  67                                 min-residency-us = <1000>;
  68                         };
  69                 };
  70
  71                 cpu0: cpu@0 {
  72                         compatible = "arm,cortex-a7";
  73                         device_type = "cpu";
  74                         reg = <0>;
  75                         clock-frequency = <792000000>;
  76                         clock-latency = <61036>; /* two CLK32 periods */
  77                         clocks = <&clks IMX7D_CLK_ARM>;
  78                         cpu-idle-states = <&cpu_sleep_wait>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         #cooling-cells = <2>;
  81                         nvmem-cells = <&fuse_grade>;
  82                         nvmem-cell-names = "speed_grade";
  83                 };
  84         };
  85
  86         cpu0_opp_table: opp-table {
  87                 compatible = "operating-points-v2";
  88                 opp-shared;
  89
  90                 opp-792000000 {
  91                         opp-hz = /bits/ 64 <792000000>;
  92                         opp-microvolt = <1000000>;
  93                         clock-latency-ns = <150000>;
  94                         opp-supported-hw = <0xf>, <0xf>;
  95                 };
  96         };
  97
  98         ckil: clock-cki {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <32768>;
 102                 clock-output-names = "ckil";
 103         };
 104
 105         osc: clock-osc {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc";
 110         };
 111
 112         usbphynop1: usbphynop1 {
 113                 compatible = "usb-nop-xceiv";
 114                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
 115                 clock-names = "main_clk";
 116                 #phy-cells = <0>;
 117         };
 118
 119         usbphynop3: usbphynop3 {
 120                 compatible = "usb-nop-xceiv";
 121                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 122                 clock-names = "main_clk";
 123                 #phy-cells = <0>;
 124         };
 125
 126         pmu {
 127                 compatible = "arm,cortex-a7-pmu";
 128                 interrupt-parent = <&gpc>;
 129                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 130                 interrupt-affinity = <&cpu0>;
 131         };
 132
 133         replicator {
 134                 /*
 135                  * non-configurable replicators don't show up on the
 136                  * AMBA bus.  As such no need to add "arm,primecell"
 137                  */
 138                 compatible = "arm,coresight-static-replicator";
 139
 140                 out-ports {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                                 /* replicator output ports */
 144                         port@0 {
 145                                 reg = <0>;
 146                                 replicator_out_port0: endpoint {
 147                                         remote-endpoint = <&tpiu_in_port>;
 148                                 };
 149                         };
 150
 151                         port@1 {
 152                                 reg = <1>;
 153                                 replicator_out_port1: endpoint {
 154                                         remote-endpoint = <&etr_in_port>;
 155                                 };
 156                         };
 157                 };
 158
 159                 in-ports {
 160                         port {
 161                                 replicator_in_port0: endpoint {
 162                                         remote-endpoint = <&etf_out_port>;
 163                                 };
 164                         };
 165                 };
 166         };
 167
 168         timer {
 169                 compatible = "arm,armv7-timer";
 170                 arm,cpu-registers-not-fw-configured;
 171                 interrupt-parent = <&intc>;
 172                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 173                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 174                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 175                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 176         };
 177
 178         soc {
 179                 #address-cells = <1>;
 180                 #size-cells = <1>;
 181                 compatible = "simple-bus";
 182                 interrupt-parent = <&gpc>;
 183                 ranges;
 184
 185                 funnel@30041000 {
 186                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 187                         reg = <0x30041000 0x1000>;
 188                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 189                         clock-names = "apb_pclk";
 190
 191                         ca_funnel_in_ports: in-ports {
 192                                 port {
 193                                         ca_funnel_in_port0: endpoint {
 194                                                 remote-endpoint = <&etm0_out_port>;
 195                                         };
 196                                 };
 197
 198                                 /* the other input ports are not connect to anything */
 199                         };
 200
 201                         out-ports {
 202                                 port {
 203                                         ca_funnel_out_port0: endpoint {
 204                                                 remote-endpoint = <&hugo_funnel_in_port0>;
 205                                         };
 206                                 };
 207
 208                         };
 209                 };
 210
 211                 etm@3007c000 {
 212                         compatible = "arm,coresight-etm3x", "arm,primecell";
 213                         reg = <0x3007c000 0x1000>;
 214                         cpu = <&cpu0>;
 215                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 216                         clock-names = "apb_pclk";
 217
 218                         out-ports {
 219                                 port {
 220                                         etm0_out_port: endpoint {
 221                                                 remote-endpoint = <&ca_funnel_in_port0>;
 222                                         };
 223                                 };
 224                         };
 225                 };
 226
 227                 funnel@30083000 {
 228                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 229                         reg = <0x30083000 0x1000>;
 230                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 231                         clock-names = "apb_pclk";
 232
 233                         in-ports {
 234                                 #address-cells = <1>;
 235                                 #size-cells = <0>;
 236
 237                                 port@0 {
 238                                         reg = <0>;
 239                                         hugo_funnel_in_port0: endpoint {
 240                                                 remote-endpoint = <&ca_funnel_out_port0>;
 241                                         };
 242                                 };
 243
 244                                 port@1 {
 245                                         reg = <1>;
 246                                         hugo_funnel_in_port1: endpoint {
 247                                                 /* M4 input */
 248                                         };
 249                                 };
 250                                 /* the other input ports are not connect to anything */
 251                         };
 252
 253                         out-ports {
 254                                 port {
 255                                         hugo_funnel_out_port0: endpoint {
 256                                                 remote-endpoint = <&etf_in_port>;
 257                                         };
 258                                 };
 259                         };
 260                 };
 261
 262                 etf@30084000 {
 263                         compatible = "arm,coresight-tmc", "arm,primecell";
 264                         reg = <0x30084000 0x1000>;
 265                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 266                         clock-names = "apb_pclk";
 267
 268                         in-ports {
 269                                 port {
 270                                         etf_in_port: endpoint {
 271                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 272                                         };
 273                                 };
 274                         };
 275
 276                         out-ports {
 277                                 port {
 278                                         etf_out_port: endpoint {
 279                                                 remote-endpoint = <&replicator_in_port0>;
 280                                         };
 281                                 };
 282                         };
 283                 };
 284
 285                 etr@30086000 {
 286                         compatible = "arm,coresight-tmc", "arm,primecell";
 287                         reg = <0x30086000 0x1000>;
 288                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 289                         clock-names = "apb_pclk";
 290
 291                         in-ports {
 292                                 port {
 293                                         etr_in_port: endpoint {
 294                                                 remote-endpoint = <&replicator_out_port1>;
 295                                         };
 296                                 };
 297                         };
 298                 };
 299
 300                 tpiu@30087000 {
 301                         compatible = "arm,coresight-tpiu", "arm,primecell";
 302                         reg = <0x30087000 0x1000>;
 303                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 304                         clock-names = "apb_pclk";
 305
 306                         in-ports {
 307                                 port {
 308                                         tpiu_in_port: endpoint {
 309                                                 remote-endpoint = <&replicator_out_port0>;
 310                                         };
 311                                 };
 312                         };
 313                 };
 314
 315                 intc: interrupt-controller@31001000 {
 316                         compatible = "arm,cortex-a7-gic";
 317                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 318                         #interrupt-cells = <3>;
 319                         interrupt-controller;
 320                         interrupt-parent = <&intc>;
 321                         reg = <0x31001000 0x1000>,
 322                               <0x31002000 0x2000>,
 323                               <0x31004000 0x2000>,
 324                               <0x31006000 0x2000>;
 325                 };
 326
 327                 aips1: bus@30000000 {
 328                         compatible = "fsl,aips-bus", "simple-bus";
 329                         #address-cells = <1>;
 330                         #size-cells = <1>;
 331                         reg = <0x30000000 0x400000>;
 332                         ranges;
 333
 334                         gpio1: gpio@30200000 {
 335                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 336                                 reg = <0x30200000 0x10000>;
 337                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 338                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 339                                 gpio-controller;
 340                                 #gpio-cells = <2>;
 341                                 interrupt-controller;
 342                                 #interrupt-cells = <2>;
 343                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
 344                         };
 345
 346                         gpio2: gpio@30210000 {
 347                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 348                                 reg = <0x30210000 0x10000>;
 349                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 350                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 351                                 gpio-controller;
 352                                 #gpio-cells = <2>;
 353                                 interrupt-controller;
 354                                 #interrupt-cells = <2>;
 355                                 gpio-ranges = <&iomuxc 0 13 32>;
 356                         };
 357
 358                         gpio3: gpio@30220000 {
 359                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 360                                 reg = <0x30220000 0x10000>;
 361                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 362                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 363                                 gpio-controller;
 364                                 #gpio-cells = <2>;
 365                                 interrupt-controller;
 366                                 #interrupt-cells = <2>;
 367                                 gpio-ranges = <&iomuxc 0 45 29>;
 368                         };
 369
 370                         gpio4: gpio@30230000 {
 371                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 372                                 reg = <0x30230000 0x10000>;
 373                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 374                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 375                                 gpio-controller;
 376                                 #gpio-cells = <2>;
 377                                 interrupt-controller;
 378                                 #interrupt-cells = <2>;
 379                                 gpio-ranges = <&iomuxc 0 74 24>;
 380                         };
 381
 382                         gpio5: gpio@30240000 {
 383                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 384                                 reg = <0x30240000 0x10000>;
 385                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 386                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 387                                 gpio-controller;
 388                                 #gpio-cells = <2>;
 389                                 interrupt-controller;
 390                                 #interrupt-cells = <2>;
 391                                 gpio-ranges = <&iomuxc 0 98 18>;
 392                         };
 393
 394                         gpio6: gpio@30250000 {
 395                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 396                                 reg = <0x30250000 0x10000>;
 397                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 398                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 399                                 gpio-controller;
 400                                 #gpio-cells = <2>;
 401                                 interrupt-controller;
 402                                 #interrupt-cells = <2>;
 403                                 gpio-ranges = <&iomuxc 0 116 23>;
 404                         };
 405
 406                         gpio7: gpio@30260000 {
 407                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 408                                 reg = <0x30260000 0x10000>;
 409                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 410                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 411                                 gpio-controller;
 412                                 #gpio-cells = <2>;
 413                                 interrupt-controller;
 414                                 #interrupt-cells = <2>;
 415                                 gpio-ranges = <&iomuxc 0 139 16>;
 416                         };
 417
 418                         wdog1: watchdog@30280000 {
 419                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 420                                 reg = <0x30280000 0x10000>;
 421                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 422                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 423                         };
 424
 425                         wdog2: watchdog@30290000 {
 426                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 427                                 reg = <0x30290000 0x10000>;
 428                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 429                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 430                                 status = "disabled";
 431                         };
 432
 433                         wdog3: watchdog@302a0000 {
 434                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 435                                 reg = <0x302a0000 0x10000>;
 436                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 437                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 438                                 status = "disabled";
 439                         };
 440
 441                         wdog4: watchdog@302b0000 {
 442                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 443                                 reg = <0x302b0000 0x10000>;
 444                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 445                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 446                                 status = "disabled";
 447                         };
 448
 449                         iomuxc_lpsr: pinctrl@302c0000 {
 450                                 compatible = "fsl,imx7d-iomuxc-lpsr";
 451                                 reg = <0x302c0000 0x10000>;
 452                                 fsl,input-sel = <&iomuxc>;
 453                         };
 454
 455                         gpt1: timer@302d0000 {
 456                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 457                                 reg = <0x302d0000 0x10000>;
 458                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 459                                 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
 460                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 461                                 clock-names = "ipg", "per";
 462                         };
 463
 464                         gpt2: timer@302e0000 {
 465                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 466                                 reg = <0x302e0000 0x10000>;
 467                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 468                                 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
 469                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 470                                 clock-names = "ipg", "per";
 471                                 status = "disabled";
 472                         };
 473
 474                         gpt3: timer@302f0000 {
 475                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 476                                 reg = <0x302f0000 0x10000>;
 477                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 478                                 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
 479                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 480                                 clock-names = "ipg", "per";
 481                                 status = "disabled";
 482                         };
 483
 484                         gpt4: timer@30300000 {
 485                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 486                                 reg = <0x30300000 0x10000>;
 487                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 488                                 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
 489                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 490                                 clock-names = "ipg", "per";
 491                                 status = "disabled";
 492                         };
 493
 494                         kpp: keypad@30320000 {
 495                                 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
 496                                 reg = <0x30320000 0x10000>;
 497                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 498                                 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
 499                                 status = "disabled";
 500                         };
 501
 502                         iomuxc: pinctrl@30330000 {
 503                                 compatible = "fsl,imx7d-iomuxc";
 504                                 reg = <0x30330000 0x10000>;
 505                         };
 506
 507                         gpr: iomuxc-gpr@30340000 {
 508                                 compatible = "fsl,imx7d-iomuxc-gpr",
 509                                         "fsl,imx6q-iomuxc-gpr", "syscon",
 510                                         "simple-mfd";
 511                                 reg = <0x30340000 0x10000>;
 512
 513                                 mux: mux-controller {
 514                                         compatible = "mmio-mux";
 515                                         #mux-control-cells = <0>;
 516                                         mux-reg-masks = <0x14 0x00000010>;
 517                                 };
 518
 519                                 video_mux: csi-mux {
 520                                         compatible = "video-mux";
 521                                         mux-controls = <&mux 0>;
 522                                         #address-cells = <1>;
 523                                         #size-cells = <0>;
 524                                         status = "disabled";
 525
 526                                         port@0 {
 527                                                 reg = <0>;
 528                                         };
 529
 530                                         port@1 {
 531                                                 reg = <1>;
 532
 533                                                 csi_mux_from_mipi_vc0: endpoint {
 534                                                         remote-endpoint = <&mipi_vc0_to_csi_mux>;
 535                                                 };
 536                                         };
 537
 538                                         port@2 {
 539                                                 reg = <2>;
 540
 541                                                 csi_mux_to_csi: endpoint {
 542                                                         remote-endpoint = <&csi_from_csi_mux>;
 543                                                 };
 544                                         };
 545                                 };
 546                         };
 547
 548                         ocotp: efuse@30350000 {
 549                                 #address-cells = <1>;
 550                                 #size-cells = <1>;
 551                                 compatible = "fsl,imx7d-ocotp", "syscon";
 552                                 reg = <0x30350000 0x10000>;
 553                                 clocks = <&clks IMX7D_OCOTP_CLK>;
 554
 555                                 tempmon_calib: calib@3c {
 556                                         reg = <0x3c 0x4>;
 557                                 };
 558
 559                                 fuse_grade: fuse-grade@10 {
 560                                         reg = <0x10 0x4>;
 561                                 };
 562                         };
 563
 564                         anatop: anatop@30360000 {
 565                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 566                                         "syscon", "simple-mfd";
 567                                 reg = <0x30360000 0x10000>;
 568                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 569                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 570
 571                                 reg_1p0d: regulator-vdd1p0d {
 572                                         compatible = "fsl,anatop-regulator";
 573                                         regulator-name = "vdd1p0d";
 574                                         regulator-min-microvolt = <800000>;
 575                                         regulator-max-microvolt = <1200000>;
 576                                         anatop-reg-offset = <0x210>;
 577                                         anatop-vol-bit-shift = <8>;
 578                                         anatop-vol-bit-width = <5>;
 579                                         anatop-min-bit-val = <8>;
 580                                         anatop-min-voltage = <800000>;
 581                                         anatop-max-voltage = <1200000>;
 582                                         anatop-enable-bit = <0>;
 583                                 };
 584
 585                                 reg_1p2: regulator-vdd1p2 {
 586                                         compatible = "fsl,anatop-regulator";
 587                                         regulator-name = "vdd1p2";
 588                                         regulator-min-microvolt = <1100000>;
 589                                         regulator-max-microvolt = <1300000>;
 590                                         anatop-reg-offset = <0x220>;
 591                                         anatop-vol-bit-shift = <8>;
 592                                         anatop-vol-bit-width = <5>;
 593                                         anatop-min-bit-val = <0x14>;
 594                                         anatop-min-voltage = <1100000>;
 595                                         anatop-max-voltage = <1300000>;
 596                                         anatop-enable-bit = <0>;
 597                                 };
 598
 599                                 tempmon: tempmon {
 600                                         compatible = "fsl,imx7d-tempmon";
 601                                         interrupt-parent = <&gpc>;
 602                                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 603                                         fsl,tempmon = <&anatop>;
 604                                         nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
 605                                         nvmem-cell-names = "calib", "temp_grade";
 606                                         clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
 607                                 };
 608                         };
 609
 610                         snvs: snvs@30370000 {
 611                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 612                                 reg = <0x30370000 0x10000>;
 613
 614                                 snvs_rtc: snvs-rtc-lp {
 615                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 616                                         regmap = <&snvs>;
 617                                         offset = <0x34>;
 618                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 619                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 620                                         clocks = <&clks IMX7D_SNVS_CLK>;
 621                                         clock-names = "snvs-rtc";
 622                                 };
 623
 624                                 snvs_pwrkey: snvs-powerkey {
 625                                         compatible = "fsl,sec-v4.0-pwrkey";
 626                                         regmap = <&snvs>;
 627                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 628                                         clocks = <&clks IMX7D_SNVS_CLK>;
 629                                         clock-names = "snvs-pwrkey";
 630                                         linux,keycode = <KEY_POWER>;
 631                                         wakeup-source;
 632                                         status = "disabled";
 633                                 };
 634                         };
 635
 636                         clks: clock-controller@30380000 {
 637                                 compatible = "fsl,imx7d-ccm";
 638                                 reg = <0x30380000 0x10000>;
 639                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 640                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 641                                 #clock-cells = <1>;
 642                                 clocks = <&ckil>, <&osc>;
 643                                 clock-names = "ckil", "osc";
 644                         };
 645
 646                         src: reset-controller@30390000 {
 647                                 compatible = "fsl,imx7d-src", "syscon";
 648                                 reg = <0x30390000 0x10000>;
 649                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 650                                 #reset-cells = <1>;
 651                         };
 652
 653                         gpc: gpc@303a0000 {
 654                                 compatible = "fsl,imx7d-gpc";
 655                                 reg = <0x303a0000 0x10000>;
 656                                 interrupt-controller;
 657                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 658                                 #interrupt-cells = <3>;
 659                                 interrupt-parent = <&intc>;
 660                                 #power-domain-cells = <1>;
 661
 662                                 pgc {
 663                                         #address-cells = <1>;
 664                                         #size-cells = <0>;
 665
 666                                         pgc_mipi_phy: power-domain@0 {
 667                                                 #power-domain-cells = <0>;
 668                                                 reg = <0>;
 669                                                 power-supply = <&reg_1p0d>;
 670                                         };
 671
 672                                         pgc_pcie_phy: power-domain@1 {
 673                                                 #power-domain-cells = <0>;
 674                                                 reg = <1>;
 675                                                 power-supply = <&reg_1p0d>;
 676                                         };
 677
 678                                         pgc_hsic_phy: power-domain@2 {
 679                                                 #power-domain-cells = <0>;
 680                                                 reg = <2>;
 681                                                 power-supply = <&reg_1p2>;
 682                                         };
 683                                 };
 684                         };
 685                 };
 686
 687                 aips2: bus@30400000 {
 688                         compatible = "fsl,aips-bus", "simple-bus";
 689                         #address-cells = <1>;
 690                         #size-cells = <1>;
 691                         reg = <0x30400000 0x400000>;
 692                         ranges;
 693
 694                         adc1: adc@30610000 {
 695                                 compatible = "fsl,imx7d-adc";
 696                                 reg = <0x30610000 0x10000>;
 697                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 698                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 699                                 clock-names = "adc";
 700                                 #io-channel-cells = <1>;
 701                                 status = "disabled";
 702                         };
 703
 704                         adc2: adc@30620000 {
 705                                 compatible = "fsl,imx7d-adc";
 706                                 reg = <0x30620000 0x10000>;
 707                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 708                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 709                                 clock-names = "adc";
 710                                 #io-channel-cells = <1>;
 711                                 status = "disabled";
 712                         };
 713
 714                         ecspi4: spi@30630000 {
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 718                                 reg = <0x30630000 0x10000>;
 719                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 720                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 721                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
 722                                 clock-names = "ipg", "per";
 723                                 status = "disabled";
 724                         };
 725
 726                         ftm1: pwm@30640000 {
 727                                 compatible = "fsl,vf610-ftm-pwm";
 728                                 reg = <0x30640000 0x10000>;
 729                                 #pwm-cells = <3>;
 730                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clock-names = "ftm_sys", "ftm_ext",
 732                                 "ftm_fix", "ftm_cnt_clk_en";
 733                                 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
 734                                         <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
 735                                         <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
 736                                         <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
 737                                 status = "disabled";
 738                         };
 739
 740                         ftm2: pwm@30650000 {
 741                                 compatible = "fsl,vf610-ftm-pwm";
 742                                 reg = <0x30650000 0x10000>;
 743                                 #pwm-cells = <3>;
 744                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 745                                 clock-names = "ftm_sys", "ftm_ext",
 746                                 "ftm_fix", "ftm_cnt_clk_en";
 747                                 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
 748                                         <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
 749                                         <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
 750                                         <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
 751                                 status = "disabled";
 752                         };
 753
 754                         pwm1: pwm@30660000 {
 755                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 756                                 reg = <0x30660000 0x10000>;
 757                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 758                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 759                                          <&clks IMX7D_PWM1_ROOT_CLK>;
 760                                 clock-names = "ipg", "per";
 761                                 #pwm-cells = <3>;
 762                                 status = "disabled";
 763                         };
 764
 765                         pwm2: pwm@30670000 {
 766                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 767                                 reg = <0x30670000 0x10000>;
 768                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 769                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 770                                          <&clks IMX7D_PWM2_ROOT_CLK>;
 771                                 clock-names = "ipg", "per";
 772                                 #pwm-cells = <3>;
 773                                 status = "disabled";
 774                         };
 775
 776                         pwm3: pwm@30680000 {
 777                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 778                                 reg = <0x30680000 0x10000>;
 779                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 780                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 781                                          <&clks IMX7D_PWM3_ROOT_CLK>;
 782                                 clock-names = "ipg", "per";
 783                                 #pwm-cells = <3>;
 784                                 status = "disabled";
 785                         };
 786
 787                         pwm4: pwm@30690000 {
 788                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 789                                 reg = <0x30690000 0x10000>;
 790                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 791                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 792                                          <&clks IMX7D_PWM4_ROOT_CLK>;
 793                                 clock-names = "ipg", "per";
 794                                 #pwm-cells = <3>;
 795                                 status = "disabled";
 796                         };
 797
 798                         csi: csi@30710000 {
 799                                 compatible = "fsl,imx7-csi";
 800                                 reg = <0x30710000 0x10000>;
 801                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 802                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 803                                          <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
 804                                          <&clks IMX7D_CLK_DUMMY>;
 805                                 clock-names = "axi", "mclk", "dcic";
 806                                 status = "disabled";
 807
 808                                 port {
 809                                         csi_from_csi_mux: endpoint {
 810                                                 remote-endpoint = <&csi_mux_to_csi>;
 811                                         };
 812                                 };
 813                         };
 814
 815                         lcdif: lcdif@30730000 {
 816                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 817                                 reg = <0x30730000 0x10000>;
 818                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
 820                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
 821                                 clock-names = "pix", "axi";
 822                                 status = "disabled";
 823                         };
 824
 825                         mipi_csi: mipi-csi@30750000 {
 826                                 compatible = "fsl,imx7-mipi-csi2";
 827                                 reg = <0x30750000 0x10000>;
 828                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 829                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 830                                          <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
 831                                          <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
 832                                 clock-names = "pclk", "wrap", "phy";
 833                                 power-domains = <&pgc_mipi_phy>;
 834                                 phy-supply = <&reg_1p0d>;
 835                                 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
 836                                 status = "disabled";
 837
 838                                 ports {
 839                                         #address-cells = <1>;
 840                                         #size-cells = <0>;
 841
 842                                         port@0 {
 843                                                 reg = <0>;
 844                                         };
 845
 846                                         port@1 {
 847                                                 reg = <1>;
 848
 849                                                 mipi_vc0_to_csi_mux: endpoint {
 850                                                         remote-endpoint = <&csi_mux_from_mipi_vc0>;
 851                                                 };
 852                                         };
 853                                 };
 854                         };
 855                 };
 856
 857                 aips3: bus@30800000 {
 858                         compatible = "fsl,aips-bus", "simple-bus";
 859                         #address-cells = <1>;
 860                         #size-cells = <1>;
 861                         reg = <0x30800000 0x400000>;
 862                         ranges;
 863
 864                         spba-bus@30800000 {
 865                                 compatible = "fsl,spba-bus", "simple-bus";
 866                                 #address-cells = <1>;
 867                                 #size-cells = <1>;
 868                                 reg = <0x30800000 0x100000>;
 869                                 ranges;
 870
 871                                 ecspi1: spi@30820000 {
 872                                         #address-cells = <1>;
 873                                         #size-cells = <0>;
 874                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 875                                         reg = <0x30820000 0x10000>;
 876                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 877                                         clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 878                                                 <&clks IMX7D_ECSPI1_ROOT_CLK>;
 879                                         clock-names = "ipg", "per";
 880                                         status = "disabled";
 881                                 };
 882
 883                                 ecspi2: spi@30830000 {
 884                                         #address-cells = <1>;
 885                                         #size-cells = <0>;
 886                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 887                                         reg = <0x30830000 0x10000>;
 888                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 889                                         clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 890                                                 <&clks IMX7D_ECSPI2_ROOT_CLK>;
 891                                         clock-names = "ipg", "per";
 892                                         status = "disabled";
 893                                 };
 894
 895                                 ecspi3: spi@30840000 {
 896                                         #address-cells = <1>;
 897                                         #size-cells = <0>;
 898                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 899                                         reg = <0x30840000 0x10000>;
 900                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 901                                         clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 902                                                 <&clks IMX7D_ECSPI3_ROOT_CLK>;
 903                                         clock-names = "ipg", "per";
 904                                         status = "disabled";
 905                                 };
 906
 907                                 uart1: serial@30860000 {
 908                                         compatible = "fsl,imx7d-uart",
 909                                                      "fsl,imx6q-uart";
 910                                         reg = <0x30860000 0x10000>;
 911                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 912                                         clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 913                                                 <&clks IMX7D_UART1_ROOT_CLK>;
 914                                         clock-names = "ipg", "per";
 915                                         status = "disabled";
 916                                 };
 917
 918                                 uart2: serial@30890000 {
 919                                         compatible = "fsl,imx7d-uart",
 920                                                      "fsl,imx6q-uart";
 921                                         reg = <0x30890000 0x10000>;
 922                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 923                                         clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 924                                                 <&clks IMX7D_UART2_ROOT_CLK>;
 925                                         clock-names = "ipg", "per";
 926                                         status = "disabled";
 927                                 };
 928
 929                                 uart3: serial@30880000 {
 930                                         compatible = "fsl,imx7d-uart",
 931                                                      "fsl,imx6q-uart";
 932                                         reg = <0x30880000 0x10000>;
 933                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 934                                         clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 935                                                 <&clks IMX7D_UART3_ROOT_CLK>;
 936                                         clock-names = "ipg", "per";
 937                                         status = "disabled";
 938                                 };
 939
 940                                 sai1: sai@308a0000 {
 941                                         #sound-dai-cells = <0>;
 942                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 943                                         reg = <0x308a0000 0x10000>;
 944                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 945                                         clocks = <&clks IMX7D_SAI1_IPG_CLK>,
 946                                                  <&clks IMX7D_SAI1_ROOT_CLK>,
 947                                                  <&clks IMX7D_CLK_DUMMY>,
 948                                                  <&clks IMX7D_CLK_DUMMY>;
 949                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 950                                         dma-names = "rx", "tx";
 951                                         dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
 952                                         status = "disabled";
 953                                 };
 954
 955                                 sai2: sai@308b0000 {
 956                                         #sound-dai-cells = <0>;
 957                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 958                                         reg = <0x308b0000 0x10000>;
 959                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 960                                         clocks = <&clks IMX7D_SAI2_IPG_CLK>,
 961                                                  <&clks IMX7D_SAI2_ROOT_CLK>,
 962                                                  <&clks IMX7D_CLK_DUMMY>,
 963                                                  <&clks IMX7D_CLK_DUMMY>;
 964                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 965                                         dma-names = "rx", "tx";
 966                                         dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
 967                                         status = "disabled";
 968                                 };
 969
 970                                 sai3: sai@308c0000 {
 971                                         #sound-dai-cells = <0>;
 972                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
 973                                         reg = <0x308c0000 0x10000>;
 974                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 975                                         clocks = <&clks IMX7D_SAI3_IPG_CLK>,
 976                                                  <&clks IMX7D_SAI3_ROOT_CLK>,
 977                                                  <&clks IMX7D_CLK_DUMMY>,
 978                                                  <&clks IMX7D_CLK_DUMMY>;
 979                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 980                                         dma-names = "rx", "tx";
 981                                         dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
 982                                         status = "disabled";
 983                                 };
 984                         };
 985
 986                         crypto: crypto@30900000 {
 987                                 compatible = "fsl,sec-v4.0";
 988                                 #address-cells = <1>;
 989                                 #size-cells = <1>;
 990                                 reg = <0x30900000 0x40000>;
 991                                 ranges = <0 0x30900000 0x40000>;
 992                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 993                                 clocks = <&clks IMX7D_CAAM_CLK>,
 994                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
 995                                 clock-names = "ipg", "aclk";
 996
 997                                 sec_jr0: jr@1000 {
 998                                         compatible = "fsl,sec-v4.0-job-ring";
 999                                         reg = <0x1000 0x1000>;
1000                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1001                                 };
1002
1003                                 sec_jr1: jr@2000 {
1004                                         compatible = "fsl,sec-v4.0-job-ring";
1005                                         reg = <0x2000 0x1000>;
1006                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1007                                 };
1008
1009                                 sec_jr2: jr@3000 {
1010                                         compatible = "fsl,sec-v4.0-job-ring";
1011                                         reg = <0x3000 0x1000>;
1012                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1013                                 };
1014                         };
1015
1016                         flexcan1: can@30a00000 {
1017                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1018                                 reg = <0x30a00000 0x10000>;
1019                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1020                                 clocks = <&clks IMX7D_CLK_DUMMY>,
1021                                         <&clks IMX7D_CAN1_ROOT_CLK>;
1022                                 clock-names = "ipg", "per";
1023                                 fsl,stop-mode = <&gpr 0x10 1>;
1024                                 status = "disabled";
1025                         };
1026
1027                         flexcan2: can@30a10000 {
1028                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1029                                 reg = <0x30a10000 0x10000>;
1030                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1031                                 clocks = <&clks IMX7D_CLK_DUMMY>,
1032                                         <&clks IMX7D_CAN2_ROOT_CLK>;
1033                                 clock-names = "ipg", "per";
1034                                 fsl,stop-mode = <&gpr 0x10 2>;
1035                                 status = "disabled";
1036                         };
1037
1038                         i2c1: i2c@30a20000 {
1039                                 #address-cells = <1>;
1040                                 #size-cells = <0>;
1041                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1042                                 reg = <0x30a20000 0x10000>;
1043                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1044                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1045                                 status = "disabled";
1046                         };
1047
1048                         i2c2: i2c@30a30000 {
1049                                 #address-cells = <1>;
1050                                 #size-cells = <0>;
1051                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1052                                 reg = <0x30a30000 0x10000>;
1053                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1054                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1055                                 status = "disabled";
1056                         };
1057
1058                         i2c3: i2c@30a40000 {
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1062                                 reg = <0x30a40000 0x10000>;
1063                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1064                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1065                                 status = "disabled";
1066                         };
1067
1068                         i2c4: i2c@30a50000 {
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1072                                 reg = <0x30a50000 0x10000>;
1073                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1074                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1075                                 status = "disabled";
1076                         };
1077
1078                         uart4: serial@30a60000 {
1079                                 compatible = "fsl,imx7d-uart",
1080                                              "fsl,imx6q-uart";
1081                                 reg = <0x30a60000 0x10000>;
1082                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1083                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1084                                         <&clks IMX7D_UART4_ROOT_CLK>;
1085                                 clock-names = "ipg", "per";
1086                                 status = "disabled";
1087                         };
1088
1089                         uart5: serial@30a70000 {
1090                                 compatible = "fsl,imx7d-uart",
1091                                              "fsl,imx6q-uart";
1092                                 reg = <0x30a70000 0x10000>;
1093                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1094                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1095                                         <&clks IMX7D_UART5_ROOT_CLK>;
1096                                 clock-names = "ipg", "per";
1097                                 status = "disabled";
1098                         };
1099
1100                         uart6: serial@30a80000 {
1101                                 compatible = "fsl,imx7d-uart",
1102                                              "fsl,imx6q-uart";
1103                                 reg = <0x30a80000 0x10000>;
1104                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1105                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1106                                         <&clks IMX7D_UART6_ROOT_CLK>;
1107                                 clock-names = "ipg", "per";
1108                                 status = "disabled";
1109                         };
1110
1111                         uart7: serial@30a90000 {
1112                                 compatible = "fsl,imx7d-uart",
1113                                              "fsl,imx6q-uart";
1114                                 reg = <0x30a90000 0x10000>;
1115                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1116                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1117                                         <&clks IMX7D_UART7_ROOT_CLK>;
1118                                 clock-names = "ipg", "per";
1119                                 status = "disabled";
1120                         };
1121
1122                         mu0a: mailbox@30aa0000 {
1123                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1124                                 reg = <0x30aa0000 0x10000>;
1125                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1126                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1127                                 #mbox-cells = <2>;
1128                                 status = "disabled";
1129                         };
1130
1131                         mu0b: mailbox@30ab0000 {
1132                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1133                                 reg = <0x30ab0000 0x10000>;
1134                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1135                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1136                                 #mbox-cells = <2>;
1137                                 fsl,mu-side-b;
1138                                 status = "disabled";
1139                         };
1140
1141                         usbotg1: usb@30b10000 {
1142                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1143                                 reg = <0x30b10000 0x200>;
1144                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1145                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1146                                 fsl,usbphy = <&usbphynop1>;
1147                                 fsl,usbmisc = <&usbmisc1 0>;
1148                                 phy-clkgate-delay-us = <400>;
1149                                 status = "disabled";
1150                         };
1151
1152                         usbh: usb@30b30000 {
1153                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1154                                 reg = <0x30b30000 0x200>;
1155                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1156                                 power-domains = <&pgc_hsic_phy>;
1157                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1158                                 fsl,usbphy = <&usbphynop3>;
1159                                 fsl,usbmisc = <&usbmisc3 0>;
1160                                 phy_type = "hsic";
1161                                 dr_mode = "host";
1162                                 phy-clkgate-delay-us = <400>;
1163                                 status = "disabled";
1164                         };
1165
1166                         usbmisc1: usbmisc@30b10200 {
1167                                 #index-cells = <1>;
1168                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1169                                 reg = <0x30b10200 0x200>;
1170                         };
1171
1172                         usbmisc3: usbmisc@30b30200 {
1173                                 #index-cells = <1>;
1174                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1175                                 reg = <0x30b30200 0x200>;
1176                         };
1177
1178                         usdhc1: mmc@30b40000 {
1179                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1180                                 reg = <0x30b40000 0x10000>;
1181                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1182                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1183                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1184                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
1185                                 clock-names = "ipg", "ahb", "per";
1186                                 bus-width = <4>;
1187                                 status = "disabled";
1188                         };
1189
1190                         usdhc2: mmc@30b50000 {
1191                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1192                                 reg = <0x30b50000 0x10000>;
1193                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1195                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1196                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
1197                                 clock-names = "ipg", "ahb", "per";
1198                                 bus-width = <4>;
1199                                 status = "disabled";
1200                         };
1201
1202                         usdhc3: mmc@30b60000 {
1203                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1204                                 reg = <0x30b60000 0x10000>;
1205                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1206                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1207                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1208                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
1209                                 clock-names = "ipg", "ahb", "per";
1210                                 bus-width = <4>;
1211                                 status = "disabled";
1212                         };
1213
1214                         qspi: spi@30bb0000 {
1215                                 compatible = "fsl,imx7d-qspi";
1216                                 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1217                                 reg-names = "QuadSPI", "QuadSPI-memory";
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1221                                 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1222                                         <&clks IMX7D_QSPI_ROOT_CLK>;
1223                                 clock-names = "qspi_en", "qspi";
1224                                 status = "disabled";
1225                         };
1226
1227                         sdma: sdma@30bd0000 {
1228                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1229                                 reg = <0x30bd0000 0x10000>;
1230                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1231                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1232                                          <&clks IMX7D_SDMA_CORE_CLK>;
1233                                 clock-names = "ipg", "ahb";
1234                                 #dma-cells = <3>;
1235                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1236                         };
1237
1238                         fec1: ethernet@30be0000 {
1239                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1240                                 reg = <0x30be0000 0x10000>;
1241                                 interrupt-names = "int0", "int1", "int2", "pps";
1242                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1243                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1244                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1245                                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1246                                 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1247                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1248                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1249                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1250                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1251                                 clock-names = "ipg", "ahb", "ptp",
1252                                         "enet_clk_ref", "enet_out";
1253                                 fsl,num-tx-queues = <3>;
1254                                 fsl,num-rx-queues = <3>;
1255                                 fsl,stop-mode = <&gpr 0x10 3>;
1256                                 status = "disabled";
1257                         };
1258                 };
1259
1260                 dma_apbh: dma-apbh@33000000 {
1261                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1262                         reg = <0x33000000 0x2000>;
1263                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1264                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1267                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1268                         #dma-cells = <1>;
1269                         dma-channels = <4>;
1270                         clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1271                 };
1272
1273                 gpmi: nand-controller@33002000{
1274                         compatible = "fsl,imx7d-gpmi-nand";
1275                         #address-cells = <1>;
1276                         #size-cells = <1>;
1277                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1278                         reg-names = "gpmi-nand", "bch";
1279                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1280                         interrupt-names = "bch";
1281                         clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1282                                 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1283                         clock-names = "gpmi_io", "gpmi_bch_apb";
1284                         dmas = <&dma_apbh 0>;
1285                         dma-names = "rx-tx";
1286                         status = "disabled";
1287                         assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1288                         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1289                 };
1290         };
1291 };