arch/arm/boot/dts/imx6ul.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6ul-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6ul-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          */
  19         chosen {};
  20
  21         aliases {
  22                 ethernet0 = &fec1;
  23                 ethernet1 = &fec2;
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 gpio4 = &gpio5;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 i2c3 = &i2c4;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 serial5 = &uart6;
  41                 serial6 = &uart7;
  42                 serial7 = &uart8;
  43                 sai1 = &sai1;
  44                 sai2 = &sai2;
  45                 sai3 = &sai3;
  46                 spi0 = &ecspi1;
  47                 spi1 = &ecspi2;
  48                 spi2 = &ecspi3;
  49                 spi3 = &ecspi4;
  50                 usb0 = &usbotg1;
  51                 usb1 = &usbotg2;
  52                 usbphy0 = &usbphy1;
  53                 usbphy1 = &usbphy2;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@0 {
  61                         compatible = "arm,cortex-a7";
  62                         device_type = "cpu";
  63                         reg = <0>;
  64                         clock-frequency = <696000000>;
  65                         clock-latency = <61036>; /* two CLK32 periods */
  66                         #cooling-cells = <2>;
  67                         operating-points =
  68                                 /* kHz  uV */
  69                                 <696000 1275000>,
  70                                 <528000 1175000>,
  71                                 <396000 1025000>,
  72                                 <198000 950000>;
  73                         fsl,soc-operating-points =
  74                                 /* KHz  uV */
  75                                 <696000 1275000>,
  76                                 <528000 1175000>,
  77                                 <396000 1175000>,
  78                                 <198000 1175000>;
  79                         clocks = <&clks IMX6UL_CLK_ARM>,
  80                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  81                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  82                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  83                                  <&clks IMX6UL_CLK_STEP>,
  84                                  <&clks IMX6UL_CLK_PLL1_SW>,
  85                                  <&clks IMX6UL_CLK_PLL1_SYS>;
  86                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  87                                       "secondary_sel", "step", "pll1_sw",
  88                                       "pll1_sys";
  89                         arm-supply = <&reg_arm>;
  90                         soc-supply = <&reg_soc>;
  91                         nvmem-cells = <&cpu_speed_grade>;
  92                         nvmem-cell-names = "speed_grade";
  93                 };
  94         };
  95
  96         timer {
  97                 compatible = "arm,armv7-timer";
  98                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 100                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 101                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 102                 interrupt-parent = <&intc>;
 103                 status = "disabled";
 104         };
 105
 106         ckil: clock-cli {
 107                 compatible = "fixed-clock";
 108                 #clock-cells = <0>;
 109                 clock-frequency = <32768>;
 110                 clock-output-names = "ckil";
 111         };
 112
 113         osc: clock-osc {
 114                 compatible = "fixed-clock";
 115                 #clock-cells = <0>;
 116                 clock-frequency = <24000000>;
 117                 clock-output-names = "osc";
 118         };
 119
 120         ipp_di0: clock-di0 {
 121                 compatible = "fixed-clock";
 122                 #clock-cells = <0>;
 123                 clock-frequency = <0>;
 124                 clock-output-names = "ipp_di0";
 125         };
 126
 127         ipp_di1: clock-di1 {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <0>;
 131                 clock-output-names = "ipp_di1";
 132         };
 133
 134         pmu {
 135                 compatible = "arm,cortex-a7-pmu";
 136                 interrupt-parent = <&gpc>;
 137                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 138         };
 139
 140         soc: soc {
 141                 #address-cells = <1>;
 142                 #size-cells = <1>;
 143                 compatible = "simple-bus";
 144                 interrupt-parent = <&gpc>;
 145                 ranges;
 146
 147                 ocram: sram@900000 {
 148                         compatible = "mmio-sram";
 149                         reg = <0x00900000 0x20000>;
 150                         ranges = <0 0x00900000 0x20000>;
 151                         #address-cells = <1>;
 152                         #size-cells = <1>;
 153                 };
 154
 155                 intc: interrupt-controller@a01000 {
 156                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 157                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 158                         #interrupt-cells = <3>;
 159                         interrupt-controller;
 160                         interrupt-parent = <&intc>;
 161                         reg = <0x00a01000 0x1000>,
 162                               <0x00a02000 0x2000>,
 163                               <0x00a04000 0x2000>,
 164                               <0x00a06000 0x2000>;
 165                 };
 166
 167                 dma_apbh: dma-controller@1804000 {
 168                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 169                         reg = <0x01804000 0x2000>;
 170                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 172                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 174                         #dma-cells = <1>;
 175                         dma-channels = <4>;
 176                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 177                 };
 178
 179                 gpmi: nand-controller@1806000 {
 180                         compatible = "fsl,imx6q-gpmi-nand";
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 184                         reg-names = "gpmi-nand", "bch";
 185                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 186                         interrupt-names = "bch";
 187                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 188                                  <&clks IMX6UL_CLK_GPMI_APB>,
 189                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 190                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 191                                  <&clks IMX6UL_CLK_PER_BCH>;
 192                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 193                                       "gpmi_bch_apb", "per1_bch";
 194                         dmas = <&dma_apbh 0>;
 195                         dma-names = "rx-tx";
 196                         status = "disabled";
 197                 };
 198
 199                 aips1: bus@2000000 {
 200                         compatible = "fsl,aips-bus", "simple-bus";
 201                         #address-cells = <1>;
 202                         #size-cells = <1>;
 203                         reg = <0x02000000 0x100000>;
 204                         ranges;
 205
 206                         spba-bus@2000000 {
 207                                 compatible = "fsl,spba-bus", "simple-bus";
 208                                 #address-cells = <1>;
 209                                 #size-cells = <1>;
 210                                 reg = <0x02000000 0x40000>;
 211                                 ranges;
 212
 213                                 ecspi1: spi@2008000 {
 214                                         #address-cells = <1>;
 215                                         #size-cells = <0>;
 216                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 217                                         reg = <0x02008000 0x4000>;
 218                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 219                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 220                                                  <&clks IMX6UL_CLK_ECSPI1>;
 221                                         clock-names = "ipg", "per";
 222                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 223                                         dma-names = "rx", "tx";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ecspi2: spi@200c000 {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 231                                         reg = <0x0200c000 0x4000>;
 232                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 234                                                  <&clks IMX6UL_CLK_ECSPI2>;
 235                                         clock-names = "ipg", "per";
 236                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 237                                         dma-names = "rx", "tx";
 238                                         status = "disabled";
 239                                 };
 240
 241                                 ecspi3: spi@2010000 {
 242                                         #address-cells = <1>;
 243                                         #size-cells = <0>;
 244                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 245                                         reg = <0x02010000 0x4000>;
 246                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 248                                                  <&clks IMX6UL_CLK_ECSPI3>;
 249                                         clock-names = "ipg", "per";
 250                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 251                                         dma-names = "rx", "tx";
 252                                         status = "disabled";
 253                                 };
 254
 255                                 ecspi4: spi@2014000 {
 256                                         #address-cells = <1>;
 257                                         #size-cells = <0>;
 258                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 259                                         reg = <0x02014000 0x4000>;
 260                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 261                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 262                                                  <&clks IMX6UL_CLK_ECSPI4>;
 263                                         clock-names = "ipg", "per";
 264                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 265                                         dma-names = "rx", "tx";
 266                                         status = "disabled";
 267                                 };
 268
 269                                 uart7: serial@2018000 {
 270                                         compatible = "fsl,imx6ul-uart",
 271                                                      "fsl,imx6q-uart";
 272                                         reg = <0x02018000 0x4000>;
 273                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 274                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 275                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 276                                         clock-names = "ipg", "per";
 277                                         status = "disabled";
 278                                 };
 279
 280                                 uart1: serial@2020000 {
 281                                         compatible = "fsl,imx6ul-uart",
 282                                                      "fsl,imx6q-uart";
 283                                         reg = <0x02020000 0x4000>;
 284                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 286                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 287                                         clock-names = "ipg", "per";
 288                                         status = "disabled";
 289                                 };
 290
 291                                 uart8: serial@2024000 {
 292                                         compatible = "fsl,imx6ul-uart",
 293                                                      "fsl,imx6q-uart";
 294                                         reg = <0x02024000 0x4000>;
 295                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 296                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 297                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 298                                         clock-names = "ipg", "per";
 299                                         status = "disabled";
 300                                 };
 301
 302                                 sai1: sai@2028000 {
 303                                         #sound-dai-cells = <0>;
 304                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 305                                         reg = <0x02028000 0x4000>;
 306                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 307                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 308                                                  <&clks IMX6UL_CLK_SAI1>,
 309                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 310                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 311                                         dmas = <&sdma 35 24 0>,
 312                                                <&sdma 36 24 0>;
 313                                         dma-names = "rx", "tx";
 314                                         status = "disabled";
 315                                 };
 316
 317                                 sai2: sai@202c000 {
 318                                         #sound-dai-cells = <0>;
 319                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 320                                         reg = <0x0202c000 0x4000>;
 321                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 322                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 323                                                  <&clks IMX6UL_CLK_SAI2>,
 324                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 325                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 326                                         dmas = <&sdma 37 24 0>,
 327                                                <&sdma 38 24 0>;
 328                                         dma-names = "rx", "tx";
 329                                         status = "disabled";
 330                                 };
 331
 332                                 sai3: sai@2030000 {
 333                                         #sound-dai-cells = <0>;
 334                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 335                                         reg = <0x02030000 0x4000>;
 336                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 337                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 338                                                  <&clks IMX6UL_CLK_SAI3>,
 339                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 340                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 341                                         dmas = <&sdma 39 24 0>,
 342                                                <&sdma 40 24 0>;
 343                                         dma-names = "rx", "tx";
 344                                         status = "disabled";
 345                                 };
 346
 347                                 asrc: asrc@2034000 {
 348                                         compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
 349                                         reg = <0x2034000 0x4000>;
 350                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 351                                         clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
 352                                                 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
 353                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 354                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 355                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 356                                                 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 357                                                 <&clks IMX6UL_CLK_SPBA>;
 358                                         clock-names = "mem", "ipg", "asrck_0",
 359                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 360                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 361                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 362                                                 "asrck_d", "asrck_e", "asrck_f", "spba";
 363                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 364                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 365                                         dma-names = "rxa", "rxb", "rxc",
 366                                                     "txa", "txb", "txc";
 367                                         fsl,asrc-rate  = <48000>;
 368                                         fsl,asrc-width = <16>;
 369                                         status = "okay";
 370                                 };
 371                         };
 372
 373                         tsc: tsc@2040000 {
 374                                 compatible = "fsl,imx6ul-tsc";
 375                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 376                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 377                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 378                                 clocks = <&clks IMX6UL_CLK_IPG>,
 379                                          <&clks IMX6UL_CLK_ADC2>;
 380                                 clock-names = "tsc", "adc";
 381                                 status = "disabled";
 382                         };
 383
 384                         pwm1: pwm@2080000 {
 385                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 386                                 reg = <0x02080000 0x4000>;
 387                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 388                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 389                                          <&clks IMX6UL_CLK_PWM1>;
 390                                 clock-names = "ipg", "per";
 391                                 #pwm-cells = <3>;
 392                                 status = "disabled";
 393                         };
 394
 395                         pwm2: pwm@2084000 {
 396                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 397                                 reg = <0x02084000 0x4000>;
 398                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 400                                          <&clks IMX6UL_CLK_PWM2>;
 401                                 clock-names = "ipg", "per";
 402                                 #pwm-cells = <3>;
 403                                 status = "disabled";
 404                         };
 405
 406                         pwm3: pwm@2088000 {
 407                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 408                                 reg = <0x02088000 0x4000>;
 409                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 410                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 411                                          <&clks IMX6UL_CLK_PWM3>;
 412                                 clock-names = "ipg", "per";
 413                                 #pwm-cells = <3>;
 414                                 status = "disabled";
 415                         };
 416
 417                         pwm4: pwm@208c000 {
 418                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 419                                 reg = <0x0208c000 0x4000>;
 420                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 422                                          <&clks IMX6UL_CLK_PWM4>;
 423                                 clock-names = "ipg", "per";
 424                                 #pwm-cells = <3>;
 425                                 status = "disabled";
 426                         };
 427
 428                         can1: can@2090000 {
 429                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 430                                 reg = <0x02090000 0x4000>;
 431                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 432                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 433                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 434                                 clock-names = "ipg", "per";
 435                                 fsl,stop-mode = <&gpr 0x10 1>;
 436                                 status = "disabled";
 437                         };
 438
 439                         can2: can@2094000 {
 440                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 441                                 reg = <0x02094000 0x4000>;
 442                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 443                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 444                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 445                                 clock-names = "ipg", "per";
 446                                 fsl,stop-mode = <&gpr 0x10 2>;
 447                                 status = "disabled";
 448                         };
 449
 450                         gpt1: timer@2098000 {
 451                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 452                                 reg = <0x02098000 0x4000>;
 453                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 454                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 455                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 456                                 clock-names = "ipg", "per";
 457                         };
 458
 459                         gpio1: gpio@209c000 {
 460                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 461                                 reg = <0x0209c000 0x4000>;
 462                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 463                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 464                                 clocks = <&clks IMX6UL_CLK_GPIO1>;
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 interrupt-controller;
 468                                 #interrupt-cells = <2>;
 469                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 470                                               <&iomuxc 16 33 16>;
 471                         };
 472
 473                         gpio2: gpio@20a0000 {
 474                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 475                                 reg = <0x020a0000 0x4000>;
 476                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 477                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 478                                 clocks = <&clks IMX6UL_CLK_GPIO2>;
 479                                 gpio-controller;
 480                                 #gpio-cells = <2>;
 481                                 interrupt-controller;
 482                                 #interrupt-cells = <2>;
 483                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 484                         };
 485
 486                         gpio3: gpio@20a4000 {
 487                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 488                                 reg = <0x020a4000 0x4000>;
 489                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 490                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 491                                 clocks = <&clks IMX6UL_CLK_GPIO3>;
 492                                 gpio-controller;
 493                                 #gpio-cells = <2>;
 494                                 interrupt-controller;
 495                                 #interrupt-cells = <2>;
 496                                 gpio-ranges = <&iomuxc 0 65 29>;
 497                         };
 498
 499                         gpio4: gpio@20a8000 {
 500                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 501                                 reg = <0x020a8000 0x4000>;
 502                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 503                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6UL_CLK_GPIO4>;
 505                                 gpio-controller;
 506                                 #gpio-cells = <2>;
 507                                 interrupt-controller;
 508                                 #interrupt-cells = <2>;
 509                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 510                         };
 511
 512                         gpio5: gpio@20ac000 {
 513                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 514                                 reg = <0x020ac000 0x4000>;
 515                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 516                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 517                                 clocks = <&clks IMX6UL_CLK_GPIO5>;
 518                                 gpio-controller;
 519                                 #gpio-cells = <2>;
 520                                 interrupt-controller;
 521                                 #interrupt-cells = <2>;
 522                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 523                         };
 524
 525                         fec2: ethernet@20b4000 {
 526                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 527                                 reg = <0x020b4000 0x4000>;
 528                                 interrupt-names = "int0", "pps";
 529                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 530                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 531                                 clocks = <&clks IMX6UL_CLK_ENET>,
 532                                          <&clks IMX6UL_CLK_ENET_AHB>,
 533                                          <&clks IMX6UL_CLK_ENET_PTP>,
 534                                          <&clks IMX6UL_CLK_ENET2_REF_SEL>;
 535                                 clock-names = "ipg", "ahb", "ptp",
 536                                               "enet_clk_ref";
 537                                 fsl,num-tx-queues = <1>;
 538                                 fsl,num-rx-queues = <1>;
 539                                 fsl,stop-mode = <&gpr 0x10 4>;
 540                                 fsl,magic-packet;
 541                                 status = "disabled";
 542                         };
 543
 544                         kpp: keypad@20b8000 {
 545                                 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
 546                                 reg = <0x020b8000 0x4000>;
 547                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 548                                 clocks = <&clks IMX6UL_CLK_KPP>;
 549                                 status = "disabled";
 550                         };
 551
 552                         wdog1: watchdog@20bc000 {
 553                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 554                                 reg = <0x020bc000 0x4000>;
 555                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 556                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 557                         };
 558
 559                         wdog2: watchdog@20c0000 {
 560                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 561                                 reg = <0x020c0000 0x4000>;
 562                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 563                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 564                                 status = "disabled";
 565                         };
 566
 567                         clks: clock-controller@20c4000 {
 568                                 compatible = "fsl,imx6ul-ccm";
 569                                 reg = <0x020c4000 0x4000>;
 570                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 571                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 572                                 #clock-cells = <1>;
 573                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 574                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 575                         };
 576
 577                         anatop: anatop@20c8000 {
 578                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 579                                              "syscon", "simple-mfd";
 580                                 reg = <0x020c8000 0x1000>;
 581                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 582                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 583                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 584
 585                                 reg_3p0: regulator-3p0 {
 586                                         compatible = "fsl,anatop-regulator";
 587                                         regulator-name = "vdd3p0";
 588                                         regulator-min-microvolt = <2625000>;
 589                                         regulator-max-microvolt = <3400000>;
 590                                         anatop-reg-offset = <0x120>;
 591                                         anatop-vol-bit-shift = <8>;
 592                                         anatop-vol-bit-width = <5>;
 593                                         anatop-min-bit-val = <0>;
 594                                         anatop-min-voltage = <2625000>;
 595                                         anatop-max-voltage = <3400000>;
 596                                         anatop-enable-bit = <0>;
 597                                 };
 598
 599                                 reg_arm: regulator-vddcore {
 600                                         compatible = "fsl,anatop-regulator";
 601                                         regulator-name = "cpu";
 602                                         regulator-min-microvolt = <725000>;
 603                                         regulator-max-microvolt = <1450000>;
 604                                         regulator-always-on;
 605                                         anatop-reg-offset = <0x140>;
 606                                         anatop-vol-bit-shift = <0>;
 607                                         anatop-vol-bit-width = <5>;
 608                                         anatop-delay-reg-offset = <0x170>;
 609                                         anatop-delay-bit-shift = <24>;
 610                                         anatop-delay-bit-width = <2>;
 611                                         anatop-min-bit-val = <1>;
 612                                         anatop-min-voltage = <725000>;
 613                                         anatop-max-voltage = <1450000>;
 614                                 };
 615
 616                                 reg_soc: regulator-vddsoc {
 617                                         compatible = "fsl,anatop-regulator";
 618                                         regulator-name = "vddsoc";
 619                                         regulator-min-microvolt = <725000>;
 620                                         regulator-max-microvolt = <1450000>;
 621                                         regulator-always-on;
 622                                         anatop-reg-offset = <0x140>;
 623                                         anatop-vol-bit-shift = <18>;
 624                                         anatop-vol-bit-width = <5>;
 625                                         anatop-delay-reg-offset = <0x170>;
 626                                         anatop-delay-bit-shift = <28>;
 627                                         anatop-delay-bit-width = <2>;
 628                                         anatop-min-bit-val = <1>;
 629                                         anatop-min-voltage = <725000>;
 630                                         anatop-max-voltage = <1450000>;
 631                                 };
 632
 633                                 tempmon: tempmon {
 634                                         compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 635                                         interrupt-parent = <&gpc>;
 636                                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 637                                         fsl,tempmon = <&anatop>;
 638                                         nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 639                                         nvmem-cell-names = "calib", "temp_grade";
 640                                         clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 641                                 };
 642                         };
 643
 644                         usbphy1: usbphy@20c9000 {
 645                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 646                                 reg = <0x020c9000 0x1000>;
 647                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 648                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 649                                 phy-3p0-supply = <&reg_3p0>;
 650                                 fsl,anatop = <&anatop>;
 651                         };
 652
 653                         usbphy2: usbphy@20ca000 {
 654                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 655                                 reg = <0x020ca000 0x1000>;
 656                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 658                                 phy-3p0-supply = <&reg_3p0>;
 659                                 fsl,anatop = <&anatop>;
 660                         };
 661
 662                         snvs: snvs@20cc000 {
 663                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 664                                 reg = <0x020cc000 0x4000>;
 665
 666                                 snvs_rtc: snvs-rtc-lp {
 667                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 668                                         regmap = <&snvs>;
 669                                         offset = <0x34>;
 670                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 671                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 672                                 };
 673
 674                                 snvs_poweroff: snvs-poweroff {
 675                                         compatible = "syscon-poweroff";
 676                                         regmap = <&snvs>;
 677                                         offset = <0x38>;
 678                                         value = <0x60>;
 679                                         mask = <0x60>;
 680                                         status = "disabled";
 681                                 };
 682
 683                                 snvs_pwrkey: snvs-powerkey {
 684                                         compatible = "fsl,sec-v4.0-pwrkey";
 685                                         regmap = <&snvs>;
 686                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 687                                         linux,keycode = <KEY_POWER>;
 688                                         wakeup-source;
 689                                         status = "disabled";
 690                                 };
 691
 692                                 snvs_lpgpr: snvs-lpgpr {
 693                                         compatible = "fsl,imx6ul-snvs-lpgpr";
 694                                 };
 695                         };
 696
 697                         epit1: epit@20d0000 {
 698                                 reg = <0x020d0000 0x4000>;
 699                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 700                         };
 701
 702                         epit2: epit@20d4000 {
 703                                 reg = <0x020d4000 0x4000>;
 704                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 705                         };
 706
 707                         src: reset-controller@20d8000 {
 708                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 709                                 reg = <0x020d8000 0x4000>;
 710                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 711                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 712                                 #reset-cells = <1>;
 713                         };
 714
 715                         gpc: gpc@20dc000 {
 716                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 717                                 reg = <0x020dc000 0x4000>;
 718                                 interrupt-controller;
 719                                 #interrupt-cells = <3>;
 720                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 721                                 interrupt-parent = <&intc>;
 722                                 clocks = <&clks IMX6UL_CLK_IPG>;
 723                                 clock-names = "ipg";
 724
 725                                 pgc {
 726                                         #address-cells = <1>;
 727                                         #size-cells = <0>;
 728
 729                                         power-domain@0 {
 730                                                 reg = <0>;
 731                                                 #power-domain-cells = <0>;
 732                                         };
 733                                 };
 734                         };
 735
 736                         iomuxc: pinctrl@20e0000 {
 737                                 compatible = "fsl,imx6ul-iomuxc";
 738                                 reg = <0x020e0000 0x4000>;
 739                         };
 740
 741                         gpr: iomuxc-gpr@20e4000 {
 742                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 743                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 744                                 reg = <0x020e4000 0x4000>;
 745                         };
 746
 747                         gpt2: timer@20e8000 {
 748                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 749                                 reg = <0x020e8000 0x4000>;
 750                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 751                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 752                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 753                                 clock-names = "ipg", "per";
 754                                 status = "disabled";
 755                         };
 756
 757                         sdma: dma-controller@20ec000 {
 758                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 759                                              "fsl,imx35-sdma";
 760                                 reg = <0x020ec000 0x4000>;
 761                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 762                                 clocks = <&clks IMX6UL_CLK_IPG>,
 763                                          <&clks IMX6UL_CLK_SDMA>;
 764                                 clock-names = "ipg", "ahb";
 765                                 #dma-cells = <3>;
 766                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 767                         };
 768
 769                         pwm5: pwm@20f0000 {
 770                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 771                                 reg = <0x020f0000 0x4000>;
 772                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 773                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 774                                          <&clks IMX6UL_CLK_PWM5>;
 775                                 clock-names = "ipg", "per";
 776                                 #pwm-cells = <3>;
 777                                 status = "disabled";
 778                         };
 779
 780                         pwm6: pwm@20f4000 {
 781                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 782                                 reg = <0x020f4000 0x4000>;
 783                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 784                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 785                                          <&clks IMX6UL_CLK_PWM6>;
 786                                 clock-names = "ipg", "per";
 787                                 #pwm-cells = <3>;
 788                                 status = "disabled";
 789                         };
 790
 791                         pwm7: pwm@20f8000 {
 792                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 793                                 reg = <0x020f8000 0x4000>;
 794                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 796                                          <&clks IMX6UL_CLK_PWM7>;
 797                                 clock-names = "ipg", "per";
 798                                 #pwm-cells = <3>;
 799                                 status = "disabled";
 800                         };
 801
 802                         pwm8: pwm@20fc000 {
 803                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 804                                 reg = <0x020fc000 0x4000>;
 805                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 806                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 807                                          <&clks IMX6UL_CLK_PWM8>;
 808                                 clock-names = "ipg", "per";
 809                                 #pwm-cells = <3>;
 810                                 status = "disabled";
 811                         };
 812                 };
 813
 814                 aips2: bus@2100000 {
 815                         compatible = "fsl,aips-bus", "simple-bus";
 816                         #address-cells = <1>;
 817                         #size-cells = <1>;
 818                         reg = <0x02100000 0x100000>;
 819                         ranges;
 820
 821                         crypto: crypto@2140000 {
 822                                 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
 823                                 #address-cells = <1>;
 824                                 #size-cells = <1>;
 825                                 reg = <0x2140000 0x3c000>;
 826                                 ranges = <0 0x2140000 0x3c000>;
 827                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 828                                 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
 829                                          <&clks IMX6UL_CLK_CAAM_MEM>;
 830                                 clock-names = "ipg", "aclk", "mem";
 831
 832                                 sec_jr0: jr@1000 {
 833                                         compatible = "fsl,sec-v4.0-job-ring";
 834                                         reg = <0x1000 0x1000>;
 835                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 836                                 };
 837
 838                                 sec_jr1: jr@2000 {
 839                                         compatible = "fsl,sec-v4.0-job-ring";
 840                                         reg = <0x2000 0x1000>;
 841                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 842                                 };
 843
 844                                 sec_jr2: jr@3000 {
 845                                         compatible = "fsl,sec-v4.0-job-ring";
 846                                         reg = <0x3000 0x1000>;
 847                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 848                                 };
 849                         };
 850
 851                         usbotg1: usb@2184000 {
 852                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 853                                 reg = <0x02184000 0x200>;
 854                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 856                                 fsl,usbphy = <&usbphy1>;
 857                                 fsl,usbmisc = <&usbmisc 0>;
 858                                 fsl,anatop = <&anatop>;
 859                                 ahb-burst-config = <0x0>;
 860                                 tx-burst-size-dword = <0x10>;
 861                                 rx-burst-size-dword = <0x10>;
 862                                 status = "disabled";
 863                         };
 864
 865                         usbotg2: usb@2184200 {
 866                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 867                                 reg = <0x02184200 0x200>;
 868                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 869                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 870                                 fsl,usbphy = <&usbphy2>;
 871                                 fsl,usbmisc = <&usbmisc 1>;
 872                                 ahb-burst-config = <0x0>;
 873                                 tx-burst-size-dword = <0x10>;
 874                                 rx-burst-size-dword = <0x10>;
 875                                 status = "disabled";
 876                         };
 877
 878                         usbmisc: usbmisc@2184800 {
 879                                 #index-cells = <1>;
 880                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 881                                 reg = <0x02184800 0x200>;
 882                         };
 883
 884                         fec1: ethernet@2188000 {
 885                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 886                                 reg = <0x02188000 0x4000>;
 887                                 interrupt-names = "int0", "pps";
 888                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 889                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 890                                 clocks = <&clks IMX6UL_CLK_ENET>,
 891                                          <&clks IMX6UL_CLK_ENET_AHB>,
 892                                          <&clks IMX6UL_CLK_ENET_PTP>,
 893                                          <&clks IMX6UL_CLK_ENET1_REF_SEL>;
 894                                 clock-names = "ipg", "ahb", "ptp",
 895                                               "enet_clk_ref";
 896                                 fsl,num-tx-queues = <1>;
 897                                 fsl,num-rx-queues = <1>;
 898                                 fsl,stop-mode = <&gpr 0x10 3>;
 899                                 fsl,magic-packet;
 900                                 status = "disabled";
 901                         };
 902
 903                         usdhc1: mmc@2190000 {
 904                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 905                                 reg = <0x02190000 0x4000>;
 906                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 907                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 908                                          <&clks IMX6UL_CLK_USDHC1>,
 909                                          <&clks IMX6UL_CLK_USDHC1>;
 910                                 clock-names = "ipg", "ahb", "per";
 911                                 fsl,tuning-step = <2>;
 912                                 fsl,tuning-start-tap = <20>;
 913                                 bus-width = <4>;
 914                                 status = "disabled";
 915                         };
 916
 917                         usdhc2: mmc@2194000 {
 918                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 919                                 reg = <0x02194000 0x4000>;
 920                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 921                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 922                                          <&clks IMX6UL_CLK_USDHC2>,
 923                                          <&clks IMX6UL_CLK_USDHC2>;
 924                                 clock-names = "ipg", "ahb", "per";
 925                                 bus-width = <4>;
 926                                 fsl,tuning-step = <2>;
 927                                 fsl,tuning-start-tap = <20>;
 928                                 status = "disabled";
 929                         };
 930
 931                         adc1: adc@2198000 {
 932                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 933                                 reg = <0x02198000 0x4000>;
 934                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 936                                 clock-names = "adc";
 937                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 938                                                          <20000000>;
 939                                 status = "disabled";
 940                         };
 941
 942                         i2c1: i2c@21a0000 {
 943                                 #address-cells = <1>;
 944                                 #size-cells = <0>;
 945                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 946                                 reg = <0x021a0000 0x4000>;
 947                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 948                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 949                                 status = "disabled";
 950                         };
 951
 952                         i2c2: i2c@21a4000 {
 953                                 #address-cells = <1>;
 954                                 #size-cells = <0>;
 955                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 956                                 reg = <0x021a4000 0x4000>;
 957                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 958                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 959                                 status = "disabled";
 960                         };
 961
 962                         i2c3: i2c@21a8000 {
 963                                 #address-cells = <1>;
 964                                 #size-cells = <0>;
 965                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 966                                 reg = <0x021a8000 0x4000>;
 967                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 968                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 969                                 status = "disabled";
 970                         };
 971
 972                         memory-controller@21b0000 {
 973                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 974                                 reg = <0x021b0000 0x4000>;
 975                                 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
 976                         };
 977
 978                         weim: weim@21b8000 {
 979                                 #address-cells = <2>;
 980                                 #size-cells = <1>;
 981                                 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
 982                                 reg = <0x021b8000 0x4000>;
 983                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 984                                 clocks = <&clks IMX6UL_CLK_EIM>;
 985                                 fsl,weim-cs-gpr = <&gpr>;
 986                                 status = "disabled";
 987                         };
 988
 989                         ocotp: efuse@21bc000 {
 990                                 #address-cells = <1>;
 991                                 #size-cells = <1>;
 992                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 993                                 reg = <0x021bc000 0x4000>;
 994                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 995
 996                                 tempmon_calib: calib@38 {
 997                                         reg = <0x38 4>;
 998                                 };
 999
1000                                 tempmon_temp_grade: temp-grade@20 {
1001                                         reg = <0x20 4>;
1002                                 };
1003
1004                                 cpu_speed_grade: speed-grade@10 {
1005                                         reg = <0x10 4>;
1006                                 };
1007                         };
1008
1009                         csi: csi@21c4000 {
1010                                 compatible = "fsl,imx6ul-csi";
1011                                 reg = <0x021c4000 0x4000>;
1012                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1013                                 clocks = <&clks IMX6UL_CLK_CSI>;
1014                                 clock-names = "mclk";
1015                                 status = "disabled";
1016                         };
1017
1018                         lcdif: lcdif@21c8000 {
1019                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
1020                                 reg = <0x021c8000 0x4000>;
1021                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1022                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
1023                                          <&clks IMX6UL_CLK_LCDIF_APB>,
1024                                          <&clks IMX6UL_CLK_DUMMY>;
1025                                 clock-names = "pix", "axi", "disp_axi";
1026                                 status = "disabled";
1027                         };
1028
1029                         pxp: pxp@21cc000 {
1030                                 compatible = "fsl,imx6ul-pxp";
1031                                 reg = <0x021cc000 0x4000>;
1032                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1033                                 clocks = <&clks IMX6UL_CLK_PXP>;
1034                                 clock-names = "axi";
1035                         };
1036
1037                         qspi: spi@21e0000 {
1038                                 #address-cells = <1>;
1039                                 #size-cells = <0>;
1040                                 compatible = "fsl,imx6ul-qspi";
1041                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1042                                 reg-names = "QuadSPI", "QuadSPI-memory";
1043                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1044                                 clocks = <&clks IMX6UL_CLK_QSPI>,
1045                                          <&clks IMX6UL_CLK_QSPI>;
1046                                 clock-names = "qspi_en", "qspi";
1047                                 status = "disabled";
1048                         };
1049
1050                         wdog3: watchdog@21e4000 {
1051                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1052                                 reg = <0x021e4000 0x4000>;
1053                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1054                                 clocks = <&clks IMX6UL_CLK_WDOG3>;
1055                                 status = "disabled";
1056                         };
1057
1058                         uart2: serial@21e8000 {
1059                                 compatible = "fsl,imx6ul-uart",
1060                                              "fsl,imx6q-uart";
1061                                 reg = <0x021e8000 0x4000>;
1062                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1063                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1064                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
1065                                 clock-names = "ipg", "per";
1066                                 status = "disabled";
1067                         };
1068
1069                         uart3: serial@21ec000 {
1070                                 compatible = "fsl,imx6ul-uart",
1071                                              "fsl,imx6q-uart";
1072                                 reg = <0x021ec000 0x4000>;
1073                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1074                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1075                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
1076                                 clock-names = "ipg", "per";
1077                                 status = "disabled";
1078                         };
1079
1080                         uart4: serial@21f0000 {
1081                                 compatible = "fsl,imx6ul-uart",
1082                                              "fsl,imx6q-uart";
1083                                 reg = <0x021f0000 0x4000>;
1084                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1085                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1086                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
1087                                 clock-names = "ipg", "per";
1088                                 status = "disabled";
1089                         };
1090
1091                         uart5: serial@21f4000 {
1092                                 compatible = "fsl,imx6ul-uart",
1093                                              "fsl,imx6q-uart";
1094                                 reg = <0x021f4000 0x4000>;
1095                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1096                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1097                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1098                                 clock-names = "ipg", "per";
1099                                 status = "disabled";
1100                         };
1101
1102                         i2c4: i2c@21f8000 {
1103                                 #address-cells = <1>;
1104                                 #size-cells = <0>;
1105                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1106                                 reg = <0x021f8000 0x4000>;
1107                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1108                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1109                                 status = "disabled";
1110                         };
1111
1112                         uart6: serial@21fc000 {
1113                                 compatible = "fsl,imx6ul-uart",
1114                                              "fsl,imx6q-uart";
1115                                 reg = <0x021fc000 0x4000>;
1116                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1117                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1118                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1119                                 clock-names = "ipg", "per";
1120                                 status = "disabled";
1121                         };
1122                 };
1123         };
1124 };