1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
11 device_type = "memory";
12 reg = <0x80000000 0x20000000>;
15 backlight_display: backlight-display {
16 compatible = "pwm-backlight";
17 pwms = <&pwm1 0 5000000>;
18 brightness-levels = <0 4 8 16 32 64 128 255>;
19 default-brightness-level = <6>;
24 reg_sd1_vmmc: regulator-sd1-vmmc {
25 compatible = "regulator-fixed";
26 regulator-name = "VSD_3V3";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
33 reg_peri_3v3: regulator-peri-3v3 {
34 compatible = "regulator-fixed";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_peri_3v3>;
37 regulator-name = "VPERI_3V3";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
42 * If you want to want to make this dynamic please
43 * check schematics and test all affected peripherals:
49 * - wm8960 audio codec
55 reg_can_3v3: regulator-can-3v3 {
56 compatible = "regulator-fixed";
57 regulator-name = "can-3v3";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
64 compatible = "fsl,imx-audio-wm8960";
65 model = "wm8960-audio";
67 audio-codec = <&codec>;
69 hp-det-gpio = <&gpio5 4 0>;
71 "Headphone Jack", "HP_L",
72 "Headphone Jack", "HP_R",
77 "LINPUT2", "Mic Jack",
78 "LINPUT3", "Mic Jack",
86 compatible = "spi-gpio";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_spi4>;
90 gpio-sck = <&gpio5 11 0>;
91 gpio-mosi = <&gpio5 10 0>;
92 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
93 num-chipselects = <1>;
98 compatible = "fairchild,74hc595";
102 registers-number = <1>;
103 spi-max-frequency = <100000>;
104 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
109 compatible = "innolux,at043tn24";
110 backlight = <&backlight_display>;
114 remote-endpoint = <&display_out>;
121 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
122 assigned-clock-rates = <786432000>;
126 clock-frequency = <100000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c2>;
132 #sound-dai-cells = <0>;
133 compatible = "wlf,wm8960";
136 wlf,hp-cfg = <3 2 3>;
137 wlf,gpio-cfg = <1 3>;
138 clocks = <&clks IMX6UL_CLK_SAI2>;
139 clock-names = "mclk";
143 compatible = "ovti,ov5640";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_camera_clock>;
147 clocks = <&clks IMX6UL_CLK_CSI>;
148 clock-names = "xclk";
149 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
150 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;
153 ov5640_to_parallel: endpoint {
154 remote-endpoint = <¶llel_from_ov5640>;
156 data-shift = <2>; /* lines 9:2 are used */
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_csi1>;
171 parallel_from_ov5640: endpoint {
172 remote-endpoint = <&ov5640_to_parallel>;
173 bus-type = <5>; /* Parallel bus */
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_enet1>;
182 phy-handle = <ðphy0>;
183 phy-supply = <®_peri_3v3>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_enet2>;
191 phy-handle = <ðphy1>;
192 phy-supply = <®_peri_3v3>;
196 #address-cells = <1>;
199 ethphy0: ethernet-phy@2 {
200 compatible = "ethernet-phy-id0022.1560";
202 micrel,led-mode = <1>;
203 clocks = <&clks IMX6UL_CLK_ENET_REF>;
204 clock-names = "rmii-ref";
208 ethphy1: ethernet-phy@1 {
209 compatible = "ethernet-phy-id0022.1560";
211 micrel,led-mode = <1>;
212 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
213 clock-names = "rmii-ref";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_flexcan1>;
221 xceiver-supply = <®_can_3v3>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_flexcan2>;
228 xceiver-supply = <®_can_3v3>;
235 gpios = <1 GPIO_ACTIVE_HIGH>;
237 line-name = "eth0-phy";
242 gpios = <2 GPIO_ACTIVE_HIGH>;
244 line-name = "eth1-phy";
249 clock-frequency = <100000>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_i2c1>;
255 compatible = "fsl,mag3110";
257 vdd-supply = <®_peri_3v3>;
258 vddio-supply = <®_peri_3v3>;
263 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
264 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_lcdif_dat
267 &pinctrl_lcdif_ctrl>;
271 display_out: endpoint {
272 remote-endpoint = <&panel_in>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_pwm1>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_qspi>;
290 #address-cells = <1>;
292 compatible = "micron,n25q256a", "jedec,spi-nor";
293 spi-max-frequency = <29000000>;
294 spi-rx-bus-width = <4>;
295 spi-tx-bus-width = <4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_sai2>;
303 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
304 <&clks IMX6UL_CLK_SAI2>;
305 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
306 assigned-clock-rates = <0>, <12288000>;
307 fsl,sai-mclk-direction-output;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_tsc>;
322 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
323 measure-delay-time = <0xffff>;
324 pre-charge-time = <0xfff>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_uart1>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_uart2>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_usb_otg1>;
350 disable-over-current;
355 fsl,tx-d-cal = <106>;
359 fsl,tx-d-cal = <106>;
363 pinctrl-names = "default", "state_100mhz", "state_200mhz";
364 pinctrl-0 = <&pinctrl_usdhc1>;
365 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
366 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
367 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
368 keep-power-in-suspend;
370 vmmc-supply = <®_sd1_vmmc>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_usdhc2>;
379 keep-power-in-suspend;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_wdog>;
387 fsl,ext-reset-output;
391 pinctrl-names = "default";
393 pinctrl_camera_clock: cameraclockgrp {
395 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
399 pinctrl_csi1: csi1grp {
401 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
402 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
403 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
404 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
405 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
406 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
407 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
408 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
409 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
410 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
411 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
415 pinctrl_enet1: enet1grp {
417 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
418 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
419 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
420 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
421 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
422 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
423 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
424 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
428 pinctrl_enet2: enet2grp {
430 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
431 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
432 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
433 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
434 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
435 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
436 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
437 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
438 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
439 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
443 pinctrl_flexcan1: flexcan1grp{
445 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
446 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
450 pinctrl_flexcan2: flexcan2grp{
452 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
453 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
457 pinctrl_i2c1: i2c1grp {
459 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
460 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
464 pinctrl_i2c2: i2c2grp {
466 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
467 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
471 pinctrl_lcdif_dat: lcdifdatgrp {
473 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
474 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
475 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
476 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
477 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
478 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
479 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
480 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
481 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
482 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
483 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
484 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
485 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
486 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
487 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
488 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
489 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
490 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
491 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
492 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
493 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
494 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
495 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
496 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
500 pinctrl_lcdif_ctrl: lcdifctrlgrp {
502 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
503 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
504 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
505 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
506 /* used for lcd reset */
507 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
511 pinctrl_qspi: qspigrp {
513 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
514 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
515 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
516 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
517 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
518 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
522 pinctrl_sai2: sai2grp {
524 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
525 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
526 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
527 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
528 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
529 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
533 pinctrl_peri_3v3: peri3v3grp {
535 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
539 pinctrl_pwm1: pwm1grp {
541 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
545 pinctrl_sim2: sim2grp {
547 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
548 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
549 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
550 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
551 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
552 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
556 pinctrl_spi4: spi4grp {
558 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
559 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
560 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
561 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
565 pinctrl_tsc: tscgrp {
567 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
568 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
569 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
570 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
574 pinctrl_uart1: uart1grp {
576 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
577 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
581 pinctrl_uart2: uart2grp {
583 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
584 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
585 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
586 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
590 pinctrl_usb_otg1: usbotg1grp {
592 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
596 pinctrl_usdhc1: usdhc1grp {
598 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
599 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
600 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
601 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
602 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
603 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
604 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
605 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
606 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
610 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
612 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
613 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
614 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
615 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
616 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
617 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
622 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
624 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
625 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
626 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
627 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
628 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
629 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
633 pinctrl_usdhc2: usdhc2grp {
635 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
636 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
637 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
638 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
639 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
640 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
644 pinctrl_wdog: wdoggrp {
646 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0