arch/arm/boot/dts/imx6sx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2014 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6sx-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6sx-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          */
  19         chosen {};
  20
  21         aliases {
  22                 can0 = &flexcan1;
  23                 can1 = &flexcan2;
  24                 ethernet0 = &fec1;
  25                 ethernet1 = &fec2;
  26                 gpio0 = &gpio1;
  27                 gpio1 = &gpio2;
  28                 gpio2 = &gpio3;
  29                 gpio3 = &gpio4;
  30                 gpio4 = &gpio5;
  31                 gpio5 = &gpio6;
  32                 gpio6 = &gpio7;
  33                 i2c0 = &i2c1;
  34                 i2c1 = &i2c2;
  35                 i2c2 = &i2c3;
  36                 i2c3 = &i2c4;
  37                 mmc0 = &usdhc1;
  38                 mmc1 = &usdhc2;
  39                 mmc2 = &usdhc3;
  40                 mmc3 = &usdhc4;
  41                 serial0 = &uart1;
  42                 serial1 = &uart2;
  43                 serial2 = &uart3;
  44                 serial3 = &uart4;
  45                 serial4 = &uart5;
  46                 serial5 = &uart6;
  47                 spi0 = &ecspi1;
  48                 spi1 = &ecspi2;
  49                 spi2 = &ecspi3;
  50                 spi3 = &ecspi4;
  51                 spi4 = &ecspi5;
  52                 usb0 = &usbotg1;
  53                 usb1 = &usbotg2;
  54                 usb2 = &usbh;
  55                 usbphy0 = &usbphy1;
  56                 usbphy1 = &usbphy2;
  57         };
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@0 {
  64                         compatible = "arm,cortex-a9";
  65                         device_type = "cpu";
  66                         reg = <0>;
  67                         next-level-cache = <&L2>;
  68                         operating-points = <
  69                                 /* kHz    uV */
  70                                 996000  1250000
  71                                 792000  1175000
  72                                 396000  1075000
  73                                 198000  975000
  74                         >;
  75                         fsl,soc-operating-points = <
  76                                 /* ARM kHz  SOC uV */
  77                                 996000      1175000
  78                                 792000      1175000
  79                                 396000      1175000
  80                                 198000      1175000
  81                         >;
  82                         clock-latency = <61036>; /* two CLK32 periods */
  83                         #cooling-cells = <2>;
  84                         clocks = <&clks IMX6SX_CLK_ARM>,
  85                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  86                                  <&clks IMX6SX_CLK_STEP>,
  87                                  <&clks IMX6SX_CLK_PLL1_SW>,
  88                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  89                         clock-names = "arm", "pll2_pfd2_396m", "step",
  90                                       "pll1_sw", "pll1_sys";
  91                         arm-supply = <&reg_arm>;
  92                         soc-supply = <&reg_soc>;
  93                         nvmem-cells = <&cpu_speed_grade>;
  94                         nvmem-cell-names = "speed_grade";
  95                 };
  96         };
  97
  98         ckil: clock-ckil {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <32768>;
 102                 clock-output-names = "ckil";
 103         };
 104
 105         osc: clock-osc {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc";
 110         };
 111
 112         ipp_di0: clock-ipp-di0 {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <0>;
 116                 clock-output-names = "ipp_di0";
 117         };
 118
 119         ipp_di1: clock-ipp-di1 {
 120                 compatible = "fixed-clock";
 121                 #clock-cells = <0>;
 122                 clock-frequency = <0>;
 123                 clock-output-names = "ipp_di1";
 124         };
 125
 126         anaclk1: clock-anaclk1 {
 127                 compatible = "fixed-clock";
 128                 #clock-cells = <0>;
 129                 clock-frequency = <0>;
 130                 clock-output-names = "anaclk1";
 131         };
 132
 133         anaclk2: clock-anaclk2 {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <0>;
 137                 clock-output-names = "anaclk2";
 138         };
 139
 140         mqs: mqs {
 141                 compatible = "fsl,imx6sx-mqs";
 142                 gpr = <&gpr>;
 143                 status = "disabled";
 144         };
 145
 146         pmu {
 147                 compatible = "arm,cortex-a9-pmu";
 148                 interrupt-parent = <&gpc>;
 149                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 150         };
 151
 152         usbphynop1: usbphynop1 {
 153                 compatible = "usb-nop-xceiv";
 154                 #phy-cells = <0>;
 155         };
 156
 157         soc {
 158                 #address-cells = <1>;
 159                 #size-cells = <1>;
 160                 compatible = "simple-bus";
 161                 interrupt-parent = <&gpc>;
 162                 ranges;
 163
 164                 ocram_s: sram@8f8000 {
 165                         compatible = "mmio-sram";
 166                         reg = <0x008f8000 0x4000>;
 167                         ranges = <0 0x008f8000 0x4000>;
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 171                 };
 172
 173                 ocram: sram@900000 {
 174                         compatible = "mmio-sram";
 175                         reg = <0x00900000 0x20000>;
 176                         ranges = <0 0x00900000 0x20000>;
 177                         #address-cells = <1>;
 178                         #size-cells = <1>;
 179                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 180                 };
 181
 182                 intc: interrupt-controller@a01000 {
 183                         compatible = "arm,cortex-a9-gic";
 184                         #interrupt-cells = <3>;
 185                         interrupt-controller;
 186                         reg = <0x00a01000 0x1000>,
 187                               <0x00a00100 0x100>;
 188                         interrupt-parent = <&intc>;
 189                 };
 190
 191                 L2: cache-controller@a02000 {
 192                         compatible = "arm,pl310-cache";
 193                         reg = <0x00a02000 0x1000>;
 194                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 195                         cache-unified;
 196                         cache-level = <2>;
 197                         arm,tag-latency = <4 2 3>;
 198                         arm,data-latency = <4 2 3>;
 199                 };
 200
 201                 gpu: gpu@1800000 {
 202                         compatible = "vivante,gc";
 203                         reg = <0x01800000 0x4000>;
 204                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 205                         clocks = <&clks IMX6SX_CLK_GPU>,
 206                                  <&clks IMX6SX_CLK_GPU>,
 207                                  <&clks IMX6SX_CLK_GPU>;
 208                         clock-names = "bus", "core", "shader";
 209                         power-domains = <&pd_pu>;
 210                 };
 211
 212                 dma_apbh: dma-apbh@1804000 {
 213                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 214                         reg = <0x01804000 0x2000>;
 215                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 218                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 219                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 220                         #dma-cells = <1>;
 221                         dma-channels = <4>;
 222                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 223                 };
 224
 225                 gpmi: nand-controller@1806000{
 226                         compatible = "fsl,imx6sx-gpmi-nand";
 227                         #address-cells = <1>;
 228                         #size-cells = <1>;
 229                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 230                         reg-names = "gpmi-nand", "bch";
 231                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 232                         interrupt-names = "bch";
 233                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 234                                  <&clks IMX6SX_CLK_GPMI_APB>,
 235                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 236                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 237                                  <&clks IMX6SX_CLK_PER1_BCH>;
 238                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 239                                       "gpmi_bch_apb", "per1_bch";
 240                         dmas = <&dma_apbh 0>;
 241                         dma-names = "rx-tx";
 242                         status = "disabled";
 243                 };
 244
 245                 aips1: bus@2000000 {
 246                         compatible = "fsl,aips-bus", "simple-bus";
 247                         #address-cells = <1>;
 248                         #size-cells = <1>;
 249                         reg = <0x02000000 0x100000>;
 250                         ranges;
 251
 252                         spba-bus@2000000 {
 253                                 compatible = "fsl,spba-bus", "simple-bus";
 254                                 #address-cells = <1>;
 255                                 #size-cells = <1>;
 256                                 reg = <0x02000000 0x40000>;
 257                                 ranges;
 258
 259                                 spdif: spdif@2004000 {
 260                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 261                                         reg = <0x02004000 0x4000>;
 262                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 263                                         dmas = <&sdma 14 18 0>,
 264                                                <&sdma 15 18 0>;
 265                                         dma-names = "rx", "tx";
 266                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 267                                                  <&clks IMX6SX_CLK_OSC>,
 268                                                  <&clks IMX6SX_CLK_SPDIF>,
 269                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 270                                                  <&clks IMX6SX_CLK_IPG>,
 271                                                  <&clks 0>, <&clks 0>,
 272                                                  <&clks IMX6SX_CLK_SPBA>;
 273                                         clock-names = "core", "rxtx0",
 274                                                       "rxtx1", "rxtx2",
 275                                                       "rxtx3", "rxtx4",
 276                                                       "rxtx5", "rxtx6",
 277                                                       "rxtx7", "spba";
 278                                         status = "disabled";
 279                                 };
 280
 281                                 ecspi1: spi@2008000 {
 282                                         #address-cells = <1>;
 283                                         #size-cells = <0>;
 284                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 285                                         reg = <0x02008000 0x4000>;
 286                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 287                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 288                                                  <&clks IMX6SX_CLK_ECSPI1>;
 289                                         clock-names = "ipg", "per";
 290                                         status = "disabled";
 291                                 };
 292
 293                                 ecspi2: spi@200c000 {
 294                                         #address-cells = <1>;
 295                                         #size-cells = <0>;
 296                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 297                                         reg = <0x0200c000 0x4000>;
 298                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 299                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 300                                                  <&clks IMX6SX_CLK_ECSPI2>;
 301                                         clock-names = "ipg", "per";
 302                                         status = "disabled";
 303                                 };
 304
 305                                 ecspi3: spi@2010000 {
 306                                         #address-cells = <1>;
 307                                         #size-cells = <0>;
 308                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 309                                         reg = <0x02010000 0x4000>;
 310                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 311                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 312                                                  <&clks IMX6SX_CLK_ECSPI3>;
 313                                         clock-names = "ipg", "per";
 314                                         status = "disabled";
 315                                 };
 316
 317                                 ecspi4: spi@2014000 {
 318                                         #address-cells = <1>;
 319                                         #size-cells = <0>;
 320                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 321                                         reg = <0x02014000 0x4000>;
 322                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 323                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 324                                                  <&clks IMX6SX_CLK_ECSPI4>;
 325                                         clock-names = "ipg", "per";
 326                                         status = "disabled";
 327                                 };
 328
 329                                 uart1: serial@2020000 {
 330                                         compatible = "fsl,imx6sx-uart",
 331                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 332                                         reg = <0x02020000 0x4000>;
 333                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 334                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 335                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 336                                         clock-names = "ipg", "per";
 337                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 338                                         dma-names = "rx", "tx";
 339                                         status = "disabled";
 340                                 };
 341
 342                                 esai: esai@2024000 {
 343                                         compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
 344                                         reg = <0x02024000 0x4000>;
 345                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 346                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 347                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 348                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 349                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 350                                                  <&clks IMX6SX_CLK_SPBA>;
 351                                         clock-names = "core", "mem", "extal",
 352                                                       "fsys", "spba";
 353                                         dmas = <&sdma 23 21 0>,
 354                                                <&sdma 24 21 0>;
 355                                         dma-names = "rx", "tx";
 356                                         status = "disabled";
 357                                 };
 358
 359                                 ssi1: ssi@2028000 {
 360                                         #sound-dai-cells = <0>;
 361                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 362                                         reg = <0x02028000 0x4000>;
 363                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 364                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 365                                                  <&clks IMX6SX_CLK_SSI1>;
 366                                         clock-names = "ipg", "baud";
 367                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 368                                         dma-names = "rx", "tx";
 369                                         fsl,fifo-depth = <15>;
 370                                         status = "disabled";
 371                                 };
 372
 373                                 ssi2: ssi@202c000 {
 374                                         #sound-dai-cells = <0>;
 375                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 376                                         reg = <0x0202c000 0x4000>;
 377                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 378                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 379                                                  <&clks IMX6SX_CLK_SSI2>;
 380                                         clock-names = "ipg", "baud";
 381                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 382                                         dma-names = "rx", "tx";
 383                                         fsl,fifo-depth = <15>;
 384                                         status = "disabled";
 385                                 };
 386
 387                                 ssi3: ssi@2030000 {
 388                                         #sound-dai-cells = <0>;
 389                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 390                                         reg = <0x02030000 0x4000>;
 391                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 392                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 393                                                  <&clks IMX6SX_CLK_SSI3>;
 394                                         clock-names = "ipg", "baud";
 395                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 396                                         dma-names = "rx", "tx";
 397                                         fsl,fifo-depth = <15>;
 398                                         status = "disabled";
 399                                 };
 400
 401                                 asrc: asrc@2034000 {
 402                                         compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
 403                                         reg = <0x02034000 0x4000>;
 404                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 405                                         clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
 406                                                 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
 407                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 408                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 409                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 410                                                 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 411                                                 <&clks IMX6SX_CLK_SPBA>;
 412                                         clock-names = "mem", "ipg", "asrck_0",
 413                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 414                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 415                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 416                                                 "asrck_d", "asrck_e", "asrck_f", "spba";
 417                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
 418                                                <&sdma 19 23 1>, <&sdma 20 23 1>,
 419                                                <&sdma 21 23 1>, <&sdma 22 23 1>;
 420                                         dma-names = "rxa", "rxb", "rxc",
 421                                                     "txa", "txb", "txc";
 422                                         fsl,asrc-rate  = <48000>;
 423                                         fsl,asrc-width = <16>;
 424                                         status = "okay";
 425                                 };
 426                         };
 427
 428                         pwm1: pwm@2080000 {
 429                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 430                                 reg = <0x02080000 0x4000>;
 431                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 432                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 433                                          <&clks IMX6SX_CLK_PWM1>;
 434                                 clock-names = "ipg", "per";
 435                                 #pwm-cells = <3>;
 436                         };
 437
 438                         pwm2: pwm@2084000 {
 439                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 440                                 reg = <0x02084000 0x4000>;
 441                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 442                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 443                                          <&clks IMX6SX_CLK_PWM2>;
 444                                 clock-names = "ipg", "per";
 445                                 #pwm-cells = <3>;
 446                         };
 447
 448                         pwm3: pwm@2088000 {
 449                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 450                                 reg = <0x02088000 0x4000>;
 451                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 452                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 453                                          <&clks IMX6SX_CLK_PWM3>;
 454                                 clock-names = "ipg", "per";
 455                                 #pwm-cells = <3>;
 456                         };
 457
 458                         pwm4: pwm@208c000 {
 459                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 460                                 reg = <0x0208c000 0x4000>;
 461                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 462                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 463                                          <&clks IMX6SX_CLK_PWM4>;
 464                                 clock-names = "ipg", "per";
 465                                 #pwm-cells = <3>;
 466                         };
 467
 468                         flexcan1: can@2090000 {
 469                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 470                                 reg = <0x02090000 0x4000>;
 471                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 473                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 474                                 clock-names = "ipg", "per";
 475                                 fsl,stop-mode = <&gpr 0x10 1>;
 476                                 status = "disabled";
 477                         };
 478
 479                         flexcan2: can@2094000 {
 480                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 481                                 reg = <0x02094000 0x4000>;
 482                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 484                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 485                                 clock-names = "ipg", "per";
 486                                 fsl,stop-mode = <&gpr 0x10 2>;
 487                                 status = "disabled";
 488                         };
 489
 490                         gpt: timer@2098000 {
 491                                 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
 492                                 reg = <0x02098000 0x4000>;
 493                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 495                                          <&clks IMX6SX_CLK_GPT_3M>;
 496                                 clock-names = "ipg", "per";
 497                         };
 498
 499                         gpio1: gpio@209c000 {
 500                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 501                                 reg = <0x0209c000 0x4000>;
 502                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 503                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 504                                 gpio-controller;
 505                                 #gpio-cells = <2>;
 506                                 interrupt-controller;
 507                                 #interrupt-cells = <2>;
 508                                 gpio-ranges = <&iomuxc 0 5 26>;
 509                         };
 510
 511                         gpio2: gpio@20a0000 {
 512                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 513                                 reg = <0x020a0000 0x4000>;
 514                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 515                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 516                                 gpio-controller;
 517                                 #gpio-cells = <2>;
 518                                 interrupt-controller;
 519                                 #interrupt-cells = <2>;
 520                                 gpio-ranges = <&iomuxc 0 31 20>;
 521                         };
 522
 523                         gpio3: gpio@20a4000 {
 524                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 525                                 reg = <0x020a4000 0x4000>;
 526                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 527                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 528                                 gpio-controller;
 529                                 #gpio-cells = <2>;
 530                                 interrupt-controller;
 531                                 #interrupt-cells = <2>;
 532                                 gpio-ranges = <&iomuxc 0 51 29>;
 533                         };
 534
 535                         gpio4: gpio@20a8000 {
 536                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 537                                 reg = <0x020a8000 0x4000>;
 538                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 539                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 540                                 gpio-controller;
 541                                 #gpio-cells = <2>;
 542                                 interrupt-controller;
 543                                 #interrupt-cells = <2>;
 544                                 gpio-ranges = <&iomuxc 0 80 32>;
 545                         };
 546
 547                         gpio5: gpio@20ac000 {
 548                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 549                                 reg = <0x020ac000 0x4000>;
 550                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 551                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 552                                 gpio-controller;
 553                                 #gpio-cells = <2>;
 554                                 interrupt-controller;
 555                                 #interrupt-cells = <2>;
 556                                 gpio-ranges = <&iomuxc 0 112 24>;
 557                         };
 558
 559                         gpio6: gpio@20b0000 {
 560                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 561                                 reg = <0x020b0000 0x4000>;
 562                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 563                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 564                                 gpio-controller;
 565                                 #gpio-cells = <2>;
 566                                 interrupt-controller;
 567                                 #interrupt-cells = <2>;
 568                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
 569                         };
 570
 571                         gpio7: gpio@20b4000 {
 572                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 573                                 reg = <0x020b4000 0x4000>;
 574                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 575                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 576                                 gpio-controller;
 577                                 #gpio-cells = <2>;
 578                                 interrupt-controller;
 579                                 #interrupt-cells = <2>;
 580                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
 581                         };
 582
 583                         kpp: keypad@20b8000 {
 584                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 585                                 reg = <0x020b8000 0x4000>;
 586                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 587                                 clocks = <&clks IMX6SX_CLK_IPG>;
 588                                 status = "disabled";
 589                         };
 590
 591                         wdog1: watchdog@20bc000 {
 592                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 593                                 reg = <0x020bc000 0x4000>;
 594                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 595                                 clocks = <&clks IMX6SX_CLK_IPG>;
 596                         };
 597
 598                         wdog2: watchdog@20c0000 {
 599                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 600                                 reg = <0x020c0000 0x4000>;
 601                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 602                                 clocks = <&clks IMX6SX_CLK_IPG>;
 603                                 status = "disabled";
 604                         };
 605
 606                         clks: clock-controller@20c4000 {
 607                                 compatible = "fsl,imx6sx-ccm";
 608                                 reg = <0x020c4000 0x4000>;
 609                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 610                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 611                                 #clock-cells = <1>;
 612                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
 613                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
 614                         };
 615
 616                         anatop: anatop@20c8000 {
 617                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 618                                              "syscon", "simple-mfd";
 619                                 reg = <0x020c8000 0x1000>;
 620                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 621                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 622                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 623
 624                                 reg_vdd1p1: regulator-1p1 {
 625                                         compatible = "fsl,anatop-regulator";
 626                                         regulator-name = "vdd1p1";
 627                                         regulator-min-microvolt = <1000000>;
 628                                         regulator-max-microvolt = <1200000>;
 629                                         regulator-always-on;
 630                                         anatop-reg-offset = <0x110>;
 631                                         anatop-vol-bit-shift = <8>;
 632                                         anatop-vol-bit-width = <5>;
 633                                         anatop-min-bit-val = <4>;
 634                                         anatop-min-voltage = <800000>;
 635                                         anatop-max-voltage = <1375000>;
 636                                         anatop-enable-bit = <0>;
 637                                 };
 638
 639                                 reg_vdd3p0: regulator-3p0 {
 640                                         compatible = "fsl,anatop-regulator";
 641                                         regulator-name = "vdd3p0";
 642                                         regulator-min-microvolt = <2800000>;
 643                                         regulator-max-microvolt = <3150000>;
 644                                         regulator-always-on;
 645                                         anatop-reg-offset = <0x120>;
 646                                         anatop-vol-bit-shift = <8>;
 647                                         anatop-vol-bit-width = <5>;
 648                                         anatop-min-bit-val = <0>;
 649                                         anatop-min-voltage = <2625000>;
 650                                         anatop-max-voltage = <3400000>;
 651                                         anatop-enable-bit = <0>;
 652                                 };
 653
 654                                 reg_vdd2p5: regulator-2p5 {
 655                                         compatible = "fsl,anatop-regulator";
 656                                         regulator-name = "vdd2p5";
 657                                         regulator-min-microvolt = <2250000>;
 658                                         regulator-max-microvolt = <2750000>;
 659                                         regulator-always-on;
 660                                         anatop-reg-offset = <0x130>;
 661                                         anatop-vol-bit-shift = <8>;
 662                                         anatop-vol-bit-width = <5>;
 663                                         anatop-min-bit-val = <0>;
 664                                         anatop-min-voltage = <2100000>;
 665                                         anatop-max-voltage = <2875000>;
 666                                         anatop-enable-bit = <0>;
 667                                 };
 668
 669                                 reg_arm: regulator-vddcore {
 670                                         compatible = "fsl,anatop-regulator";
 671                                         regulator-name = "vddarm";
 672                                         regulator-min-microvolt = <725000>;
 673                                         regulator-max-microvolt = <1450000>;
 674                                         regulator-always-on;
 675                                         anatop-reg-offset = <0x140>;
 676                                         anatop-vol-bit-shift = <0>;
 677                                         anatop-vol-bit-width = <5>;
 678                                         anatop-delay-reg-offset = <0x170>;
 679                                         anatop-delay-bit-shift = <24>;
 680                                         anatop-delay-bit-width = <2>;
 681                                         anatop-min-bit-val = <1>;
 682                                         anatop-min-voltage = <725000>;
 683                                         anatop-max-voltage = <1450000>;
 684                                 };
 685
 686                                 reg_pcie: regulator-vddpcie {
 687                                         compatible = "fsl,anatop-regulator";
 688                                         regulator-name = "vddpcie";
 689                                         regulator-min-microvolt = <725000>;
 690                                         regulator-max-microvolt = <1450000>;
 691                                         anatop-reg-offset = <0x140>;
 692                                         anatop-vol-bit-shift = <9>;
 693                                         anatop-vol-bit-width = <5>;
 694                                         anatop-delay-reg-offset = <0x170>;
 695                                         anatop-delay-bit-shift = <26>;
 696                                         anatop-delay-bit-width = <2>;
 697                                         anatop-min-bit-val = <1>;
 698                                         anatop-min-voltage = <725000>;
 699                                         anatop-max-voltage = <1450000>;
 700                                 };
 701
 702                                 reg_soc: regulator-vddsoc {
 703                                         compatible = "fsl,anatop-regulator";
 704                                         regulator-name = "vddsoc";
 705                                         regulator-min-microvolt = <725000>;
 706                                         regulator-max-microvolt = <1450000>;
 707                                         regulator-always-on;
 708                                         anatop-reg-offset = <0x140>;
 709                                         anatop-vol-bit-shift = <18>;
 710                                         anatop-vol-bit-width = <5>;
 711                                         anatop-delay-reg-offset = <0x170>;
 712                                         anatop-delay-bit-shift = <28>;
 713                                         anatop-delay-bit-width = <2>;
 714                                         anatop-min-bit-val = <1>;
 715                                         anatop-min-voltage = <725000>;
 716                                         anatop-max-voltage = <1450000>;
 717                                 };
 718
 719                                 tempmon: tempmon {
 720                                         compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
 721                                         interrupt-parent = <&gpc>;
 722                                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 723                                         fsl,tempmon = <&anatop>;
 724                                         nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 725                                         nvmem-cell-names = "calib", "temp_grade";
 726                                         clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 727                                 };
 728                         };
 729
 730                         usbphy1: usbphy@20c9000 {
 731                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 732                                 reg = <0x020c9000 0x1000>;
 733                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 734                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 735                                 fsl,anatop = <&anatop>;
 736                         };
 737
 738                         usbphy2: usbphy@20ca000 {
 739                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 740                                 reg = <0x020ca000 0x1000>;
 741                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 742                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 743                                 fsl,anatop = <&anatop>;
 744                         };
 745
 746                         snvs: snvs@20cc000 {
 747                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 748                                 reg = <0x020cc000 0x4000>;
 749
 750                                 snvs_rtc: snvs-rtc-lp {
 751                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 752                                         regmap = <&snvs>;
 753                                         offset = <0x34>;
 754                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 755                                 };
 756
 757                                 snvs_poweroff: snvs-poweroff {
 758                                         compatible = "syscon-poweroff";
 759                                         regmap = <&snvs>;
 760                                         offset = <0x38>;
 761                                         value = <0x60>;
 762                                         mask = <0x60>;
 763                                         status = "disabled";
 764                                 };
 765
 766                                 snvs_pwrkey: snvs-powerkey {
 767                                         compatible = "fsl,sec-v4.0-pwrkey";
 768                                         regmap = <&snvs>;
 769                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 770                                         linux,keycode = <KEY_POWER>;
 771                                         wakeup-source;
 772                                         status = "disabled";
 773                                 };
 774                         };
 775
 776                         epit1: epit@20d0000 {
 777                                 reg = <0x020d0000 0x4000>;
 778                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 779                         };
 780
 781                         epit2: epit@20d4000 {
 782                                 reg = <0x020d4000 0x4000>;
 783                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 784                         };
 785
 786                         src: reset-controller@20d8000 {
 787                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 788                                 reg = <0x020d8000 0x4000>;
 789                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 790                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 791                                 #reset-cells = <1>;
 792                         };
 793
 794                         gpc: gpc@20dc000 {
 795                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 796                                 reg = <0x020dc000 0x4000>;
 797                                 interrupt-controller;
 798                                 #interrupt-cells = <3>;
 799                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 800                                 interrupt-parent = <&intc>;
 801                                 clocks = <&clks IMX6SX_CLK_IPG>;
 802                                 clock-names = "ipg";
 803
 804                                 pgc {
 805                                         #address-cells = <1>;
 806                                         #size-cells = <0>;
 807
 808                                         power-domain@0 {
 809                                                 reg = <0>;
 810                                                 #power-domain-cells = <0>;
 811                                         };
 812
 813                                         pd_pu: power-domain@1 {
 814                                                 reg = <1>;
 815                                                 #power-domain-cells = <0>;
 816                                                 power-supply = <&reg_soc>;
 817                                                 clocks = <&clks IMX6SX_CLK_GPU>;
 818                                         };
 819
 820                                         pd_disp: power-domain@2 {
 821                                                 reg = <2>;
 822                                                 #power-domain-cells = <0>;
 823                                                 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
 824                                                          <&clks IMX6SX_CLK_DISPLAY_AXI>,
 825                                                          <&clks IMX6SX_CLK_LCDIF1_PIX>,
 826                                                          <&clks IMX6SX_CLK_LCDIF_APB>,
 827                                                          <&clks IMX6SX_CLK_LCDIF2_PIX>,
 828                                                          <&clks IMX6SX_CLK_CSI>,
 829                                                          <&clks IMX6SX_CLK_VADC>;
 830                                         };
 831
 832                                         pd_pci: power-domain@3 {
 833                                                 reg = <3>;
 834                                                 #power-domain-cells = <0>;
 835                                                 power-supply = <&reg_pcie>;
 836                                         };
 837                                 };
 838                         };
 839
 840                         iomuxc: pinctrl@20e0000 {
 841                                 compatible = "fsl,imx6sx-iomuxc";
 842                                 reg = <0x020e0000 0x4000>;
 843                         };
 844
 845                         gpr: iomuxc-gpr@20e4000 {
 846                                 compatible = "fsl,imx6sx-iomuxc-gpr",
 847                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 848                                 reg = <0x020e4000 0x4000>;
 849                         };
 850
 851                         sdma: sdma@20ec000 {
 852                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
 853                                 reg = <0x020ec000 0x4000>;
 854                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks IMX6SX_CLK_IPG>,
 856                                          <&clks IMX6SX_CLK_SDMA>;
 857                                 clock-names = "ipg", "ahb";
 858                                 #dma-cells = <3>;
 859                                 /* imx6sx reuses imx6q sdma firmware */
 860                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 861                         };
 862                 };
 863
 864                 aips2: bus@2100000 {
 865                         compatible = "fsl,aips-bus", "simple-bus";
 866                         #address-cells = <1>;
 867                         #size-cells = <1>;
 868                         reg = <0x02100000 0x100000>;
 869                         ranges;
 870
 871                         crypto: crypto@2100000 {
 872                                 compatible = "fsl,sec-v4.0";
 873                                 #address-cells = <1>;
 874                                 #size-cells = <1>;
 875                                 reg = <0x2100000 0x10000>;
 876                                 ranges = <0 0x2100000 0x10000>;
 877                                 interrupt-parent = <&intc>;
 878                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
 879                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
 880                                          <&clks IMX6SX_CLK_CAAM_IPG>,
 881                                          <&clks IMX6SX_CLK_EIM_SLOW>;
 882                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 883
 884                                 sec_jr0: jr@1000 {
 885                                         compatible = "fsl,sec-v4.0-job-ring";
 886                                         reg = <0x1000 0x1000>;
 887                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 888                                 };
 889
 890                                 sec_jr1: jr@2000 {
 891                                         compatible = "fsl,sec-v4.0-job-ring";
 892                                         reg = <0x2000 0x1000>;
 893                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 894                                 };
 895                         };
 896
 897                         usbotg1: usb@2184000 {
 898                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 899                                 reg = <0x02184000 0x200>;
 900                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 902                                 fsl,usbphy = <&usbphy1>;
 903                                 fsl,usbmisc = <&usbmisc 0>;
 904                                 fsl,anatop = <&anatop>;
 905                                 ahb-burst-config = <0x0>;
 906                                 tx-burst-size-dword = <0x10>;
 907                                 rx-burst-size-dword = <0x10>;
 908                                 status = "disabled";
 909                         };
 910
 911                         usbotg2: usb@2184200 {
 912                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 913                                 reg = <0x02184200 0x200>;
 914                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 915                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 916                                 fsl,usbphy = <&usbphy2>;
 917                                 fsl,usbmisc = <&usbmisc 1>;
 918                                 ahb-burst-config = <0x0>;
 919                                 tx-burst-size-dword = <0x10>;
 920                                 rx-burst-size-dword = <0x10>;
 921                                 status = "disabled";
 922                         };
 923
 924                         usbh: usb@2184400 {
 925                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 926                                 reg = <0x02184400 0x200>;
 927                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 928                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 929                                 fsl,usbphy = <&usbphynop1>;
 930                                 fsl,usbmisc = <&usbmisc 2>;
 931                                 phy_type = "hsic";
 932                                 fsl,anatop = <&anatop>;
 933                                 dr_mode = "host";
 934                                 ahb-burst-config = <0x0>;
 935                                 tx-burst-size-dword = <0x10>;
 936                                 rx-burst-size-dword = <0x10>;
 937                                 status = "disabled";
 938                         };
 939
 940                         usbmisc: usbmisc@2184800 {
 941                                 #index-cells = <1>;
 942                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 943                                 reg = <0x02184800 0x200>;
 944                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 945                         };
 946
 947                         fec1: ethernet@2188000 {
 948                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 949                                 reg = <0x02188000 0x4000>;
 950                                 interrupt-names = "int0", "pps";
 951                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 952                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 953                                 clocks = <&clks IMX6SX_CLK_ENET>,
 954                                          <&clks IMX6SX_CLK_ENET_AHB>,
 955                                          <&clks IMX6SX_CLK_ENET_PTP>,
 956                                          <&clks IMX6SX_CLK_ENET_REF>,
 957                                          <&clks IMX6SX_CLK_ENET_PTP>;
 958                                 clock-names = "ipg", "ahb", "ptp",
 959                                               "enet_clk_ref", "enet_out";
 960                                 fsl,num-tx-queues = <3>;
 961                                 fsl,num-rx-queues = <3>;
 962                                 fsl,stop-mode = <&gpr 0x10 3>;
 963                                 status = "disabled";
 964                         };
 965
 966                         mlb: mlb@218c000 {
 967                                 reg = <0x0218c000 0x4000>;
 968                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 969                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 970                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 971                                 clocks = <&clks IMX6SX_CLK_MLB>;
 972                                 status = "disabled";
 973                         };
 974
 975                         usdhc1: mmc@2190000 {
 976                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 977                                 reg = <0x02190000 0x4000>;
 978                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 979                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 980                                          <&clks IMX6SX_CLK_USDHC1>,
 981                                          <&clks IMX6SX_CLK_USDHC1>;
 982                                 clock-names = "ipg", "ahb", "per";
 983                                 bus-width = <4>;
 984                                 status = "disabled";
 985                         };
 986
 987                         usdhc2: mmc@2194000 {
 988                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 989                                 reg = <0x02194000 0x4000>;
 990                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 991                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 992                                          <&clks IMX6SX_CLK_USDHC2>,
 993                                          <&clks IMX6SX_CLK_USDHC2>;
 994                                 clock-names = "ipg", "ahb", "per";
 995                                 bus-width = <4>;
 996                                 status = "disabled";
 997                         };
 998
 999                         usdhc3: mmc@2198000 {
1000                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1001                                 reg = <0x02198000 0x4000>;
1002                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1003                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
1004                                          <&clks IMX6SX_CLK_USDHC3>,
1005                                          <&clks IMX6SX_CLK_USDHC3>;
1006                                 clock-names = "ipg", "ahb", "per";
1007                                 bus-width = <4>;
1008                                 status = "disabled";
1009                         };
1010
1011                         usdhc4: mmc@219c000 {
1012                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1013                                 reg = <0x0219c000 0x4000>;
1014                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1015                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
1016                                          <&clks IMX6SX_CLK_USDHC4>,
1017                                          <&clks IMX6SX_CLK_USDHC4>;
1018                                 clock-names = "ipg", "ahb", "per";
1019                                 bus-width = <4>;
1020                                 status = "disabled";
1021                         };
1022
1023                         i2c1: i2c@21a0000 {
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1027                                 reg = <0x021a0000 0x4000>;
1028                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1029                                 clocks = <&clks IMX6SX_CLK_I2C1>;
1030                                 status = "disabled";
1031                         };
1032
1033                         i2c2: i2c@21a4000 {
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1037                                 reg = <0x021a4000 0x4000>;
1038                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1039                                 clocks = <&clks IMX6SX_CLK_I2C2>;
1040                                 status = "disabled";
1041                         };
1042
1043                         i2c3: i2c@21a8000 {
1044                                 #address-cells = <1>;
1045                                 #size-cells = <0>;
1046                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1047                                 reg = <0x021a8000 0x4000>;
1048                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1049                                 clocks = <&clks IMX6SX_CLK_I2C3>;
1050                                 status = "disabled";
1051                         };
1052
1053                         memory-controller@21b0000 {
1054                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1055                                 reg = <0x021b0000 0x4000>;
1056                                 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1057                         };
1058
1059                         fec2: ethernet@21b4000 {
1060                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1061                                 reg = <0x021b4000 0x4000>;
1062                                 interrupt-names = "int0", "pps";
1063                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1064                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1065                                 clocks = <&clks IMX6SX_CLK_ENET>,
1066                                          <&clks IMX6SX_CLK_ENET_AHB>,
1067                                          <&clks IMX6SX_CLK_ENET_PTP>,
1068                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1069                                          <&clks IMX6SX_CLK_ENET_PTP>;
1070                                 clock-names = "ipg", "ahb", "ptp",
1071                                               "enet_clk_ref", "enet_out";
1072                                 fsl,stop-mode = <&gpr 0x10 4>;
1073                                 status = "disabled";
1074                         };
1075
1076                         weim: weim@21b8000 {
1077                                 #address-cells = <2>;
1078                                 #size-cells = <1>;
1079                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1080                                 reg = <0x021b8000 0x4000>;
1081                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1082                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1083                                 fsl,weim-cs-gpr = <&gpr>;
1084                                 status = "disabled";
1085                         };
1086
1087                         ocotp: efuse@21bc000 {
1088                                 #address-cells = <1>;
1089                                 #size-cells = <1>;
1090                                 compatible = "fsl,imx6sx-ocotp", "syscon";
1091                                 reg = <0x021bc000 0x4000>;
1092                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1093
1094                                 cpu_speed_grade: speed-grade@10 {
1095                                         reg = <0x10 4>;
1096                                 };
1097
1098                                 tempmon_calib: calib@38 {
1099                                         reg = <0x38 4>;
1100                                 };
1101
1102                                 tempmon_temp_grade: temp-grade@20 {
1103                                         reg = <0x20 4>;
1104                                 };
1105                         };
1106
1107                         sai1: sai@21d4000 {
1108                                 compatible = "fsl,imx6sx-sai";
1109                                 reg = <0x021d4000 0x4000>;
1110                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1111                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1112                                          <&clks IMX6SX_CLK_SAI1>,
1113                                          <&clks 0>, <&clks 0>;
1114                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1115                                 dma-names = "rx", "tx";
1116                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1117                                 status = "disabled";
1118                         };
1119
1120                         audmux: audmux@21d8000 {
1121                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1122                                 reg = <0x021d8000 0x4000>;
1123                                 status = "disabled";
1124                         };
1125
1126                         sai2: sai@21dc000 {
1127                                 compatible = "fsl,imx6sx-sai";
1128                                 reg = <0x021dc000 0x4000>;
1129                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1130                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1131                                          <&clks IMX6SX_CLK_SAI2>,
1132                                          <&clks 0>, <&clks 0>;
1133                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1134                                 dma-names = "rx", "tx";
1135                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1136                                 status = "disabled";
1137                         };
1138
1139                         qspi1: spi@21e0000 {
1140                                 #address-cells = <1>;
1141                                 #size-cells = <0>;
1142                                 compatible = "fsl,imx6sx-qspi";
1143                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1144                                 reg-names = "QuadSPI", "QuadSPI-memory";
1145                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1146                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1147                                          <&clks IMX6SX_CLK_QSPI1>;
1148                                 clock-names = "qspi_en", "qspi";
1149                                 status = "disabled";
1150                         };
1151
1152                         qspi2: spi@21e4000 {
1153                                 #address-cells = <1>;
1154                                 #size-cells = <0>;
1155                                 compatible = "fsl,imx6sx-qspi";
1156                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1157                                 reg-names = "QuadSPI", "QuadSPI-memory";
1158                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1159                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1160                                          <&clks IMX6SX_CLK_QSPI2>;
1161                                 clock-names = "qspi_en", "qspi";
1162                                 status = "disabled";
1163                         };
1164
1165                         uart2: serial@21e8000 {
1166                                 compatible = "fsl,imx6sx-uart",
1167                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1168                                 reg = <0x021e8000 0x4000>;
1169                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1170                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1171                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1172                                 clock-names = "ipg", "per";
1173                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1174                                 dma-names = "rx", "tx";
1175                                 status = "disabled";
1176                         };
1177
1178                         uart3: serial@21ec000 {
1179                                 compatible = "fsl,imx6sx-uart",
1180                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1181                                 reg = <0x021ec000 0x4000>;
1182                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1183                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1184                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1185                                 clock-names = "ipg", "per";
1186                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1187                                 dma-names = "rx", "tx";
1188                                 status = "disabled";
1189                         };
1190
1191                         uart4: serial@21f0000 {
1192                                 compatible = "fsl,imx6sx-uart",
1193                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1194                                 reg = <0x021f0000 0x4000>;
1195                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1196                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1197                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1198                                 clock-names = "ipg", "per";
1199                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1200                                 dma-names = "rx", "tx";
1201                                 status = "disabled";
1202                         };
1203
1204                         uart5: serial@21f4000 {
1205                                 compatible = "fsl,imx6sx-uart",
1206                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1207                                 reg = <0x021f4000 0x4000>;
1208                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1209                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1210                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1211                                 clock-names = "ipg", "per";
1212                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1213                                 dma-names = "rx", "tx";
1214                                 status = "disabled";
1215                         };
1216
1217                         i2c4: i2c@21f8000 {
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1221                                 reg = <0x021f8000 0x4000>;
1222                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1223                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1224                                 status = "disabled";
1225                         };
1226                 };
1227
1228                 aips3: bus@2200000 {
1229                         compatible = "fsl,aips-bus", "simple-bus";
1230                         #address-cells = <1>;
1231                         #size-cells = <1>;
1232                         reg = <0x02200000 0x100000>;
1233                         ranges;
1234
1235                         spba-bus@2240000 {
1236                                 compatible = "fsl,spba-bus", "simple-bus";
1237                                 #address-cells = <1>;
1238                                 #size-cells = <1>;
1239                                 reg = <0x02240000 0x40000>;
1240                                 ranges;
1241
1242                                 csi1: csi@2214000 {
1243                                         reg = <0x02214000 0x4000>;
1244                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1245                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1246                                                  <&clks IMX6SX_CLK_CSI>,
1247                                                  <&clks IMX6SX_CLK_DCIC1>;
1248                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1249                                         status = "disabled";
1250                                 };
1251
1252                                 pxp: pxp@2218000 {
1253                                         compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1254                                         reg = <0x02218000 0x4000>;
1255                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1256                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1257                                         clock-names = "axi";
1258                                         power-domains = <&pd_disp>;
1259                                         status = "disabled";
1260                                 };
1261
1262                                 csi2: csi@221c000 {
1263                                         reg = <0x0221c000 0x4000>;
1264                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1265                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1266                                                  <&clks IMX6SX_CLK_CSI>,
1267                                                  <&clks IMX6SX_CLK_DCIC2>;
1268                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1269                                         status = "disabled";
1270                                 };
1271
1272                                 lcdif1: lcdif@2220000 {
1273                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1274                                         reg = <0x02220000 0x4000>;
1275                                         interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1276                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1277                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1278                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1279                                         clock-names = "pix", "axi", "disp_axi";
1280                                         power-domains = <&pd_disp>;
1281                                         status = "disabled";
1282                                 };
1283
1284                                 lcdif2: lcdif@2224000 {
1285                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1286                                         reg = <0x02224000 0x4000>;
1287                                         interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1288                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1289                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1290                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1291                                         clock-names = "pix", "axi", "disp_axi";
1292                                         power-domains = <&pd_disp>;
1293                                         status = "disabled";
1294                                 };
1295
1296                                 vadc: vadc@2228000 {
1297                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1298                                         reg-names = "vadc-vafe", "vadc-vdec";
1299                                         clocks = <&clks IMX6SX_CLK_VADC>,
1300                                                  <&clks IMX6SX_CLK_CSI>;
1301                                         clock-names = "vadc", "csi";
1302                                         power-domains = <&pd_disp>;
1303                                         status = "disabled";
1304                                 };
1305                         };
1306
1307                         adc1: adc@2280000 {
1308                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1309                                 reg = <0x02280000 0x4000>;
1310                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1311                                 clocks = <&clks IMX6SX_CLK_IPG>;
1312                                 clock-names = "adc";
1313                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1314                                                          <20000000>;
1315                                 status = "disabled";
1316                         };
1317
1318                         adc2: adc@2284000 {
1319                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1320                                 reg = <0x02284000 0x4000>;
1321                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1322                                 clocks = <&clks IMX6SX_CLK_IPG>;
1323                                 clock-names = "adc";
1324                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1325                                                          <20000000>;
1326                                 status = "disabled";
1327                         };
1328
1329                         wdog3: watchdog@2288000 {
1330                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1331                                 reg = <0x02288000 0x4000>;
1332                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1333                                 clocks = <&clks IMX6SX_CLK_IPG>;
1334                                 status = "disabled";
1335                         };
1336
1337                         ecspi5: spi@228c000 {
1338                                 #address-cells = <1>;
1339                                 #size-cells = <0>;
1340                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1341                                 reg = <0x0228c000 0x4000>;
1342                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1343                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1344                                          <&clks IMX6SX_CLK_ECSPI5>;
1345                                 clock-names = "ipg", "per";
1346                                 status = "disabled";
1347                         };
1348
1349                         uart6: serial@22a0000 {
1350                                 compatible = "fsl,imx6sx-uart",
1351                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1352                                 reg = <0x022a0000 0x4000>;
1353                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1354                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1355                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1356                                 clock-names = "ipg", "per";
1357                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1358                                 dma-names = "rx", "tx";
1359                                 status = "disabled";
1360                         };
1361
1362                         pwm5: pwm@22a4000 {
1363                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1364                                 reg = <0x022a4000 0x4000>;
1365                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1366                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1367                                          <&clks IMX6SX_CLK_PWM5>;
1368                                 clock-names = "ipg", "per";
1369                                 #pwm-cells = <3>;
1370                         };
1371
1372                         pwm6: pwm@22a8000 {
1373                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1374                                 reg = <0x022a8000 0x4000>;
1375                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1376                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1377                                          <&clks IMX6SX_CLK_PWM6>;
1378                                 clock-names = "ipg", "per";
1379                                 #pwm-cells = <3>;
1380                         };
1381
1382                         pwm7: pwm@22ac000 {
1383                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1384                                 reg = <0x022ac000 0x4000>;
1385                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1386                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1387                                          <&clks IMX6SX_CLK_PWM7>;
1388                                 clock-names = "ipg", "per";
1389                                 #pwm-cells = <3>;
1390                         };
1391
1392                         pwm8: pwm@22b0000 {
1393                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1394                                 reg = <0x0022b0000 0x4000>;
1395                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1396                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1397                                          <&clks IMX6SX_CLK_PWM8>;
1398                                 clock-names = "ipg", "per";
1399                                 #pwm-cells = <3>;
1400                         };
1401                 };
1402
1403                 pcie: pcie@8ffc000 {
1404                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1405                         reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1406                         reg-names = "dbi", "config";
1407                         #address-cells = <3>;
1408                         #size-cells = <2>;
1409                         device_type = "pci";
1410                         bus-range = <0x00 0xff>;
1411                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1412                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1413                         num-lanes = <1>;
1414                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1415                         interrupt-names = "msi";
1416                         #interrupt-cells = <1>;
1417                         interrupt-map-mask = <0 0 0 0x7>;
1418                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1419                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1420                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1421                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1422                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1423                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1424                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1425                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1426                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1427                         power-domains = <&pd_disp>, <&pd_pci>;
1428                         power-domain-names = "pcie", "pcie_phy";
1429                         status = "disabled";
1430                 };
1431         };
1432 };