2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
27 tzic: tz-interrupt-controller@e0000000 {
28 compatible = "fsl,imx51-tzic", "fsl,tzic";
30 #interrupt-cells = <1>;
31 reg = <0xe0000000 0x4000>;
39 compatible = "fsl,imx-ckil", "fixed-clock";
40 clock-frequency = <32768>;
44 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>;
49 compatible = "fsl,imx-ckih2", "fixed-clock";
50 clock-frequency = <0>;
54 compatible = "fsl,imx-osc", "fixed-clock";
55 clock-frequency = <24000000>;
64 compatible = "arm,cortex-a8";
66 clock-latency = <61036>; /* two CLK32 periods */
70 /* kHz uV (No regulator support) */
80 compatible = "simple-bus";
81 interrupt-parent = <&tzic>;
86 compatible = "fsl,imx51-ipu";
87 reg = <0x40000000 0x20000000>;
89 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
90 clock-names = "bus", "di0", "di1";
94 aips@70000000 { /* AIPS1 */
95 compatible = "fsl,aips-bus", "simple-bus";
98 reg = <0x70000000 0x10000000>;
102 compatible = "fsl,spba-bus", "simple-bus";
103 #address-cells = <1>;
105 reg = <0x70000000 0x40000>;
108 esdhc1: esdhc@70004000 {
109 compatible = "fsl,imx51-esdhc";
110 reg = <0x70004000 0x4000>;
112 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
113 clock-names = "ipg", "ahb", "per";
117 esdhc2: esdhc@70008000 {
118 compatible = "fsl,imx51-esdhc";
119 reg = <0x70008000 0x4000>;
121 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
122 clock-names = "ipg", "ahb", "per";
127 uart3: serial@7000c000 {
128 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
129 reg = <0x7000c000 0x4000>;
131 clocks = <&clks 32>, <&clks 33>;
132 clock-names = "ipg", "per";
136 ecspi1: ecspi@70010000 {
137 #address-cells = <1>;
139 compatible = "fsl,imx51-ecspi";
140 reg = <0x70010000 0x4000>;
142 clocks = <&clks 51>, <&clks 52>;
143 clock-names = "ipg", "per";
148 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
149 reg = <0x70014000 0x4000>;
152 fsl,fifo-depth = <15>;
153 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
157 esdhc3: esdhc@70020000 {
158 compatible = "fsl,imx51-esdhc";
159 reg = <0x70020000 0x4000>;
161 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
162 clock-names = "ipg", "ahb", "per";
167 esdhc4: esdhc@70024000 {
168 compatible = "fsl,imx51-esdhc";
169 reg = <0x70024000 0x4000>;
171 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
172 clock-names = "ipg", "ahb", "per";
178 usbotg: usb@73f80000 {
179 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
180 reg = <0x73f80000 0x0200>;
182 fsl,usbmisc = <&usbmisc 0>;
186 usbh1: usb@73f80200 {
187 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
188 reg = <0x73f80200 0x0200>;
190 fsl,usbmisc = <&usbmisc 1>;
194 usbh2: usb@73f80400 {
195 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
196 reg = <0x73f80400 0x0200>;
198 fsl,usbmisc = <&usbmisc 2>;
202 usbh3: usb@73f80600 {
203 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
204 reg = <0x73f80600 0x0200>;
206 fsl,usbmisc = <&usbmisc 3>;
210 usbmisc: usbmisc@73f80800 {
212 compatible = "fsl,imx51-usbmisc";
213 reg = <0x73f80800 0x200>;
216 gpio1: gpio@73f84000 {
217 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
218 reg = <0x73f84000 0x4000>;
219 interrupts = <50 51>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
226 gpio2: gpio@73f88000 {
227 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
228 reg = <0x73f88000 0x4000>;
229 interrupts = <52 53>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
236 gpio3: gpio@73f8c000 {
237 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
238 reg = <0x73f8c000 0x4000>;
239 interrupts = <54 55>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
246 gpio4: gpio@73f90000 {
247 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
248 reg = <0x73f90000 0x4000>;
249 interrupts = <56 57>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
257 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
258 reg = <0x73f94000 0x4000>;
264 wdog1: wdog@73f98000 {
265 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
266 reg = <0x73f98000 0x4000>;
271 wdog2: wdog@73f9c000 {
272 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
273 reg = <0x73f9c000 0x4000>;
279 gpt: timer@73fa0000 {
280 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
281 reg = <0x73fa0000 0x4000>;
283 clocks = <&clks 36>, <&clks 41>;
284 clock-names = "ipg", "per";
287 iomuxc: iomuxc@73fa8000 {
288 compatible = "fsl,imx51-iomuxc";
289 reg = <0x73fa8000 0x4000>;
292 pinctrl_audmux_1: audmuxgrp-1 {
294 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
295 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
296 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
297 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
303 pinctrl_fec_1: fecgrp-1 {
305 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
306 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
307 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
308 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
309 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
310 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
311 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
312 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
313 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
314 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
315 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
316 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
317 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
318 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
319 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
320 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
321 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
325 pinctrl_fec_2: fecgrp-2 {
327 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
328 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
329 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
330 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
331 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
332 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
333 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
334 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
335 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
336 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
337 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
338 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
339 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
340 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
341 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
342 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
343 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
344 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
350 pinctrl_ecspi1_1: ecspi1grp-1 {
352 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
353 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
354 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
360 pinctrl_ecspi2_1: ecspi2grp-1 {
362 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
363 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
364 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
370 pinctrl_esdhc1_1: esdhc1grp-1 {
372 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
373 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
374 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
375 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
376 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
377 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
383 pinctrl_esdhc2_1: esdhc2grp-1 {
385 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
386 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
387 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
388 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
389 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
390 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
396 pinctrl_i2c2_1: i2c2grp-1 {
398 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
399 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
403 pinctrl_i2c2_2: i2c2grp-2 {
405 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
406 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
412 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
414 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
415 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
416 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
417 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
418 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
419 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
420 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
421 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
422 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
423 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
424 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
425 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
426 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
427 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
428 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
429 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
430 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
431 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
432 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
433 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
434 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
435 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
436 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
437 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
438 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
439 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
445 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
447 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
448 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
449 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
450 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
451 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
452 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
453 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
454 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
455 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
456 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
457 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
458 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
459 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
460 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
461 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
462 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
463 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
464 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
465 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
466 MX51_PAD_DI_GP4__DI2_PIN15 0x5
472 pinctrl_pata_1: patagrp-1 {
474 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
475 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
476 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
477 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
478 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
479 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
480 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
481 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
482 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
483 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
484 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
485 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
486 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
487 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
488 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
489 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
490 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
491 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
492 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
493 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
494 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
495 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
496 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
497 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
498 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
499 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
500 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
501 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
502 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
508 pinctrl_uart1_1: uart1grp-1 {
510 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
511 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
512 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
513 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
519 pinctrl_uart2_1: uart2grp-1 {
521 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
522 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
528 pinctrl_uart3_1: uart3grp-1 {
530 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
531 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
532 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
533 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
537 pinctrl_uart3_2: uart3grp-2 {
539 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
540 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
546 pinctrl_kpp_1: kppgrp-1 {
548 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
549 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
550 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
551 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
552 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
553 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
554 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
555 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
563 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
564 reg = <0x73fb4000 0x4000>;
565 clocks = <&clks 37>, <&clks 38>;
566 clock-names = "ipg", "per";
572 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
573 reg = <0x73fb8000 0x4000>;
574 clocks = <&clks 39>, <&clks 40>;
575 clock-names = "ipg", "per";
579 uart1: serial@73fbc000 {
580 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
581 reg = <0x73fbc000 0x4000>;
583 clocks = <&clks 28>, <&clks 29>;
584 clock-names = "ipg", "per";
588 uart2: serial@73fc0000 {
589 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
590 reg = <0x73fc0000 0x4000>;
592 clocks = <&clks 30>, <&clks 31>;
593 clock-names = "ipg", "per";
598 compatible = "fsl,imx51-src";
599 reg = <0x73fd0000 0x4000>;
604 compatible = "fsl,imx51-ccm";
605 reg = <0x73fd4000 0x4000>;
606 interrupts = <0 71 0x04 0 72 0x04>;
611 aips@80000000 { /* AIPS2 */
612 compatible = "fsl,aips-bus", "simple-bus";
613 #address-cells = <1>;
615 reg = <0x80000000 0x10000000>;
618 ecspi2: ecspi@83fac000 {
619 #address-cells = <1>;
621 compatible = "fsl,imx51-ecspi";
622 reg = <0x83fac000 0x4000>;
624 clocks = <&clks 53>, <&clks 54>;
625 clock-names = "ipg", "per";
629 sdma: sdma@83fb0000 {
630 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
631 reg = <0x83fb0000 0x4000>;
633 clocks = <&clks 56>, <&clks 56>;
634 clock-names = "ipg", "ahb";
635 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
638 cspi: cspi@83fc0000 {
639 #address-cells = <1>;
641 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
642 reg = <0x83fc0000 0x4000>;
644 clocks = <&clks 55>, <&clks 55>;
645 clock-names = "ipg", "per";
650 #address-cells = <1>;
652 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
653 reg = <0x83fc4000 0x4000>;
660 #address-cells = <1>;
662 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
663 reg = <0x83fc8000 0x4000>;
670 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
671 reg = <0x83fcc000 0x4000>;
674 fsl,fifo-depth = <15>;
675 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
679 audmux: audmux@83fd0000 {
680 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
681 reg = <0x83fd0000 0x4000>;
686 compatible = "fsl,imx51-nand";
687 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
693 pata: pata@83fe0000 {
694 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
695 reg = <0x83fe0000 0x4000>;
697 clocks = <&clks 161>;
702 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
703 reg = <0x83fe8000 0x4000>;
706 fsl,fifo-depth = <15>;
707 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
711 fec: ethernet@83fec000 {
712 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
713 reg = <0x83fec000 0x4000>;
715 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
716 clock-names = "ipg", "ahb", "ptp";