2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 /include/ "skeleton.dtsi"
15 interrupt-parent = <&icoll>;
36 compatible = "arm,arm926ejs";
41 compatible = "simple-bus";
44 reg = <0x80000000 0x80000>;
48 compatible = "simple-bus";
51 reg = <0x80000000 0x3c900>;
54 icoll: interrupt-controller@80000000 {
55 compatible = "fsl,imx28-icoll", "fsl,icoll";
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
62 reg = <0x80002000 0x2000>;
68 compatible = "fsl,imx28-dma-apbh";
69 reg = <0x80004000 0x2000>;
74 reg = <0x80006000 0x800>;
80 compatible = "fsl,imx28-gpmi-nand";
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
84 reg-names = "gpmi-nand", "bch";
85 interrupts = <88>, <41>;
86 interrupt-names = "gpmi-dma", "bch";
88 clock-names = "gpmi_io";
89 fsl,gpmi-dma-channel = <4>;
96 reg = <0x80010000 0x2000>;
99 fsl,ssp-dma-channel = <0>;
104 #address-cells = <1>;
106 reg = <0x80012000 0x2000>;
107 interrupts = <97 83>;
109 fsl,ssp-dma-channel = <1>;
114 #address-cells = <1>;
116 reg = <0x80014000 0x2000>;
117 interrupts = <98 84>;
119 fsl,ssp-dma-channel = <2>;
124 #address-cells = <1>;
126 reg = <0x80016000 0x2000>;
127 interrupts = <99 85>;
129 fsl,ssp-dma-channel = <3>;
134 #address-cells = <1>;
136 compatible = "fsl,imx28-pinctrl", "simple-bus";
137 reg = <0x80018000 0x2000>;
140 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
144 interrupt-controller;
145 #interrupt-cells = <2>;
149 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
153 interrupt-controller;
154 #interrupt-cells = <2>;
158 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
162 interrupt-controller;
163 #interrupt-cells = <2>;
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
171 interrupt-controller;
172 #interrupt-cells = <2>;
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
180 interrupt-controller;
181 #interrupt-cells = <2>;
184 duart_pins_a: duart@0 {
187 0x3102 /* MX28_PAD_PWM0__DUART_RX */
188 0x3112 /* MX28_PAD_PWM1__DUART_TX */
190 fsl,drive-strength = <0>;
195 duart_pins_b: duart@1 {
198 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
199 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
201 fsl,drive-strength = <0>;
206 duart_4pins_a: duart-4pins@0 {
209 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
210 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
211 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
212 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
214 fsl,drive-strength = <0>;
219 gpmi_pins_a: gpmi-nand@0 {
222 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
223 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
224 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
225 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
226 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
227 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
228 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
229 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
230 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
231 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
232 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
233 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
234 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
235 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
236 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
238 fsl,drive-strength = <0>;
243 gpmi_status_cfg: gpmi-status-cfg {
245 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
246 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
247 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
249 fsl,drive-strength = <2>;
252 auart0_pins_a: auart0@0 {
255 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
256 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
257 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
258 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
260 fsl,drive-strength = <0>;
265 auart0_2pins_a: auart0-2pins@0 {
268 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
269 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
271 fsl,drive-strength = <0>;
276 auart1_pins_a: auart1@0 {
279 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
280 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
281 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
282 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
284 fsl,drive-strength = <0>;
289 auart1_2pins_a: auart1-2pins@0 {
292 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
293 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
295 fsl,drive-strength = <0>;
300 auart2_2pins_a: auart2-2pins@0 {
303 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
304 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
306 fsl,drive-strength = <0>;
311 auart3_pins_a: auart3@0 {
314 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
315 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
316 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
317 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
319 fsl,drive-strength = <0>;
324 auart3_2pins_a: auart3-2pins@0 {
327 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
328 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
330 fsl,drive-strength = <0>;
335 mac0_pins_a: mac0@0 {
338 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
339 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
340 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
341 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
342 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
343 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
344 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
345 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
346 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
348 fsl,drive-strength = <1>;
353 mac1_pins_a: mac1@0 {
356 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
357 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
358 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
359 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
360 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
361 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
363 fsl,drive-strength = <1>;
368 mmc0_8bit_pins_a: mmc0-8bit@0 {
371 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
372 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
373 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
374 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
375 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
376 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
377 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
378 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
379 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
380 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
381 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
383 fsl,drive-strength = <1>;
388 mmc0_4bit_pins_a: mmc0-4bit@0 {
391 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
392 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
393 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
394 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
395 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
396 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
397 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
399 fsl,drive-strength = <1>;
404 mmc0_cd_cfg: mmc0-cd-cfg {
406 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
411 mmc0_sck_cfg: mmc0-sck-cfg {
413 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
415 fsl,drive-strength = <2>;
419 i2c0_pins_a: i2c0@0 {
422 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
423 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
425 fsl,drive-strength = <1>;
430 i2c0_pins_b: i2c0@1 {
433 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
434 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
436 fsl,drive-strength = <1>;
441 i2c1_pins_a: i2c1@0 {
444 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
445 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
447 fsl,drive-strength = <1>;
452 saif0_pins_a: saif0@0 {
455 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
456 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
457 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
458 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
460 fsl,drive-strength = <2>;
465 saif1_pins_a: saif1@0 {
468 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
470 fsl,drive-strength = <2>;
475 pwm0_pins_a: pwm0@0 {
478 0x3100 /* MX28_PAD_PWM0__PWM_0 */
480 fsl,drive-strength = <0>;
485 pwm2_pins_a: pwm2@0 {
488 0x3120 /* MX28_PAD_PWM2__PWM_2 */
490 fsl,drive-strength = <0>;
495 pwm4_pins_a: pwm4@0 {
498 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
500 fsl,drive-strength = <0>;
505 lcdif_24bit_pins_a: lcdif-24bit@0 {
508 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
509 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
510 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
511 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
512 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
513 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
514 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
515 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
516 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
517 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
518 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
519 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
520 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
521 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
522 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
523 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
524 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
525 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
526 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
527 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
528 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
529 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
530 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
531 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
533 fsl,drive-strength = <0>;
538 can0_pins_a: can0@0 {
541 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
542 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
544 fsl,drive-strength = <0>;
549 can1_pins_a: can1@0 {
552 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
553 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
555 fsl,drive-strength = <0>;
560 spi2_pins_a: spi2@0 {
563 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
564 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
565 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
566 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
568 fsl,drive-strength = <1>;
573 usbphy0_pins_a: usbphy0@0 {
576 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
578 fsl,drive-strength = <2>;
583 usbphy0_pins_b: usbphy0@1 {
586 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
588 fsl,drive-strength = <2>;
593 usbphy1_pins_a: usbphy1@0 {
596 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
598 fsl,drive-strength = <2>;
605 reg = <0x8001c000 0x2000>;
611 reg = <0x80022000 0x2000>;
616 compatible = "fsl,imx28-dma-apbx";
617 reg = <0x80024000 0x2000>;
622 reg = <0x80028000 0x2000>;
623 interrupts = <52 53 54>;
628 reg = <0x8002a000 0x2000>;
634 reg = <0x8002c000 0x2000>;
639 reg = <0x8002e000 0x2000>;
644 compatible = "fsl,imx28-lcdif";
645 reg = <0x80030000 0x2000>;
646 interrupts = <38 86>;
652 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
653 reg = <0x80032000 0x2000>;
655 clocks = <&clks 58>, <&clks 58>;
656 clock-names = "ipg", "per";
661 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
662 reg = <0x80034000 0x2000>;
664 clocks = <&clks 59>, <&clks 59>;
665 clock-names = "ipg", "per";
670 reg = <0x8003c000 0x200>;
674 simgpmisel@8003c200 {
675 reg = <0x8003c200 0x100>;
680 reg = <0x8003c300 0x100>;
685 reg = <0x8003c400 0x100>;
690 reg = <0x8003c500 0x100>;
695 reg = <0x8003c700 0x100>;
700 reg = <0x8003c800 0x100>;
706 compatible = "simple-bus";
707 #address-cells = <1>;
709 reg = <0x80040000 0x40000>;
712 clks: clkctrl@80040000 {
713 compatible = "fsl,imx28-clkctrl";
714 reg = <0x80040000 0x2000>;
718 saif0: saif@80042000 {
719 compatible = "fsl,imx28-saif";
720 reg = <0x80042000 0x2000>;
721 interrupts = <59 80>;
723 fsl,saif-dma-channel = <4>;
728 reg = <0x80044000 0x2000>;
732 saif1: saif@80046000 {
733 compatible = "fsl,imx28-saif";
734 reg = <0x80046000 0x2000>;
735 interrupts = <58 81>;
737 fsl,saif-dma-channel = <5>;
742 compatible = "fsl,imx28-lradc";
743 reg = <0x80050000 0x2000>;
744 interrupts = <10 14 15 16 17 18 19
750 reg = <0x80054000 0x2000>;
751 interrupts = <45 66>;
756 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
757 reg = <0x80056000 0x2000>;
762 #address-cells = <1>;
764 compatible = "fsl,imx28-i2c";
765 reg = <0x80058000 0x2000>;
766 interrupts = <111 68>;
767 clock-frequency = <100000>;
768 fsl,i2c-dma-channel = <6>;
773 #address-cells = <1>;
775 compatible = "fsl,imx28-i2c";
776 reg = <0x8005a000 0x2000>;
777 interrupts = <110 69>;
778 clock-frequency = <100000>;
779 fsl,i2c-dma-channel = <7>;
784 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
785 reg = <0x80064000 0x2000>;
788 fsl,pwm-number = <8>;
793 compatible = "fsl,imx28-timrot", "fsl,timrot";
794 reg = <0x80068000 0x2000>;
795 interrupts = <48 49 50 51>;
798 auart0: serial@8006a000 {
799 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
800 reg = <0x8006a000 0x2000>;
801 interrupts = <112 70 71>;
806 auart1: serial@8006c000 {
807 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
808 reg = <0x8006c000 0x2000>;
809 interrupts = <113 72 73>;
814 auart2: serial@8006e000 {
815 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
816 reg = <0x8006e000 0x2000>;
817 interrupts = <114 74 75>;
822 auart3: serial@80070000 {
823 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
824 reg = <0x80070000 0x2000>;
825 interrupts = <115 76 77>;
830 auart4: serial@80072000 {
831 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
832 reg = <0x80072000 0x2000>;
833 interrupts = <116 78 79>;
838 duart: serial@80074000 {
839 compatible = "arm,pl011", "arm,primecell";
840 reg = <0x80074000 0x1000>;
842 clocks = <&clks 45>, <&clks 26>;
843 clock-names = "uart", "apb_pclk";
847 usbphy0: usbphy@8007c000 {
848 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
849 reg = <0x8007c000 0x2000>;
854 usbphy1: usbphy@8007e000 {
855 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
856 reg = <0x8007e000 0x2000>;
864 compatible = "simple-bus";
865 #address-cells = <1>;
867 reg = <0x80080000 0x80000>;
871 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
872 reg = <0x80080000 0x10000>;
875 fsl,usbphy = <&usbphy0>;
880 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
881 reg = <0x80090000 0x10000>;
884 fsl,usbphy = <&usbphy1>;
889 reg = <0x800c0000 0x10000>;
893 mac0: ethernet@800f0000 {
894 compatible = "fsl,imx28-fec";
895 reg = <0x800f0000 0x4000>;
897 clocks = <&clks 57>, <&clks 57>;
898 clock-names = "ipg", "ahb";
902 mac1: ethernet@800f4000 {
903 compatible = "fsl,imx28-fec";
904 reg = <0x800f4000 0x4000>;
906 clocks = <&clks 57>, <&clks 57>;
907 clock-names = "ipg", "ahb";
912 reg = <0x800f8000 0x8000>;