1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for Cortina systems Gemini SoC
6 /include/ "skeleton.dtsi"
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/cortina,gemini-clock.h>
10 #include <dt-bindings/reset/cortina,gemini-reset.h>
11 #include <dt-bindings/gpio/gpio.h>
18 compatible = "simple-bus";
19 interrupt-parent = <&intcon>;
22 compatible = "cortina,gemini-flash", "cfi-flash";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pflash_default_pins>;
32 syscon: syscon@40000000 {
33 compatible = "cortina,gemini-syscon",
34 "syscon", "simple-mfd";
35 reg = <0x40000000 0x1000>;
40 compatible = "syscon-reboot";
42 /* GLOBAL_RESET register */
44 /* RESET_GLOBAL | RESET_CPU1 */
49 compatible = "cortina,gemini-pinctrl";
51 /* Hog the DRAM pins */
52 pinctrl-names = "default";
53 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
54 <&vcontrol_default_pins>;
56 dram_default_pins: pinctrl-dram {
62 rtc_default_pins: pinctrl-rtc {
68 power_default_pins: pinctrl-power {
74 cir_default_pins: pinctrl-cir {
80 system_default_pins: pinctrl-system {
86 vcontrol_default_pins: pinctrl-vcontrol {
88 function = "vcontrol";
89 groups = "vcontrolgrp";
92 ice_default_pins: pinctrl-ice {
98 uart_default_pins: pinctrl-uart {
101 groups = "uartrxtxgrp";
104 pflash_default_pins: pinctrl-pflash {
107 groups = "pflashgrp";
110 usb_default_pins: pinctrl-usb {
116 gmii_default_pins: pinctrl-gmii {
122 pci_default_pins: pinctrl-pci {
128 sata_default_pins: pinctrl-sata {
134 /* Activate both groups of pins for this state */
135 sata_and_ide_pins: pinctrl-sata-ide {
145 tvc_default_pins: pinctrl-tvc {
155 compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
156 reg = <0x41000000 0x1000>;
157 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
158 resets = <&syscon GEMINI_RESET_WDOG>;
159 clocks = <&syscon GEMINI_CLK_APB>;
160 clock-names = "PCLK";
163 uart0: serial@42000000 {
164 compatible = "ns16550a";
165 reg = <0x42000000 0x100>;
166 resets = <&syscon GEMINI_RESET_UART>;
167 clocks = <&syscon GEMINI_CLK_UART>;
168 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&uart_default_pins>;
175 compatible = "faraday,fttmr010";
176 reg = <0x43000000 0x1000>;
177 interrupt-parent = <&intcon>;
178 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
179 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
180 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
181 resets = <&syscon GEMINI_RESET_TIMER>;
182 /* APB clock or RTC clock */
183 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
184 clock-names = "PCLK", "EXTCLK";
189 compatible = "cortina,gemini-rtc";
190 reg = <0x45000000 0x100>;
191 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
192 resets = <&syscon GEMINI_RESET_RTC>;
193 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
194 clock-names = "PCLK", "EXTCLK";
195 pinctrl-names = "default";
196 pinctrl-0 = <&rtc_default_pins>;
199 sata: sata@46000000 {
200 compatible = "cortina,gemini-sata-bridge";
201 reg = <0x46000000 0x100>;
202 resets = <&syscon GEMINI_RESET_SATA0>,
203 <&syscon GEMINI_RESET_SATA1>;
204 reset-names = "sata0", "sata1";
205 clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
206 <&syscon GEMINI_CLK_GATE_SATA1>;
207 clock-names = "SATA0_PCLK", "SATA1_PCLK";
209 * This defines the special "ide" state that needs
210 * to be explicitly enabled to enable the IDE pins,
211 * as these pins are normally used for other things.
213 pinctrl-names = "default", "ide";
214 pinctrl-0 = <&sata_default_pins>;
215 pinctrl-1 = <&sata_and_ide_pins>;
220 intcon: interrupt-controller@48000000 {
221 compatible = "faraday,ftintc010";
222 reg = <0x48000000 0x1000>;
223 resets = <&syscon GEMINI_RESET_INTCON0>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
228 power-controller@4b000000 {
229 compatible = "cortina,gemini-power-controller";
230 reg = <0x4b000000 0x100>;
231 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&power_default_pins>;
236 gpio0: gpio@4d000000 {
237 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
238 reg = <0x4d000000 0x100>;
239 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
240 resets = <&syscon GEMINI_RESET_GPIO0>;
241 clocks = <&syscon GEMINI_CLK_APB>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
248 gpio1: gpio@4e000000 {
249 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
250 reg = <0x4e000000 0x100>;
251 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
252 resets = <&syscon GEMINI_RESET_GPIO1>;
253 clocks = <&syscon GEMINI_CLK_APB>;
256 interrupt-controller;
257 #interrupt-cells = <2>;
260 gpio2: gpio@4f000000 {
261 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
262 reg = <0x4f000000 0x100>;
263 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
264 resets = <&syscon GEMINI_RESET_GPIO2>;
265 clocks = <&syscon GEMINI_CLK_APB>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
273 compatible = "cortina,gemini-pci", "faraday,ftpci100";
275 * The first 256 bytes in the IO range is actually used
276 * to configure the host bridge.
278 reg = <0x50000000 0x100>;
279 resets = <&syscon GEMINI_RESET_PCI>;
280 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
281 clock-names = "PCLK", "PCICLK";
282 pinctrl-names = "default";
283 pinctrl-0 = <&pci_default_pins>;
284 #address-cells = <3>;
286 #interrupt-cells = <1>;
289 bus-range = <0x00 0xff>;
290 /* PCI ranges mappings */
292 /* 1MiB I/O space 0x50000000-0x500fffff */
293 <0x01000000 0 0 0x50000000 0 0x00100000>,
294 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
295 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
299 /* 128MiB at 0x00000000-0x07ffffff */
300 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
301 /* 64MiB at 0x00000000-0x03ffffff */
302 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
303 /* 64MiB at 0x00000000-0x03ffffff */
304 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
307 * This PCI host bridge variant has a cascaded interrupt
308 * controller embedded in the host bridge.
310 pci_intc: interrupt-controller {
311 interrupt-parent = <&intcon>;
312 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <1>;
320 compatible = "cortina,gemini-pata", "faraday,ftide010";
321 reg = <0x63000000 0x1000>;
322 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
323 resets = <&syscon GEMINI_RESET_IDE>;
324 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
325 clock-names = "PCLK";
331 compatible = "cortina,gemini-pata", "faraday,ftide010";
332 reg = <0x63400000 0x1000>;
333 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
334 resets = <&syscon GEMINI_RESET_IDE>;
335 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
336 clock-names = "PCLK";
341 dma-controller@67000000 {
342 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
343 /* Faraday Technology FTDMAC020 variant */
344 arm,primecell-periphid = <0x0003b080>;
345 reg = <0x67000000 0x1000>;
346 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
347 resets = <&syscon GEMINI_RESET_DMAC>;
348 clocks = <&syscon GEMINI_CLK_AHB>;
349 clock-names = "apb_pclk";
350 /* Bus interface AHB1 (AHB0) is totally tilted */
351 lli-bus-interface-ahb2;
352 mem-bus-interface-ahb2;
353 memcpy-burst-size = <256>;
354 memcpy-bus-width = <32>;
358 display-controller@6a000000 {
359 compatible = "cortina,gemini-tvc", "faraday,tve200";
360 reg = <0x6a000000 0x1000>;
361 interrupts = <13 IRQ_TYPE_EDGE_RISING>;
362 resets = <&syscon GEMINI_RESET_TVC>;
363 clocks = <&syscon GEMINI_CLK_GATE_TVC>,
364 <&syscon GEMINI_CLK_TVC>;
365 clock-names = "PCLK", "TVE";
366 pinctrl-names = "default";
367 pinctrl-0 = <&tvc_default_pins>;
368 #address-cells = <1>;