2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 samsung,power-domain = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
255 isp_pd: power-domain@10044020 {
256 compatible = "samsung,exynos4210-pd";
257 reg = <0x10044020 0x20>;
260 mfc_pd: power-domain@10044060 {
261 compatible = "samsung,exynos4210-pd";
262 reg = <0x10044060 0x20>;
265 disp_pd: power-domain@100440C0 {
266 compatible = "samsung,exynos4210-pd";
267 reg = <0x100440C0 0x20>;
270 msc_pd: power-domain@10044120 {
271 compatible = "samsung,exynos4210-pd";
272 reg = <0x10044120 0x20>;
275 pinctrl_0: pinctrl@13400000 {
276 compatible = "samsung,exynos5420-pinctrl";
277 reg = <0x13400000 0x1000>;
278 interrupts = <0 45 0>;
280 wakeup-interrupt-controller {
281 compatible = "samsung,exynos4210-wakeup-eint";
282 interrupt-parent = <&gic>;
283 interrupts = <0 32 0>;
287 pinctrl_1: pinctrl@13410000 {
288 compatible = "samsung,exynos5420-pinctrl";
289 reg = <0x13410000 0x1000>;
290 interrupts = <0 78 0>;
293 pinctrl_2: pinctrl@14000000 {
294 compatible = "samsung,exynos5420-pinctrl";
295 reg = <0x14000000 0x1000>;
296 interrupts = <0 46 0>;
299 pinctrl_3: pinctrl@14010000 {
300 compatible = "samsung,exynos5420-pinctrl";
301 reg = <0x14010000 0x1000>;
302 interrupts = <0 50 0>;
305 pinctrl_4: pinctrl@03860000 {
306 compatible = "samsung,exynos5420-pinctrl";
307 reg = <0x03860000 0x1000>;
308 interrupts = <0 47 0>;
312 clocks = <&clock CLK_RTC>;
318 #address-cells = <1>;
320 compatible = "arm,amba-bus";
321 interrupt-parent = <&gic>;
324 adma: adma@03880000 {
325 compatible = "arm,pl330", "arm,primecell";
326 reg = <0x03880000 0x1000>;
327 interrupts = <0 110 0>;
328 clocks = <&clock_audss EXYNOS_ADMA>;
329 clock-names = "apb_pclk";
332 #dma-requests = <16>;
335 pdma0: pdma@121A0000 {
336 compatible = "arm,pl330", "arm,primecell";
337 reg = <0x121A0000 0x1000>;
338 interrupts = <0 34 0>;
339 clocks = <&clock CLK_PDMA0>;
340 clock-names = "apb_pclk";
343 #dma-requests = <32>;
346 pdma1: pdma@121B0000 {
347 compatible = "arm,pl330", "arm,primecell";
348 reg = <0x121B0000 0x1000>;
349 interrupts = <0 35 0>;
350 clocks = <&clock CLK_PDMA1>;
351 clock-names = "apb_pclk";
354 #dma-requests = <32>;
357 mdma0: mdma@10800000 {
358 compatible = "arm,pl330", "arm,primecell";
359 reg = <0x10800000 0x1000>;
360 interrupts = <0 33 0>;
361 clocks = <&clock CLK_MDMA0>;
362 clock-names = "apb_pclk";
368 mdma1: mdma@11C10000 {
369 compatible = "arm,pl330", "arm,primecell";
370 reg = <0x11C10000 0x1000>;
371 interrupts = <0 124 0>;
372 clocks = <&clock CLK_MDMA1>;
373 clock-names = "apb_pclk";
378 * MDMA1 can support both secure and non-secure
379 * AXI transactions. When this is enabled in the kernel
380 * for boards that run in secure mode, we are getting
381 * imprecise external aborts causing the kernel to oops.
388 compatible = "samsung,exynos5420-i2s";
389 reg = <0x03830000 0x100>;
393 dma-names = "tx", "rx", "tx-sec";
394 clocks = <&clock_audss EXYNOS_I2S_BUS>,
395 <&clock_audss EXYNOS_I2S_BUS>,
396 <&clock_audss EXYNOS_SCLK_I2S>;
397 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
398 samsung,idma-addr = <0x03000000>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2s0_bus>;
405 compatible = "samsung,exynos5420-i2s";
406 reg = <0x12D60000 0x100>;
409 dma-names = "tx", "rx";
410 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
411 clock-names = "iis", "i2s_opclk0";
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2s1_bus>;
418 compatible = "samsung,exynos5420-i2s";
419 reg = <0x12D70000 0x100>;
422 dma-names = "tx", "rx";
423 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
424 clock-names = "iis", "i2s_opclk0";
425 pinctrl-names = "default";
426 pinctrl-0 = <&i2s2_bus>;
430 spi_0: spi@12d20000 {
431 compatible = "samsung,exynos4210-spi";
432 reg = <0x12d20000 0x100>;
433 interrupts = <0 68 0>;
436 dma-names = "tx", "rx";
437 #address-cells = <1>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&spi0_bus>;
441 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
442 clock-names = "spi", "spi_busclk0";
446 spi_1: spi@12d30000 {
447 compatible = "samsung,exynos4210-spi";
448 reg = <0x12d30000 0x100>;
449 interrupts = <0 69 0>;
452 dma-names = "tx", "rx";
453 #address-cells = <1>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&spi1_bus>;
457 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
458 clock-names = "spi", "spi_busclk0";
462 spi_2: spi@12d40000 {
463 compatible = "samsung,exynos4210-spi";
464 reg = <0x12d40000 0x100>;
465 interrupts = <0 70 0>;
468 dma-names = "tx", "rx";
469 #address-cells = <1>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi2_bus>;
473 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
474 clock-names = "spi", "spi_busclk0";
478 uart_0: serial@12C00000 {
479 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
480 clock-names = "uart", "clk_uart_baud0";
483 uart_1: serial@12C10000 {
484 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
485 clock-names = "uart", "clk_uart_baud0";
488 uart_2: serial@12C20000 {
489 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
490 clock-names = "uart", "clk_uart_baud0";
493 uart_3: serial@12C30000 {
494 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
495 clock-names = "uart", "clk_uart_baud0";
499 compatible = "samsung,exynos4210-pwm";
500 reg = <0x12dd0000 0x100>;
501 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
503 clocks = <&clock CLK_PWM>;
504 clock-names = "timers";
507 dp_phy: video-phy@10040728 {
508 compatible = "samsung,exynos5250-dp-video-phy";
509 reg = <0x10040728 4>;
513 dp: dp-controller@145B0000 {
514 clocks = <&clock CLK_DP1>;
520 fimd: fimd@14400000 {
521 samsung,power-domain = <&disp_pd>;
522 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
523 clock-names = "sclk_fimd", "fimd";
527 compatible = "samsung,exynos-adc-v2";
528 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
529 interrupts = <0 106 0>;
530 clocks = <&clock CLK_TSADC>;
532 #io-channel-cells = <1>;
537 i2c_0: i2c@12C60000 {
538 compatible = "samsung,s3c2440-i2c";
539 reg = <0x12C60000 0x100>;
540 interrupts = <0 56 0>;
541 #address-cells = <1>;
543 clocks = <&clock CLK_I2C0>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2c0_bus>;
550 i2c_1: i2c@12C70000 {
551 compatible = "samsung,s3c2440-i2c";
552 reg = <0x12C70000 0x100>;
553 interrupts = <0 57 0>;
554 #address-cells = <1>;
556 clocks = <&clock CLK_I2C1>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&i2c1_bus>;
563 i2c_2: i2c@12C80000 {
564 compatible = "samsung,s3c2440-i2c";
565 reg = <0x12C80000 0x100>;
566 interrupts = <0 58 0>;
567 #address-cells = <1>;
569 clocks = <&clock CLK_I2C2>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_bus>;
576 i2c_3: i2c@12C90000 {
577 compatible = "samsung,s3c2440-i2c";
578 reg = <0x12C90000 0x100>;
579 interrupts = <0 59 0>;
580 #address-cells = <1>;
582 clocks = <&clock CLK_I2C3>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c3_bus>;
589 hsi2c_4: i2c@12CA0000 {
590 compatible = "samsung,exynos5-hsi2c";
591 reg = <0x12CA0000 0x1000>;
592 interrupts = <0 60 0>;
593 #address-cells = <1>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c4_hs_bus>;
597 clocks = <&clock CLK_USI0>;
598 clock-names = "hsi2c";
602 hsi2c_5: i2c@12CB0000 {
603 compatible = "samsung,exynos5-hsi2c";
604 reg = <0x12CB0000 0x1000>;
605 interrupts = <0 61 0>;
606 #address-cells = <1>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&i2c5_hs_bus>;
610 clocks = <&clock CLK_USI1>;
611 clock-names = "hsi2c";
615 hsi2c_6: i2c@12CC0000 {
616 compatible = "samsung,exynos5-hsi2c";
617 reg = <0x12CC0000 0x1000>;
618 interrupts = <0 62 0>;
619 #address-cells = <1>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c6_hs_bus>;
623 clocks = <&clock CLK_USI2>;
624 clock-names = "hsi2c";
628 hsi2c_7: i2c@12CD0000 {
629 compatible = "samsung,exynos5-hsi2c";
630 reg = <0x12CD0000 0x1000>;
631 interrupts = <0 63 0>;
632 #address-cells = <1>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&i2c7_hs_bus>;
636 clocks = <&clock CLK_USI3>;
637 clock-names = "hsi2c";
641 hsi2c_8: i2c@12E00000 {
642 compatible = "samsung,exynos5-hsi2c";
643 reg = <0x12E00000 0x1000>;
644 interrupts = <0 87 0>;
645 #address-cells = <1>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&i2c8_hs_bus>;
649 clocks = <&clock CLK_USI4>;
650 clock-names = "hsi2c";
654 hsi2c_9: i2c@12E10000 {
655 compatible = "samsung,exynos5-hsi2c";
656 reg = <0x12E10000 0x1000>;
657 interrupts = <0 88 0>;
658 #address-cells = <1>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&i2c9_hs_bus>;
662 clocks = <&clock CLK_USI5>;
663 clock-names = "hsi2c";
667 hsi2c_10: i2c@12E20000 {
668 compatible = "samsung,exynos5-hsi2c";
669 reg = <0x12E20000 0x1000>;
670 interrupts = <0 203 0>;
671 #address-cells = <1>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&i2c10_hs_bus>;
675 clocks = <&clock CLK_USI6>;
676 clock-names = "hsi2c";
680 hdmi: hdmi@14530000 {
681 compatible = "samsung,exynos5420-hdmi";
682 reg = <0x14530000 0x70000>;
683 interrupts = <0 95 0>;
684 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
685 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
686 <&clock CLK_MOUT_HDMI>;
687 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
688 "sclk_hdmiphy", "mout_hdmi";
693 hdmiphy: hdmiphy@145D0000 {
694 reg = <0x145D0000 0x20>;
697 mixer: mixer@14450000 {
698 compatible = "samsung,exynos5420-mixer";
699 reg = <0x14450000 0x10000>;
700 interrupts = <0 94 0>;
701 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
702 clock-names = "mixer", "sclk_hdmi";
705 gsc_0: video-scaler@13e00000 {
706 compatible = "samsung,exynos5-gsc";
707 reg = <0x13e00000 0x1000>;
708 interrupts = <0 85 0>;
709 clocks = <&clock CLK_GSCL0>;
710 clock-names = "gscl";
711 samsung,power-domain = <&gsc_pd>;
714 gsc_1: video-scaler@13e10000 {
715 compatible = "samsung,exynos5-gsc";
716 reg = <0x13e10000 0x1000>;
717 interrupts = <0 86 0>;
718 clocks = <&clock CLK_GSCL1>;
719 clock-names = "gscl";
720 samsung,power-domain = <&gsc_pd>;
723 pmu_system_controller: system-controller@10040000 {
724 compatible = "samsung,exynos5420-pmu", "syscon";
725 reg = <0x10040000 0x5000>;
728 sysreg_system_controller: syscon@10050000 {
729 compatible = "samsung,exynos5-sysreg", "syscon";
730 reg = <0x10050000 0x5000>;
733 tmu_cpu0: tmu@10060000 {
734 compatible = "samsung,exynos5420-tmu";
735 reg = <0x10060000 0x100>;
736 interrupts = <0 65 0>;
737 clocks = <&clock CLK_TMU>;
738 clock-names = "tmu_apbif";
741 tmu_cpu1: tmu@10064000 {
742 compatible = "samsung,exynos5420-tmu";
743 reg = <0x10064000 0x100>;
744 interrupts = <0 183 0>;
745 clocks = <&clock CLK_TMU>;
746 clock-names = "tmu_apbif";
749 tmu_cpu2: tmu@10068000 {
750 compatible = "samsung,exynos5420-tmu-ext-triminfo";
751 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
752 interrupts = <0 184 0>;
753 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
754 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
757 tmu_cpu3: tmu@1006c000 {
758 compatible = "samsung,exynos5420-tmu-ext-triminfo";
759 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
760 interrupts = <0 185 0>;
761 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
762 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
765 tmu_gpu: tmu@100a0000 {
766 compatible = "samsung,exynos5420-tmu-ext-triminfo";
767 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
768 interrupts = <0 215 0>;
769 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
770 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
773 watchdog: watchdog@101D0000 {
774 compatible = "samsung,exynos5420-wdt";
775 reg = <0x101D0000 0x100>;
776 interrupts = <0 42 0>;
777 clocks = <&clock CLK_WDT>;
778 clock-names = "watchdog";
779 samsung,syscon-phandle = <&pmu_system_controller>;
783 compatible = "samsung,exynos4210-secss";
784 reg = <0x10830000 0x10000>;
785 interrupts = <0 112 0>;
786 clocks = <&clock 471>;
787 clock-names = "secss";
790 usbdrd3_0: usb@12000000 {
791 compatible = "samsung,exynos5250-dwusb3";
792 clocks = <&clock CLK_USBD300>;
793 clock-names = "usbdrd30";
794 #address-cells = <1>;
799 compatible = "snps,dwc3";
800 reg = <0x12000000 0x10000>;
801 interrupts = <0 72 0>;
802 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
803 phy-names = "usb2-phy", "usb3-phy";
807 usbdrd_phy0: phy@12100000 {
808 compatible = "samsung,exynos5420-usbdrd-phy";
809 reg = <0x12100000 0x100>;
810 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
811 clock-names = "phy", "ref";
812 samsung,pmu-syscon = <&pmu_system_controller>;
816 usbdrd3_1: usb@12400000 {
817 compatible = "samsung,exynos5250-dwusb3";
818 clocks = <&clock CLK_USBD301>;
819 clock-names = "usbdrd30";
820 #address-cells = <1>;
825 compatible = "snps,dwc3";
826 reg = <0x12400000 0x10000>;
827 interrupts = <0 73 0>;
828 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
829 phy-names = "usb2-phy", "usb3-phy";
833 usbdrd_phy1: phy@12500000 {
834 compatible = "samsung,exynos5420-usbdrd-phy";
835 reg = <0x12500000 0x100>;
836 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
837 clock-names = "phy", "ref";
838 samsung,pmu-syscon = <&pmu_system_controller>;