2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include "exynos54xx.dtsi"
17 #include <dt-bindings/clock/exynos5420.h>
18 #include <dt-bindings/clock/exynos-audss-clk.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 compatible = "samsung,exynos5420", "samsung,exynos5";
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 pinctrl3 = &pinctrl_3;
32 pinctrl4 = &pinctrl_4;
44 * The 'cpus' node is not present here but instead it is provided
45 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
49 cluster_a15_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
53 opp-hz = /bits/ 64 <1800000000>;
54 opp-microvolt = <1250000>;
55 clock-latency-ns = <140000>;
58 opp-hz = /bits/ 64 <1700000000>;
59 opp-microvolt = <1212500>;
60 clock-latency-ns = <140000>;
63 opp-hz = /bits/ 64 <1600000000>;
64 opp-microvolt = <1175000>;
65 clock-latency-ns = <140000>;
68 opp-hz = /bits/ 64 <1500000000>;
69 opp-microvolt = <1137500>;
70 clock-latency-ns = <140000>;
73 opp-hz = /bits/ 64 <1400000000>;
74 opp-microvolt = <1112500>;
75 clock-latency-ns = <140000>;
78 opp-hz = /bits/ 64 <1300000000>;
79 opp-microvolt = <1062500>;
80 clock-latency-ns = <140000>;
83 opp-hz = /bits/ 64 <1200000000>;
84 opp-microvolt = <1037500>;
85 clock-latency-ns = <140000>;
88 opp-hz = /bits/ 64 <1100000000>;
89 opp-microvolt = <1012500>;
90 clock-latency-ns = <140000>;
93 opp-hz = /bits/ 64 <1000000000>;
94 opp-microvolt = < 987500>;
95 clock-latency-ns = <140000>;
98 opp-hz = /bits/ 64 <900000000>;
99 opp-microvolt = < 962500>;
100 clock-latency-ns = <140000>;
103 opp-hz = /bits/ 64 <800000000>;
104 opp-microvolt = < 937500>;
105 clock-latency-ns = <140000>;
108 opp-hz = /bits/ 64 <700000000>;
109 opp-microvolt = < 912500>;
110 clock-latency-ns = <140000>;
114 cluster_a7_opp_table: opp_table1 {
115 compatible = "operating-points-v2";
118 opp-hz = /bits/ 64 <1300000000>;
119 opp-microvolt = <1275000>;
120 clock-latency-ns = <140000>;
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <1212500>;
125 clock-latency-ns = <140000>;
128 opp-hz = /bits/ 64 <1100000000>;
129 opp-microvolt = <1162500>;
130 clock-latency-ns = <140000>;
133 opp-hz = /bits/ 64 <1000000000>;
134 opp-microvolt = <1112500>;
135 clock-latency-ns = <140000>;
138 opp-hz = /bits/ 64 <900000000>;
139 opp-microvolt = <1062500>;
140 clock-latency-ns = <140000>;
143 opp-hz = /bits/ 64 <800000000>;
144 opp-microvolt = <1025000>;
145 clock-latency-ns = <140000>;
148 opp-hz = /bits/ 64 <700000000>;
149 opp-microvolt = <975000>;
150 clock-latency-ns = <140000>;
153 opp-hz = /bits/ 64 <600000000>;
154 opp-microvolt = <937500>;
155 clock-latency-ns = <140000>;
160 compatible = "arm,cci-400";
161 #address-cells = <1>;
163 reg = <0x10d20000 0x1000>;
164 ranges = <0x0 0x10d20000 0x6000>;
166 cci_control0: slave-if@4000 {
167 compatible = "arm,cci-400-ctrl-if";
168 interface-type = "ace";
169 reg = <0x4000 0x1000>;
171 cci_control1: slave-if@5000 {
172 compatible = "arm,cci-400-ctrl-if";
173 interface-type = "ace";
174 reg = <0x5000 0x1000>;
178 clock: clock-controller@10010000 {
179 compatible = "samsung,exynos5420-clock";
180 reg = <0x10010000 0x30000>;
184 clock_audss: audss-clock-controller@3810000 {
185 compatible = "samsung,exynos5420-audss-clock";
186 reg = <0x03810000 0x0C>;
188 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
189 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
190 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
191 power-domains = <&mau_pd>;
194 mfc: codec@11000000 {
195 compatible = "samsung,mfc-v7";
196 reg = <0x11000000 0x10000>;
197 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clock CLK_MFC>;
200 power-domains = <&mfc_pd>;
201 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
202 iommu-names = "left", "right";
205 mmc_0: mmc@12200000 {
206 compatible = "samsung,exynos5420-dw-mshc-smu";
207 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
208 #address-cells = <1>;
210 reg = <0x12200000 0x2000>;
211 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
212 clock-names = "biu", "ciu";
217 mmc_1: mmc@12210000 {
218 compatible = "samsung,exynos5420-dw-mshc-smu";
219 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
220 #address-cells = <1>;
222 reg = <0x12210000 0x2000>;
223 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
224 clock-names = "biu", "ciu";
229 mmc_2: mmc@12220000 {
230 compatible = "samsung,exynos5420-dw-mshc";
231 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
232 #address-cells = <1>;
234 reg = <0x12220000 0x1000>;
235 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
236 clock-names = "biu", "ciu";
241 nocp_mem0_0: nocp@10CA1000 {
242 compatible = "samsung,exynos5420-nocp";
243 reg = <0x10CA1000 0x200>;
247 nocp_mem0_1: nocp@10CA1400 {
248 compatible = "samsung,exynos5420-nocp";
249 reg = <0x10CA1400 0x200>;
253 nocp_mem1_0: nocp@10CA1800 {
254 compatible = "samsung,exynos5420-nocp";
255 reg = <0x10CA1800 0x200>;
259 nocp_mem1_1: nocp@10CA1C00 {
260 compatible = "samsung,exynos5420-nocp";
261 reg = <0x10CA1C00 0x200>;
265 nocp_g3d_0: nocp@11A51000 {
266 compatible = "samsung,exynos5420-nocp";
267 reg = <0x11A51000 0x200>;
271 nocp_g3d_1: nocp@11A51400 {
272 compatible = "samsung,exynos5420-nocp";
273 reg = <0x11A51400 0x200>;
277 gsc_pd: power-domain@10044000 {
278 compatible = "samsung,exynos4210-pd";
279 reg = <0x10044000 0x20>;
280 #power-domain-cells = <0>;
282 clocks = <&clock CLK_FIN_PLL>,
283 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
284 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
285 clock-names = "oscclk", "clk0", "asb0", "asb1";
288 isp_pd: power-domain@10044020 {
289 compatible = "samsung,exynos4210-pd";
290 reg = <0x10044020 0x20>;
291 #power-domain-cells = <0>;
295 mfc_pd: power-domain@10044060 {
296 compatible = "samsung,exynos4210-pd";
297 reg = <0x10044060 0x20>;
298 clocks = <&clock CLK_FIN_PLL>,
299 <&clock CLK_MOUT_USER_ACLK333>,
300 <&clock CLK_ACLK333>;
301 clock-names = "oscclk", "clk0","asb0";
302 #power-domain-cells = <0>;
306 msc_pd: power-domain@10044120 {
307 compatible = "samsung,exynos4210-pd";
308 reg = <0x10044120 0x20>;
309 #power-domain-cells = <0>;
313 disp_pd: power-domain@100440C0 {
314 compatible = "samsung,exynos4210-pd";
315 reg = <0x100440C0 0x20>;
316 #power-domain-cells = <0>;
318 clocks = <&clock CLK_FIN_PLL>,
319 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
320 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
321 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
322 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
323 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
326 mau_pd: power-domain@100440E0 {
327 compatible = "samsung,exynos4210-pd";
328 reg = <0x100440E0 0x20>;
329 #power-domain-cells = <0>;
333 pinctrl_0: pinctrl@13400000 {
334 compatible = "samsung,exynos5420-pinctrl";
335 reg = <0x13400000 0x1000>;
336 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
338 wakeup-interrupt-controller {
339 compatible = "samsung,exynos4210-wakeup-eint";
340 interrupt-parent = <&gic>;
341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
345 pinctrl_1: pinctrl@13410000 {
346 compatible = "samsung,exynos5420-pinctrl";
347 reg = <0x13410000 0x1000>;
348 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
351 pinctrl_2: pinctrl@14000000 {
352 compatible = "samsung,exynos5420-pinctrl";
353 reg = <0x14000000 0x1000>;
354 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
357 pinctrl_3: pinctrl@14010000 {
358 compatible = "samsung,exynos5420-pinctrl";
359 reg = <0x14010000 0x1000>;
360 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
363 pinctrl_4: pinctrl@3860000 {
364 compatible = "samsung,exynos5420-pinctrl";
365 reg = <0x03860000 0x1000>;
366 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
367 power-domains = <&mau_pd>;
371 #address-cells = <1>;
373 compatible = "simple-bus";
374 interrupt-parent = <&gic>;
378 compatible = "arm,pl330", "arm,primecell";
379 reg = <0x03880000 0x1000>;
380 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clock_audss EXYNOS_ADMA>;
382 clock-names = "apb_pclk";
385 #dma-requests = <16>;
386 power-domains = <&mau_pd>;
389 pdma0: pdma@121A0000 {
390 compatible = "arm,pl330", "arm,primecell";
391 reg = <0x121A0000 0x1000>;
392 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clock CLK_PDMA0>;
394 clock-names = "apb_pclk";
397 #dma-requests = <32>;
400 pdma1: pdma@121B0000 {
401 compatible = "arm,pl330", "arm,primecell";
402 reg = <0x121B0000 0x1000>;
403 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clock CLK_PDMA1>;
405 clock-names = "apb_pclk";
408 #dma-requests = <32>;
411 mdma0: mdma@10800000 {
412 compatible = "arm,pl330", "arm,primecell";
413 reg = <0x10800000 0x1000>;
414 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clock CLK_MDMA0>;
416 clock-names = "apb_pclk";
422 mdma1: mdma@11C10000 {
423 compatible = "arm,pl330", "arm,primecell";
424 reg = <0x11C10000 0x1000>;
425 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clock CLK_MDMA1>;
427 clock-names = "apb_pclk";
432 * MDMA1 can support both secure and non-secure
433 * AXI transactions. When this is enabled in
434 * the kernel for boards that run in secure
435 * mode, we are getting imprecise external
436 * aborts causing the kernel to oops.
443 compatible = "samsung,exynos5420-i2s";
444 reg = <0x03830000 0x100>;
448 dma-names = "tx", "rx", "tx-sec";
449 clocks = <&clock_audss EXYNOS_I2S_BUS>,
450 <&clock_audss EXYNOS_I2S_BUS>,
451 <&clock_audss EXYNOS_SCLK_I2S>;
452 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
454 clock-output-names = "i2s_cdclk0";
455 #sound-dai-cells = <1>;
456 samsung,idma-addr = <0x03000000>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&i2s0_bus>;
459 power-domains = <&mau_pd>;
464 compatible = "samsung,exynos5420-i2s";
465 reg = <0x12D60000 0x100>;
468 dma-names = "tx", "rx";
469 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
470 clock-names = "iis", "i2s_opclk0";
472 clock-output-names = "i2s_cdclk1";
473 #sound-dai-cells = <1>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&i2s1_bus>;
480 compatible = "samsung,exynos5420-i2s";
481 reg = <0x12D70000 0x100>;
484 dma-names = "tx", "rx";
485 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
486 clock-names = "iis", "i2s_opclk0";
488 clock-output-names = "i2s_cdclk2";
489 #sound-dai-cells = <1>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&i2s2_bus>;
495 spi_0: spi@12d20000 {
496 compatible = "samsung,exynos4210-spi";
497 reg = <0x12d20000 0x100>;
498 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
501 dma-names = "tx", "rx";
502 #address-cells = <1>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&spi0_bus>;
506 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
507 clock-names = "spi", "spi_busclk0";
511 spi_1: spi@12d30000 {
512 compatible = "samsung,exynos4210-spi";
513 reg = <0x12d30000 0x100>;
514 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
517 dma-names = "tx", "rx";
518 #address-cells = <1>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&spi1_bus>;
522 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
523 clock-names = "spi", "spi_busclk0";
527 spi_2: spi@12d40000 {
528 compatible = "samsung,exynos4210-spi";
529 reg = <0x12d40000 0x100>;
530 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
533 dma-names = "tx", "rx";
534 #address-cells = <1>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&spi2_bus>;
538 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
539 clock-names = "spi", "spi_busclk0";
543 dp_phy: dp-video-phy {
544 compatible = "samsung,exynos5420-dp-video-phy";
545 samsung,pmu-syscon = <&pmu_system_controller>;
549 mipi_phy: mipi-video-phy {
550 compatible = "samsung,s5pv210-mipi-video-phy";
551 syscon = <&pmu_system_controller>;
556 compatible = "samsung,exynos5410-mipi-dsi";
557 reg = <0x14500000 0x10000>;
558 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
559 phys = <&mipi_phy 1>;
561 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
562 clock-names = "bus_clk", "pll_clk";
563 #address-cells = <1>;
569 compatible = "samsung,exynos-adc-v2";
570 reg = <0x12D10000 0x100>;
571 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clock CLK_TSADC>;
574 #io-channel-cells = <1>;
576 samsung,syscon-phandle = <&pmu_system_controller>;
580 hsi2c_8: i2c@12E00000 {
581 compatible = "samsung,exynos5250-hsi2c";
582 reg = <0x12E00000 0x1000>;
583 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
584 #address-cells = <1>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c8_hs_bus>;
588 clocks = <&clock CLK_USI4>;
589 clock-names = "hsi2c";
593 hsi2c_9: i2c@12E10000 {
594 compatible = "samsung,exynos5250-hsi2c";
595 reg = <0x12E10000 0x1000>;
596 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
597 #address-cells = <1>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c9_hs_bus>;
601 clocks = <&clock CLK_USI5>;
602 clock-names = "hsi2c";
606 hsi2c_10: i2c@12E20000 {
607 compatible = "samsung,exynos5250-hsi2c";
608 reg = <0x12E20000 0x1000>;
609 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
610 #address-cells = <1>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&i2c10_hs_bus>;
614 clocks = <&clock CLK_USI6>;
615 clock-names = "hsi2c";
619 hdmi: hdmi@14530000 {
620 compatible = "samsung,exynos5420-hdmi";
621 reg = <0x14530000 0x70000>;
622 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
624 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
625 <&clock CLK_MOUT_HDMI>;
626 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
627 "sclk_hdmiphy", "mout_hdmi";
629 samsung,syscon-phandle = <&pmu_system_controller>;
631 power-domains = <&disp_pd>;
632 #sound-dai-cells = <0>;
635 hdmiphy: hdmiphy@145D0000 {
636 reg = <0x145D0000 0x20>;
639 hdmicec: cec@101B0000 {
640 compatible = "samsung,s5p-cec";
641 reg = <0x101B0000 0x200>;
642 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&clock CLK_HDMI_CEC>;
644 clock-names = "hdmicec";
645 samsung,syscon-phandle = <&pmu_system_controller>;
646 hdmi-phandle = <&hdmi>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&hdmi_cec>;
652 mixer: mixer@14450000 {
653 compatible = "samsung,exynos5420-mixer";
654 reg = <0x14450000 0x10000>;
655 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
657 <&clock CLK_SCLK_HDMI>;
658 clock-names = "mixer", "hdmi", "sclk_hdmi";
659 power-domains = <&disp_pd>;
660 iommus = <&sysmmu_tv>;
664 rotator: rotator@11C00000 {
665 compatible = "samsung,exynos5250-rotator";
666 reg = <0x11C00000 0x64>;
667 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clock CLK_ROTATOR>;
669 clock-names = "rotator";
670 iommus = <&sysmmu_rotator>;
673 gsc_0: video-scaler@13e00000 {
674 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
675 reg = <0x13e00000 0x1000>;
676 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clock CLK_GSCL0>;
678 clock-names = "gscl";
679 power-domains = <&gsc_pd>;
680 iommus = <&sysmmu_gscl0>;
683 gsc_1: video-scaler@13e10000 {
684 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
685 reg = <0x13e10000 0x1000>;
686 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&clock CLK_GSCL1>;
688 clock-names = "gscl";
689 power-domains = <&gsc_pd>;
690 iommus = <&sysmmu_gscl1>;
693 jpeg_0: jpeg@11F50000 {
694 compatible = "samsung,exynos5420-jpeg";
695 reg = <0x11F50000 0x1000>;
696 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
697 clock-names = "jpeg";
698 clocks = <&clock CLK_JPEG>;
699 iommus = <&sysmmu_jpeg0>;
702 jpeg_1: jpeg@11F60000 {
703 compatible = "samsung,exynos5420-jpeg";
704 reg = <0x11F60000 0x1000>;
705 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
706 clock-names = "jpeg";
707 clocks = <&clock CLK_JPEG2>;
708 iommus = <&sysmmu_jpeg1>;
711 pmu_system_controller: system-controller@10040000 {
712 compatible = "samsung,exynos5420-pmu", "syscon";
713 reg = <0x10040000 0x5000>;
714 clock-names = "clkout16";
715 clocks = <&clock CLK_FIN_PLL>;
717 interrupt-controller;
718 #interrupt-cells = <3>;
719 interrupt-parent = <&gic>;
722 tmu_cpu0: tmu@10060000 {
723 compatible = "samsung,exynos5420-tmu";
724 reg = <0x10060000 0x100>;
725 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clock CLK_TMU>;
727 clock-names = "tmu_apbif";
728 #include "exynos5420-tmu-sensor-conf.dtsi"
731 tmu_cpu1: tmu@10064000 {
732 compatible = "samsung,exynos5420-tmu";
733 reg = <0x10064000 0x100>;
734 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clock CLK_TMU>;
736 clock-names = "tmu_apbif";
737 #include "exynos5420-tmu-sensor-conf.dtsi"
740 tmu_cpu2: tmu@10068000 {
741 compatible = "samsung,exynos5420-tmu-ext-triminfo";
742 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
743 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
745 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
746 #include "exynos5420-tmu-sensor-conf.dtsi"
749 tmu_cpu3: tmu@1006c000 {
750 compatible = "samsung,exynos5420-tmu-ext-triminfo";
751 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
752 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
754 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
755 #include "exynos5420-tmu-sensor-conf.dtsi"
758 tmu_gpu: tmu@100a0000 {
759 compatible = "samsung,exynos5420-tmu-ext-triminfo";
760 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
761 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
763 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
764 #include "exynos5420-tmu-sensor-conf.dtsi"
767 sysmmu_g2dr: sysmmu@0x10A60000 {
768 compatible = "samsung,exynos-sysmmu";
769 reg = <0x10A60000 0x1000>;
770 interrupt-parent = <&combiner>;
772 clock-names = "sysmmu", "master";
773 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
777 sysmmu_g2dw: sysmmu@0x10A70000 {
778 compatible = "samsung,exynos-sysmmu";
779 reg = <0x10A70000 0x1000>;
780 interrupt-parent = <&combiner>;
782 clock-names = "sysmmu", "master";
783 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
787 sysmmu_tv: sysmmu@0x14650000 {
788 compatible = "samsung,exynos-sysmmu";
789 reg = <0x14650000 0x1000>;
790 interrupt-parent = <&combiner>;
792 clock-names = "sysmmu", "master";
793 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
794 power-domains = <&disp_pd>;
798 sysmmu_gscl0: sysmmu@0x13E80000 {
799 compatible = "samsung,exynos-sysmmu";
800 reg = <0x13E80000 0x1000>;
801 interrupt-parent = <&combiner>;
803 clock-names = "sysmmu", "master";
804 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
805 power-domains = <&gsc_pd>;
809 sysmmu_gscl1: sysmmu@0x13E90000 {
810 compatible = "samsung,exynos-sysmmu";
811 reg = <0x13E90000 0x1000>;
812 interrupt-parent = <&combiner>;
814 clock-names = "sysmmu", "master";
815 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
816 power-domains = <&gsc_pd>;
820 sysmmu_scaler0r: sysmmu@0x12880000 {
821 compatible = "samsung,exynos-sysmmu";
822 reg = <0x12880000 0x1000>;
823 interrupt-parent = <&combiner>;
825 clock-names = "sysmmu", "master";
826 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
830 sysmmu_scaler1r: sysmmu@0x12890000 {
831 compatible = "samsung,exynos-sysmmu";
832 reg = <0x12890000 0x1000>;
833 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
834 clock-names = "sysmmu", "master";
835 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
839 sysmmu_scaler2r: sysmmu@0x128A0000 {
840 compatible = "samsung,exynos-sysmmu";
841 reg = <0x128A0000 0x1000>;
842 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
843 clock-names = "sysmmu", "master";
844 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
848 sysmmu_scaler0w: sysmmu@0x128C0000 {
849 compatible = "samsung,exynos-sysmmu";
850 reg = <0x128C0000 0x1000>;
851 interrupt-parent = <&combiner>;
853 clock-names = "sysmmu", "master";
854 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
858 sysmmu_scaler1w: sysmmu@0x128D0000 {
859 compatible = "samsung,exynos-sysmmu";
860 reg = <0x128D0000 0x1000>;
861 interrupt-parent = <&combiner>;
863 clock-names = "sysmmu", "master";
864 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
868 sysmmu_scaler2w: sysmmu@0x128E0000 {
869 compatible = "samsung,exynos-sysmmu";
870 reg = <0x128E0000 0x1000>;
871 interrupt-parent = <&combiner>;
873 clock-names = "sysmmu", "master";
874 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
878 sysmmu_rotator: sysmmu@0x11D40000 {
879 compatible = "samsung,exynos-sysmmu";
880 reg = <0x11D40000 0x1000>;
881 interrupt-parent = <&combiner>;
883 clock-names = "sysmmu", "master";
884 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
888 sysmmu_jpeg0: sysmmu@0x11F10000 {
889 compatible = "samsung,exynos-sysmmu";
890 reg = <0x11F10000 0x1000>;
891 interrupt-parent = <&combiner>;
893 clock-names = "sysmmu", "master";
894 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
898 sysmmu_jpeg1: sysmmu@0x11F20000 {
899 compatible = "samsung,exynos-sysmmu";
900 reg = <0x11F20000 0x1000>;
901 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
902 clock-names = "sysmmu", "master";
903 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
907 sysmmu_mfc_l: sysmmu@0x11200000 {
908 compatible = "samsung,exynos-sysmmu";
909 reg = <0x11200000 0x1000>;
910 interrupt-parent = <&combiner>;
912 clock-names = "sysmmu", "master";
913 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
914 power-domains = <&mfc_pd>;
918 sysmmu_mfc_r: sysmmu@0x11210000 {
919 compatible = "samsung,exynos-sysmmu";
920 reg = <0x11210000 0x1000>;
921 interrupt-parent = <&combiner>;
923 clock-names = "sysmmu", "master";
924 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
925 power-domains = <&mfc_pd>;
929 sysmmu_fimd1_0: sysmmu@0x14640000 {
930 compatible = "samsung,exynos-sysmmu";
931 reg = <0x14640000 0x1000>;
932 interrupt-parent = <&combiner>;
934 clock-names = "sysmmu", "master";
935 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
936 power-domains = <&disp_pd>;
940 sysmmu_fimd1_1: sysmmu@0x14680000 {
941 compatible = "samsung,exynos-sysmmu";
942 reg = <0x14680000 0x1000>;
943 interrupt-parent = <&combiner>;
945 clock-names = "sysmmu", "master";
946 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
947 power-domains = <&disp_pd>;
951 bus_wcore: bus_wcore {
952 compatible = "samsung,exynos-bus";
953 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
955 operating-points-v2 = <&bus_wcore_opp_table>;
960 compatible = "samsung,exynos-bus";
961 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
963 operating-points-v2 = <&bus_noc_opp_table>;
967 bus_fsys_apb: bus_fsys_apb {
968 compatible = "samsung,exynos-bus";
969 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
971 operating-points-v2 = <&bus_fsys_apb_opp_table>;
976 compatible = "samsung,exynos-bus";
977 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
979 operating-points-v2 = <&bus_fsys_apb_opp_table>;
983 bus_fsys2: bus_fsys2 {
984 compatible = "samsung,exynos-bus";
985 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
987 operating-points-v2 = <&bus_fsys2_opp_table>;
992 compatible = "samsung,exynos-bus";
993 clocks = <&clock CLK_DOUT_ACLK333>;
995 operating-points-v2 = <&bus_mfc_opp_table>;
1000 compatible = "samsung,exynos-bus";
1001 clocks = <&clock CLK_DOUT_ACLK266>;
1002 clock-names = "bus";
1003 operating-points-v2 = <&bus_gen_opp_table>;
1004 status = "disabled";
1007 bus_peri: bus_peri {
1008 compatible = "samsung,exynos-bus";
1009 clocks = <&clock CLK_DOUT_ACLK66>;
1010 clock-names = "bus";
1011 operating-points-v2 = <&bus_peri_opp_table>;
1012 status = "disabled";
1016 compatible = "samsung,exynos-bus";
1017 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1018 clock-names = "bus";
1019 operating-points-v2 = <&bus_g2d_opp_table>;
1020 status = "disabled";
1023 bus_g2d_acp: bus_g2d_acp {
1024 compatible = "samsung,exynos-bus";
1025 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1026 clock-names = "bus";
1027 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1028 status = "disabled";
1031 bus_jpeg: bus_jpeg {
1032 compatible = "samsung,exynos-bus";
1033 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1034 clock-names = "bus";
1035 operating-points-v2 = <&bus_jpeg_opp_table>;
1036 status = "disabled";
1039 bus_jpeg_apb: bus_jpeg_apb {
1040 compatible = "samsung,exynos-bus";
1041 clocks = <&clock CLK_DOUT_ACLK166>;
1042 clock-names = "bus";
1043 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1044 status = "disabled";
1047 bus_disp1_fimd: bus_disp1_fimd {
1048 compatible = "samsung,exynos-bus";
1049 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1050 clock-names = "bus";
1051 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1052 status = "disabled";
1055 bus_disp1: bus_disp1 {
1056 compatible = "samsung,exynos-bus";
1057 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1058 clock-names = "bus";
1059 operating-points-v2 = <&bus_disp1_opp_table>;
1060 status = "disabled";
1063 bus_gscl_scaler: bus_gscl_scaler {
1064 compatible = "samsung,exynos-bus";
1065 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1066 clock-names = "bus";
1067 operating-points-v2 = <&bus_gscl_opp_table>;
1068 status = "disabled";
1071 bus_mscl: bus_mscl {
1072 compatible = "samsung,exynos-bus";
1073 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1074 clock-names = "bus";
1075 operating-points-v2 = <&bus_mscl_opp_table>;
1076 status = "disabled";
1079 bus_wcore_opp_table: opp_table2 {
1080 compatible = "operating-points-v2";
1083 opp-hz = /bits/ 64 <84000000>;
1084 opp-microvolt = <925000>;
1087 opp-hz = /bits/ 64 <111000000>;
1088 opp-microvolt = <950000>;
1091 opp-hz = /bits/ 64 <222000000>;
1092 opp-microvolt = <950000>;
1095 opp-hz = /bits/ 64 <333000000>;
1096 opp-microvolt = <950000>;
1099 opp-hz = /bits/ 64 <400000000>;
1100 opp-microvolt = <987500>;
1104 bus_noc_opp_table: opp_table3 {
1105 compatible = "operating-points-v2";
1108 opp-hz = /bits/ 64 <67000000>;
1111 opp-hz = /bits/ 64 <75000000>;
1114 opp-hz = /bits/ 64 <86000000>;
1117 opp-hz = /bits/ 64 <100000000>;
1121 bus_fsys_apb_opp_table: opp_table4 {
1122 compatible = "operating-points-v2";
1126 opp-hz = /bits/ 64 <100000000>;
1129 opp-hz = /bits/ 64 <200000000>;
1133 bus_fsys2_opp_table: opp_table5 {
1134 compatible = "operating-points-v2";
1137 opp-hz = /bits/ 64 <75000000>;
1140 opp-hz = /bits/ 64 <100000000>;
1143 opp-hz = /bits/ 64 <150000000>;
1147 bus_mfc_opp_table: opp_table6 {
1148 compatible = "operating-points-v2";
1151 opp-hz = /bits/ 64 <96000000>;
1154 opp-hz = /bits/ 64 <111000000>;
1157 opp-hz = /bits/ 64 <167000000>;
1160 opp-hz = /bits/ 64 <222000000>;
1163 opp-hz = /bits/ 64 <333000000>;
1167 bus_gen_opp_table: opp_table7 {
1168 compatible = "operating-points-v2";
1171 opp-hz = /bits/ 64 <89000000>;
1174 opp-hz = /bits/ 64 <133000000>;
1177 opp-hz = /bits/ 64 <178000000>;
1180 opp-hz = /bits/ 64 <267000000>;
1184 bus_peri_opp_table: opp_table8 {
1185 compatible = "operating-points-v2";
1188 opp-hz = /bits/ 64 <67000000>;
1192 bus_g2d_opp_table: opp_table9 {
1193 compatible = "operating-points-v2";
1196 opp-hz = /bits/ 64 <84000000>;
1199 opp-hz = /bits/ 64 <167000000>;
1202 opp-hz = /bits/ 64 <222000000>;
1205 opp-hz = /bits/ 64 <300000000>;
1208 opp-hz = /bits/ 64 <333000000>;
1212 bus_g2d_acp_opp_table: opp_table10 {
1213 compatible = "operating-points-v2";
1216 opp-hz = /bits/ 64 <67000000>;
1219 opp-hz = /bits/ 64 <133000000>;
1222 opp-hz = /bits/ 64 <178000000>;
1225 opp-hz = /bits/ 64 <267000000>;
1229 bus_jpeg_opp_table: opp_table11 {
1230 compatible = "operating-points-v2";
1233 opp-hz = /bits/ 64 <75000000>;
1236 opp-hz = /bits/ 64 <150000000>;
1239 opp-hz = /bits/ 64 <200000000>;
1242 opp-hz = /bits/ 64 <300000000>;
1246 bus_jpeg_apb_opp_table: opp_table12 {
1247 compatible = "operating-points-v2";
1250 opp-hz = /bits/ 64 <84000000>;
1253 opp-hz = /bits/ 64 <111000000>;
1256 opp-hz = /bits/ 64 <134000000>;
1259 opp-hz = /bits/ 64 <167000000>;
1263 bus_disp1_fimd_opp_table: opp_table13 {
1264 compatible = "operating-points-v2";
1267 opp-hz = /bits/ 64 <120000000>;
1270 opp-hz = /bits/ 64 <200000000>;
1274 bus_disp1_opp_table: opp_table14 {
1275 compatible = "operating-points-v2";
1278 opp-hz = /bits/ 64 <120000000>;
1281 opp-hz = /bits/ 64 <200000000>;
1284 opp-hz = /bits/ 64 <300000000>;
1288 bus_gscl_opp_table: opp_table15 {
1289 compatible = "operating-points-v2";
1292 opp-hz = /bits/ 64 <150000000>;
1295 opp-hz = /bits/ 64 <200000000>;
1298 opp-hz = /bits/ 64 <300000000>;
1302 bus_mscl_opp_table: opp_table16 {
1303 compatible = "operating-points-v2";
1306 opp-hz = /bits/ 64 <84000000>;
1309 opp-hz = /bits/ 64 <167000000>;
1312 opp-hz = /bits/ 64 <222000000>;
1315 opp-hz = /bits/ 64 <333000000>;
1318 opp-hz = /bits/ 64 <400000000>;
1324 cpu0_thermal: cpu0-thermal {
1325 thermal-sensors = <&tmu_cpu0>;
1326 #include "exynos5420-trip-points.dtsi"
1328 cpu1_thermal: cpu1-thermal {
1329 thermal-sensors = <&tmu_cpu1>;
1330 #include "exynos5420-trip-points.dtsi"
1332 cpu2_thermal: cpu2-thermal {
1333 thermal-sensors = <&tmu_cpu2>;
1334 #include "exynos5420-trip-points.dtsi"
1336 cpu3_thermal: cpu3-thermal {
1337 thermal-sensors = <&tmu_cpu3>;
1338 #include "exynos5420-trip-points.dtsi"
1340 gpu_thermal: gpu-thermal {
1341 thermal-sensors = <&tmu_gpu>;
1342 #include "exynos5420-trip-points.dtsi"
1348 clocks = <&clock CLK_DP1>;
1352 power-domains = <&disp_pd>;
1356 compatible = "samsung,exynos5420-fimd";
1357 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1358 clock-names = "sclk_fimd", "fimd";
1359 power-domains = <&disp_pd>;
1360 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1361 iommu-names = "m0", "m1";
1365 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1366 clocks = <&clock CLK_G2D>;
1367 clock-names = "fimg2d";
1372 clocks = <&clock CLK_I2C0>;
1373 clock-names = "i2c";
1374 pinctrl-names = "default";
1375 pinctrl-0 = <&i2c0_bus>;
1379 clocks = <&clock CLK_I2C1>;
1380 clock-names = "i2c";
1381 pinctrl-names = "default";
1382 pinctrl-0 = <&i2c1_bus>;
1386 clocks = <&clock CLK_I2C2>;
1387 clock-names = "i2c";
1388 pinctrl-names = "default";
1389 pinctrl-0 = <&i2c2_bus>;
1393 clocks = <&clock CLK_I2C3>;
1394 clock-names = "i2c";
1395 pinctrl-names = "default";
1396 pinctrl-0 = <&i2c3_bus>;
1400 clocks = <&clock CLK_USI0>;
1401 clock-names = "hsi2c";
1402 pinctrl-names = "default";
1403 pinctrl-0 = <&i2c4_hs_bus>;
1407 clocks = <&clock CLK_USI1>;
1408 clock-names = "hsi2c";
1409 pinctrl-names = "default";
1410 pinctrl-0 = <&i2c5_hs_bus>;
1414 clocks = <&clock CLK_USI2>;
1415 clock-names = "hsi2c";
1416 pinctrl-names = "default";
1417 pinctrl-0 = <&i2c6_hs_bus>;
1421 clocks = <&clock CLK_USI3>;
1422 clock-names = "hsi2c";
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&i2c7_hs_bus>;
1428 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1429 clock-names = "fin_pll", "mct";
1433 clocks = <&clock CLK_PWM>;
1434 clock-names = "timers";
1438 clocks = <&clock CLK_RTC>;
1439 clock-names = "rtc";
1440 interrupt-parent = <&pmu_system_controller>;
1441 status = "disabled";
1445 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1446 clock-names = "uart", "clk_uart_baud0";
1447 dmas = <&pdma0 13>, <&pdma0 14>;
1448 dma-names = "rx", "tx";
1452 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1453 clock-names = "uart", "clk_uart_baud0";
1454 dmas = <&pdma1 15>, <&pdma1 16>;
1455 dma-names = "rx", "tx";
1459 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1460 clock-names = "uart", "clk_uart_baud0";
1461 dmas = <&pdma0 15>, <&pdma0 16>;
1462 dma-names = "rx", "tx";
1466 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1467 clock-names = "uart", "clk_uart_baud0";
1468 dmas = <&pdma1 17>, <&pdma1 18>;
1469 dma-names = "rx", "tx";
1473 clocks = <&clock CLK_SSS>;
1474 clock-names = "secss";
1478 clocks = <&clock CLK_USBD300>;
1479 clock-names = "usbdrd30";
1483 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1484 clock-names = "phy", "ref";
1485 samsung,pmu-syscon = <&pmu_system_controller>;
1489 clocks = <&clock CLK_USBD301>;
1490 clock-names = "usbdrd30";
1494 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1499 clock-names = "phy", "ref";
1500 samsung,pmu-syscon = <&pmu_system_controller>;
1504 clocks = <&clock CLK_USBH20>;
1505 clock-names = "usbhost";
1509 clocks = <&clock CLK_USBH20>;
1510 clock-names = "usbhost";
1514 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1515 clock-names = "phy", "ref";
1516 samsung,sysreg-phandle = <&sysreg_system_controller>;
1517 samsung,pmureg-phandle = <&pmu_system_controller>;
1521 clocks = <&clock CLK_WDT>;
1522 clock-names = "watchdog";
1523 samsung,syscon-phandle = <&pmu_system_controller>;
1526 #include "exynos5420-pinctrl.dtsi"