1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5420 SoC device tree source
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
9 * EXYNOS5420 based board files can include this file and provide
10 * values for board specfic bindings.
13 #include "exynos54xx.dtsi"
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "samsung,exynos5420", "samsung,exynos5";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
41 * The 'cpus' node is not present here but instead it is provided
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
46 cluster_a15_opp_table: opp_table0 {
47 compatible = "operating-points-v2";
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000>;
52 clock-latency-ns = <140000>;
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500>;
57 clock-latency-ns = <140000>;
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000>;
62 clock-latency-ns = <140000>;
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500>;
67 clock-latency-ns = <140000>;
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500>;
72 clock-latency-ns = <140000>;
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500>;
77 clock-latency-ns = <140000>;
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500>;
82 clock-latency-ns = <140000>;
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500>;
87 clock-latency-ns = <140000>;
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500>;
92 clock-latency-ns = <140000>;
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500>;
97 clock-latency-ns = <140000>;
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500>;
102 clock-latency-ns = <140000>;
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500>;
107 clock-latency-ns = <140000>;
111 cluster_a7_opp_table: opp_table1 {
112 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <1300000000>;
116 opp-microvolt = <1275000>;
117 clock-latency-ns = <140000>;
120 opp-hz = /bits/ 64 <1200000000>;
121 opp-microvolt = <1212500>;
122 clock-latency-ns = <140000>;
125 opp-hz = /bits/ 64 <1100000000>;
126 opp-microvolt = <1162500>;
127 clock-latency-ns = <140000>;
130 opp-hz = /bits/ 64 <1000000000>;
131 opp-microvolt = <1112500>;
132 clock-latency-ns = <140000>;
135 opp-hz = /bits/ 64 <900000000>;
136 opp-microvolt = <1062500>;
137 clock-latency-ns = <140000>;
140 opp-hz = /bits/ 64 <800000000>;
141 opp-microvolt = <1025000>;
142 clock-latency-ns = <140000>;
145 opp-hz = /bits/ 64 <700000000>;
146 opp-microvolt = <975000>;
147 clock-latency-ns = <140000>;
150 opp-hz = /bits/ 64 <600000000>;
151 opp-microvolt = <937500>;
152 clock-latency-ns = <140000>;
157 compatible = "arm,cci-400";
158 #address-cells = <1>;
160 reg = <0x10d20000 0x1000>;
161 ranges = <0x0 0x10d20000 0x6000>;
163 cci_control0: slave-if@4000 {
164 compatible = "arm,cci-400-ctrl-if";
165 interface-type = "ace";
166 reg = <0x4000 0x1000>;
168 cci_control1: slave-if@5000 {
169 compatible = "arm,cci-400-ctrl-if";
170 interface-type = "ace";
171 reg = <0x5000 0x1000>;
175 clock: clock-controller@10010000 {
176 compatible = "samsung,exynos5420-clock";
177 reg = <0x10010000 0x30000>;
181 clock_audss: audss-clock-controller@3810000 {
182 compatible = "samsung,exynos5420-audss-clock";
183 reg = <0x03810000 0x0C>;
185 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
186 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
187 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
188 power-domains = <&mau_pd>;
191 mfc: codec@11000000 {
192 compatible = "samsung,mfc-v7";
193 reg = <0x11000000 0x10000>;
194 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clock CLK_MFC>;
197 power-domains = <&mfc_pd>;
198 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
199 iommu-names = "left", "right";
202 mmc_0: mmc@12200000 {
203 compatible = "samsung,exynos5420-dw-mshc-smu";
204 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
207 reg = <0x12200000 0x2000>;
208 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
209 clock-names = "biu", "ciu";
214 mmc_1: mmc@12210000 {
215 compatible = "samsung,exynos5420-dw-mshc-smu";
216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
217 #address-cells = <1>;
219 reg = <0x12210000 0x2000>;
220 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
221 clock-names = "biu", "ciu";
226 mmc_2: mmc@12220000 {
227 compatible = "samsung,exynos5420-dw-mshc";
228 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
229 #address-cells = <1>;
231 reg = <0x12220000 0x1000>;
232 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
233 clock-names = "biu", "ciu";
238 nocp_mem0_0: nocp@10ca1000 {
239 compatible = "samsung,exynos5420-nocp";
240 reg = <0x10CA1000 0x200>;
244 nocp_mem0_1: nocp@10ca1400 {
245 compatible = "samsung,exynos5420-nocp";
246 reg = <0x10CA1400 0x200>;
250 nocp_mem1_0: nocp@10ca1800 {
251 compatible = "samsung,exynos5420-nocp";
252 reg = <0x10CA1800 0x200>;
256 nocp_mem1_1: nocp@10ca1c00 {
257 compatible = "samsung,exynos5420-nocp";
258 reg = <0x10CA1C00 0x200>;
262 nocp_g3d_0: nocp@11a51000 {
263 compatible = "samsung,exynos5420-nocp";
264 reg = <0x11A51000 0x200>;
268 nocp_g3d_1: nocp@11a51400 {
269 compatible = "samsung,exynos5420-nocp";
270 reg = <0x11A51400 0x200>;
274 gsc_pd: power-domain@10044000 {
275 compatible = "samsung,exynos4210-pd";
276 reg = <0x10044000 0x20>;
277 #power-domain-cells = <0>;
281 isp_pd: power-domain@10044020 {
282 compatible = "samsung,exynos4210-pd";
283 reg = <0x10044020 0x20>;
284 #power-domain-cells = <0>;
288 mfc_pd: power-domain@10044060 {
289 compatible = "samsung,exynos4210-pd";
290 reg = <0x10044060 0x20>;
291 #power-domain-cells = <0>;
295 msc_pd: power-domain@10044120 {
296 compatible = "samsung,exynos4210-pd";
297 reg = <0x10044120 0x20>;
298 #power-domain-cells = <0>;
302 disp_pd: power-domain@100440c0 {
303 compatible = "samsung,exynos4210-pd";
304 reg = <0x100440C0 0x20>;
305 #power-domain-cells = <0>;
309 mau_pd: power-domain@100440e0 {
310 compatible = "samsung,exynos4210-pd";
311 reg = <0x100440E0 0x20>;
312 #power-domain-cells = <0>;
316 pinctrl_0: pinctrl@13400000 {
317 compatible = "samsung,exynos5420-pinctrl";
318 reg = <0x13400000 0x1000>;
319 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
321 wakeup-interrupt-controller {
322 compatible = "samsung,exynos4210-wakeup-eint";
323 interrupt-parent = <&gic>;
324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
328 pinctrl_1: pinctrl@13410000 {
329 compatible = "samsung,exynos5420-pinctrl";
330 reg = <0x13410000 0x1000>;
331 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
334 pinctrl_2: pinctrl@14000000 {
335 compatible = "samsung,exynos5420-pinctrl";
336 reg = <0x14000000 0x1000>;
337 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
340 pinctrl_3: pinctrl@14010000 {
341 compatible = "samsung,exynos5420-pinctrl";
342 reg = <0x14010000 0x1000>;
343 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
346 pinctrl_4: pinctrl@3860000 {
347 compatible = "samsung,exynos5420-pinctrl";
348 reg = <0x03860000 0x1000>;
349 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
350 power-domains = <&mau_pd>;
354 #address-cells = <1>;
356 compatible = "simple-bus";
357 interrupt-parent = <&gic>;
361 compatible = "arm,pl330", "arm,primecell";
362 reg = <0x03880000 0x1000>;
363 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clock_audss EXYNOS_ADMA>;
365 clock-names = "apb_pclk";
368 #dma-requests = <16>;
369 power-domains = <&mau_pd>;
372 pdma0: pdma@121a0000 {
373 compatible = "arm,pl330", "arm,primecell";
374 reg = <0x121A0000 0x1000>;
375 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clock CLK_PDMA0>;
377 clock-names = "apb_pclk";
380 #dma-requests = <32>;
383 pdma1: pdma@121b0000 {
384 compatible = "arm,pl330", "arm,primecell";
385 reg = <0x121B0000 0x1000>;
386 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clock CLK_PDMA1>;
388 clock-names = "apb_pclk";
391 #dma-requests = <32>;
394 mdma0: mdma@10800000 {
395 compatible = "arm,pl330", "arm,primecell";
396 reg = <0x10800000 0x1000>;
397 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clock CLK_MDMA0>;
399 clock-names = "apb_pclk";
405 mdma1: mdma@11c10000 {
406 compatible = "arm,pl330", "arm,primecell";
407 reg = <0x11C10000 0x1000>;
408 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clock CLK_MDMA1>;
410 clock-names = "apb_pclk";
415 * MDMA1 can support both secure and non-secure
416 * AXI transactions. When this is enabled in
417 * the kernel for boards that run in secure
418 * mode, we are getting imprecise external
419 * aborts causing the kernel to oops.
426 compatible = "samsung,exynos5420-i2s";
427 reg = <0x03830000 0x100>;
431 dma-names = "tx", "rx", "tx-sec";
432 clocks = <&clock_audss EXYNOS_I2S_BUS>,
433 <&clock_audss EXYNOS_I2S_BUS>,
434 <&clock_audss EXYNOS_SCLK_I2S>;
435 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
437 clock-output-names = "i2s_cdclk0";
438 #sound-dai-cells = <1>;
439 samsung,idma-addr = <0x03000000>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2s0_bus>;
442 power-domains = <&mau_pd>;
447 compatible = "samsung,exynos5420-i2s";
448 reg = <0x12D60000 0x100>;
451 dma-names = "tx", "rx";
452 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
453 clock-names = "iis", "i2s_opclk0";
455 clock-output-names = "i2s_cdclk1";
456 #sound-dai-cells = <1>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&i2s1_bus>;
463 compatible = "samsung,exynos5420-i2s";
464 reg = <0x12D70000 0x100>;
467 dma-names = "tx", "rx";
468 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
469 clock-names = "iis", "i2s_opclk0";
471 clock-output-names = "i2s_cdclk2";
472 #sound-dai-cells = <1>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2s2_bus>;
478 spi_0: spi@12d20000 {
479 compatible = "samsung,exynos4210-spi";
480 reg = <0x12d20000 0x100>;
481 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
484 dma-names = "tx", "rx";
485 #address-cells = <1>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&spi0_bus>;
489 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
490 clock-names = "spi", "spi_busclk0";
494 spi_1: spi@12d30000 {
495 compatible = "samsung,exynos4210-spi";
496 reg = <0x12d30000 0x100>;
497 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
500 dma-names = "tx", "rx";
501 #address-cells = <1>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&spi1_bus>;
505 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
506 clock-names = "spi", "spi_busclk0";
510 spi_2: spi@12d40000 {
511 compatible = "samsung,exynos4210-spi";
512 reg = <0x12d40000 0x100>;
513 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
516 dma-names = "tx", "rx";
517 #address-cells = <1>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&spi2_bus>;
521 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
522 clock-names = "spi", "spi_busclk0";
526 dp_phy: dp-video-phy {
527 compatible = "samsung,exynos5420-dp-video-phy";
528 samsung,pmu-syscon = <&pmu_system_controller>;
532 mipi_phy: mipi-video-phy {
533 compatible = "samsung,s5pv210-mipi-video-phy";
534 syscon = <&pmu_system_controller>;
539 compatible = "samsung,exynos5410-mipi-dsi";
540 reg = <0x14500000 0x10000>;
541 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
542 phys = <&mipi_phy 1>;
544 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
545 clock-names = "bus_clk", "pll_clk";
546 #address-cells = <1>;
552 compatible = "samsung,exynos-adc-v2";
553 reg = <0x12D10000 0x100>;
554 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&clock CLK_TSADC>;
557 #io-channel-cells = <1>;
559 samsung,syscon-phandle = <&pmu_system_controller>;
563 hsi2c_8: i2c@12e00000 {
564 compatible = "samsung,exynos5250-hsi2c";
565 reg = <0x12E00000 0x1000>;
566 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
567 #address-cells = <1>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c8_hs_bus>;
571 clocks = <&clock CLK_USI4>;
572 clock-names = "hsi2c";
576 hsi2c_9: i2c@12e10000 {
577 compatible = "samsung,exynos5250-hsi2c";
578 reg = <0x12E10000 0x1000>;
579 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2c9_hs_bus>;
584 clocks = <&clock CLK_USI5>;
585 clock-names = "hsi2c";
589 hsi2c_10: i2c@12e20000 {
590 compatible = "samsung,exynos5250-hsi2c";
591 reg = <0x12E20000 0x1000>;
592 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
593 #address-cells = <1>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c10_hs_bus>;
597 clocks = <&clock CLK_USI6>;
598 clock-names = "hsi2c";
602 hdmi: hdmi@14530000 {
603 compatible = "samsung,exynos5420-hdmi";
604 reg = <0x14530000 0x70000>;
605 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
607 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
608 <&clock CLK_MOUT_HDMI>;
609 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
610 "sclk_hdmiphy", "mout_hdmi";
612 samsung,syscon-phandle = <&pmu_system_controller>;
614 power-domains = <&disp_pd>;
615 #sound-dai-cells = <0>;
618 hdmiphy: hdmiphy@145d0000 {
619 reg = <0x145D0000 0x20>;
622 hdmicec: cec@101b0000 {
623 compatible = "samsung,s5p-cec";
624 reg = <0x101B0000 0x200>;
625 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&clock CLK_HDMI_CEC>;
627 clock-names = "hdmicec";
628 samsung,syscon-phandle = <&pmu_system_controller>;
629 hdmi-phandle = <&hdmi>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&hdmi_cec>;
635 mixer: mixer@14450000 {
636 compatible = "samsung,exynos5420-mixer";
637 reg = <0x14450000 0x10000>;
638 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
640 <&clock CLK_SCLK_HDMI>;
641 clock-names = "mixer", "hdmi", "sclk_hdmi";
642 power-domains = <&disp_pd>;
643 iommus = <&sysmmu_tv>;
647 rotator: rotator@11c00000 {
648 compatible = "samsung,exynos5250-rotator";
649 reg = <0x11C00000 0x64>;
650 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&clock CLK_ROTATOR>;
652 clock-names = "rotator";
653 iommus = <&sysmmu_rotator>;
656 gsc_0: video-scaler@13e00000 {
657 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
658 reg = <0x13e00000 0x1000>;
659 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&clock CLK_GSCL0>;
661 clock-names = "gscl";
662 power-domains = <&gsc_pd>;
663 iommus = <&sysmmu_gscl0>;
666 gsc_1: video-scaler@13e10000 {
667 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
668 reg = <0x13e10000 0x1000>;
669 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clock CLK_GSCL1>;
671 clock-names = "gscl";
672 power-domains = <&gsc_pd>;
673 iommus = <&sysmmu_gscl1>;
676 jpeg_0: jpeg@11f50000 {
677 compatible = "samsung,exynos5420-jpeg";
678 reg = <0x11F50000 0x1000>;
679 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
680 clock-names = "jpeg";
681 clocks = <&clock CLK_JPEG>;
682 iommus = <&sysmmu_jpeg0>;
685 jpeg_1: jpeg@11f60000 {
686 compatible = "samsung,exynos5420-jpeg";
687 reg = <0x11F60000 0x1000>;
688 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
689 clock-names = "jpeg";
690 clocks = <&clock CLK_JPEG2>;
691 iommus = <&sysmmu_jpeg1>;
694 pmu_system_controller: system-controller@10040000 {
695 compatible = "samsung,exynos5420-pmu", "syscon";
696 reg = <0x10040000 0x5000>;
697 clock-names = "clkout16";
698 clocks = <&clock CLK_FIN_PLL>;
700 interrupt-controller;
701 #interrupt-cells = <3>;
702 interrupt-parent = <&gic>;
705 tmu_cpu0: tmu@10060000 {
706 compatible = "samsung,exynos5420-tmu";
707 reg = <0x10060000 0x100>;
708 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&clock CLK_TMU>;
710 clock-names = "tmu_apbif";
711 #include "exynos5420-tmu-sensor-conf.dtsi"
714 tmu_cpu1: tmu@10064000 {
715 compatible = "samsung,exynos5420-tmu";
716 reg = <0x10064000 0x100>;
717 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clock CLK_TMU>;
719 clock-names = "tmu_apbif";
720 #include "exynos5420-tmu-sensor-conf.dtsi"
723 tmu_cpu2: tmu@10068000 {
724 compatible = "samsung,exynos5420-tmu-ext-triminfo";
725 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
726 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
728 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
729 #include "exynos5420-tmu-sensor-conf.dtsi"
732 tmu_cpu3: tmu@1006c000 {
733 compatible = "samsung,exynos5420-tmu-ext-triminfo";
734 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
735 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
737 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
738 #include "exynos5420-tmu-sensor-conf.dtsi"
741 tmu_gpu: tmu@100a0000 {
742 compatible = "samsung,exynos5420-tmu-ext-triminfo";
743 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
744 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
746 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
747 #include "exynos5420-tmu-sensor-conf.dtsi"
750 sysmmu_g2dr: sysmmu@0x10A60000 {
751 compatible = "samsung,exynos-sysmmu";
752 reg = <0x10A60000 0x1000>;
753 interrupt-parent = <&combiner>;
755 clock-names = "sysmmu", "master";
756 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
760 sysmmu_g2dw: sysmmu@0x10A70000 {
761 compatible = "samsung,exynos-sysmmu";
762 reg = <0x10A70000 0x1000>;
763 interrupt-parent = <&combiner>;
765 clock-names = "sysmmu", "master";
766 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
770 sysmmu_tv: sysmmu@0x14650000 {
771 compatible = "samsung,exynos-sysmmu";
772 reg = <0x14650000 0x1000>;
773 interrupt-parent = <&combiner>;
775 clock-names = "sysmmu", "master";
776 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
777 power-domains = <&disp_pd>;
781 sysmmu_gscl0: sysmmu@0x13E80000 {
782 compatible = "samsung,exynos-sysmmu";
783 reg = <0x13E80000 0x1000>;
784 interrupt-parent = <&combiner>;
786 clock-names = "sysmmu", "master";
787 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
788 power-domains = <&gsc_pd>;
792 sysmmu_gscl1: sysmmu@0x13E90000 {
793 compatible = "samsung,exynos-sysmmu";
794 reg = <0x13E90000 0x1000>;
795 interrupt-parent = <&combiner>;
797 clock-names = "sysmmu", "master";
798 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
799 power-domains = <&gsc_pd>;
803 sysmmu_scaler0r: sysmmu@0x12880000 {
804 compatible = "samsung,exynos-sysmmu";
805 reg = <0x12880000 0x1000>;
806 interrupt-parent = <&combiner>;
808 clock-names = "sysmmu", "master";
809 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
813 sysmmu_scaler1r: sysmmu@0x12890000 {
814 compatible = "samsung,exynos-sysmmu";
815 reg = <0x12890000 0x1000>;
816 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
817 clock-names = "sysmmu", "master";
818 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
822 sysmmu_scaler2r: sysmmu@0x128A0000 {
823 compatible = "samsung,exynos-sysmmu";
824 reg = <0x128A0000 0x1000>;
825 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
826 clock-names = "sysmmu", "master";
827 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
831 sysmmu_scaler0w: sysmmu@0x128C0000 {
832 compatible = "samsung,exynos-sysmmu";
833 reg = <0x128C0000 0x1000>;
834 interrupt-parent = <&combiner>;
836 clock-names = "sysmmu", "master";
837 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
841 sysmmu_scaler1w: sysmmu@0x128D0000 {
842 compatible = "samsung,exynos-sysmmu";
843 reg = <0x128D0000 0x1000>;
844 interrupt-parent = <&combiner>;
846 clock-names = "sysmmu", "master";
847 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
851 sysmmu_scaler2w: sysmmu@0x128E0000 {
852 compatible = "samsung,exynos-sysmmu";
853 reg = <0x128E0000 0x1000>;
854 interrupt-parent = <&combiner>;
856 clock-names = "sysmmu", "master";
857 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
861 sysmmu_rotator: sysmmu@0x11D40000 {
862 compatible = "samsung,exynos-sysmmu";
863 reg = <0x11D40000 0x1000>;
864 interrupt-parent = <&combiner>;
866 clock-names = "sysmmu", "master";
867 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
871 sysmmu_jpeg0: sysmmu@0x11F10000 {
872 compatible = "samsung,exynos-sysmmu";
873 reg = <0x11F10000 0x1000>;
874 interrupt-parent = <&combiner>;
876 clock-names = "sysmmu", "master";
877 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
881 sysmmu_jpeg1: sysmmu@0x11F20000 {
882 compatible = "samsung,exynos-sysmmu";
883 reg = <0x11F20000 0x1000>;
884 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
885 clock-names = "sysmmu", "master";
886 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
890 sysmmu_mfc_l: sysmmu@0x11200000 {
891 compatible = "samsung,exynos-sysmmu";
892 reg = <0x11200000 0x1000>;
893 interrupt-parent = <&combiner>;
895 clock-names = "sysmmu", "master";
896 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
897 power-domains = <&mfc_pd>;
901 sysmmu_mfc_r: sysmmu@0x11210000 {
902 compatible = "samsung,exynos-sysmmu";
903 reg = <0x11210000 0x1000>;
904 interrupt-parent = <&combiner>;
906 clock-names = "sysmmu", "master";
907 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
908 power-domains = <&mfc_pd>;
912 sysmmu_fimd1_0: sysmmu@0x14640000 {
913 compatible = "samsung,exynos-sysmmu";
914 reg = <0x14640000 0x1000>;
915 interrupt-parent = <&combiner>;
917 clock-names = "sysmmu", "master";
918 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
919 power-domains = <&disp_pd>;
923 sysmmu_fimd1_1: sysmmu@0x14680000 {
924 compatible = "samsung,exynos-sysmmu";
925 reg = <0x14680000 0x1000>;
926 interrupt-parent = <&combiner>;
928 clock-names = "sysmmu", "master";
929 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
930 power-domains = <&disp_pd>;
934 bus_wcore: bus_wcore {
935 compatible = "samsung,exynos-bus";
936 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
938 operating-points-v2 = <&bus_wcore_opp_table>;
943 compatible = "samsung,exynos-bus";
944 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
946 operating-points-v2 = <&bus_noc_opp_table>;
950 bus_fsys_apb: bus_fsys_apb {
951 compatible = "samsung,exynos-bus";
952 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
954 operating-points-v2 = <&bus_fsys_apb_opp_table>;
959 compatible = "samsung,exynos-bus";
960 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
962 operating-points-v2 = <&bus_fsys_apb_opp_table>;
966 bus_fsys2: bus_fsys2 {
967 compatible = "samsung,exynos-bus";
968 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
970 operating-points-v2 = <&bus_fsys2_opp_table>;
975 compatible = "samsung,exynos-bus";
976 clocks = <&clock CLK_DOUT_ACLK333>;
978 operating-points-v2 = <&bus_mfc_opp_table>;
983 compatible = "samsung,exynos-bus";
984 clocks = <&clock CLK_DOUT_ACLK266>;
986 operating-points-v2 = <&bus_gen_opp_table>;
991 compatible = "samsung,exynos-bus";
992 clocks = <&clock CLK_DOUT_ACLK66>;
994 operating-points-v2 = <&bus_peri_opp_table>;
999 compatible = "samsung,exynos-bus";
1000 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1001 clock-names = "bus";
1002 operating-points-v2 = <&bus_g2d_opp_table>;
1003 status = "disabled";
1006 bus_g2d_acp: bus_g2d_acp {
1007 compatible = "samsung,exynos-bus";
1008 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1009 clock-names = "bus";
1010 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1011 status = "disabled";
1014 bus_jpeg: bus_jpeg {
1015 compatible = "samsung,exynos-bus";
1016 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1017 clock-names = "bus";
1018 operating-points-v2 = <&bus_jpeg_opp_table>;
1019 status = "disabled";
1022 bus_jpeg_apb: bus_jpeg_apb {
1023 compatible = "samsung,exynos-bus";
1024 clocks = <&clock CLK_DOUT_ACLK166>;
1025 clock-names = "bus";
1026 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1027 status = "disabled";
1030 bus_disp1_fimd: bus_disp1_fimd {
1031 compatible = "samsung,exynos-bus";
1032 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1033 clock-names = "bus";
1034 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1035 status = "disabled";
1038 bus_disp1: bus_disp1 {
1039 compatible = "samsung,exynos-bus";
1040 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1041 clock-names = "bus";
1042 operating-points-v2 = <&bus_disp1_opp_table>;
1043 status = "disabled";
1046 bus_gscl_scaler: bus_gscl_scaler {
1047 compatible = "samsung,exynos-bus";
1048 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1049 clock-names = "bus";
1050 operating-points-v2 = <&bus_gscl_opp_table>;
1051 status = "disabled";
1054 bus_mscl: bus_mscl {
1055 compatible = "samsung,exynos-bus";
1056 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1057 clock-names = "bus";
1058 operating-points-v2 = <&bus_mscl_opp_table>;
1059 status = "disabled";
1062 bus_wcore_opp_table: opp_table2 {
1063 compatible = "operating-points-v2";
1066 opp-hz = /bits/ 64 <84000000>;
1067 opp-microvolt = <925000>;
1070 opp-hz = /bits/ 64 <111000000>;
1071 opp-microvolt = <950000>;
1074 opp-hz = /bits/ 64 <222000000>;
1075 opp-microvolt = <950000>;
1078 opp-hz = /bits/ 64 <333000000>;
1079 opp-microvolt = <950000>;
1082 opp-hz = /bits/ 64 <400000000>;
1083 opp-microvolt = <987500>;
1087 bus_noc_opp_table: opp_table3 {
1088 compatible = "operating-points-v2";
1091 opp-hz = /bits/ 64 <67000000>;
1094 opp-hz = /bits/ 64 <75000000>;
1097 opp-hz = /bits/ 64 <86000000>;
1100 opp-hz = /bits/ 64 <100000000>;
1104 bus_fsys_apb_opp_table: opp_table4 {
1105 compatible = "operating-points-v2";
1109 opp-hz = /bits/ 64 <100000000>;
1112 opp-hz = /bits/ 64 <200000000>;
1116 bus_fsys2_opp_table: opp_table5 {
1117 compatible = "operating-points-v2";
1120 opp-hz = /bits/ 64 <75000000>;
1123 opp-hz = /bits/ 64 <100000000>;
1126 opp-hz = /bits/ 64 <150000000>;
1130 bus_mfc_opp_table: opp_table6 {
1131 compatible = "operating-points-v2";
1134 opp-hz = /bits/ 64 <96000000>;
1137 opp-hz = /bits/ 64 <111000000>;
1140 opp-hz = /bits/ 64 <167000000>;
1143 opp-hz = /bits/ 64 <222000000>;
1146 opp-hz = /bits/ 64 <333000000>;
1150 bus_gen_opp_table: opp_table7 {
1151 compatible = "operating-points-v2";
1154 opp-hz = /bits/ 64 <89000000>;
1157 opp-hz = /bits/ 64 <133000000>;
1160 opp-hz = /bits/ 64 <178000000>;
1163 opp-hz = /bits/ 64 <267000000>;
1167 bus_peri_opp_table: opp_table8 {
1168 compatible = "operating-points-v2";
1171 opp-hz = /bits/ 64 <67000000>;
1175 bus_g2d_opp_table: opp_table9 {
1176 compatible = "operating-points-v2";
1179 opp-hz = /bits/ 64 <84000000>;
1182 opp-hz = /bits/ 64 <167000000>;
1185 opp-hz = /bits/ 64 <222000000>;
1188 opp-hz = /bits/ 64 <300000000>;
1191 opp-hz = /bits/ 64 <333000000>;
1195 bus_g2d_acp_opp_table: opp_table10 {
1196 compatible = "operating-points-v2";
1199 opp-hz = /bits/ 64 <67000000>;
1202 opp-hz = /bits/ 64 <133000000>;
1205 opp-hz = /bits/ 64 <178000000>;
1208 opp-hz = /bits/ 64 <267000000>;
1212 bus_jpeg_opp_table: opp_table11 {
1213 compatible = "operating-points-v2";
1216 opp-hz = /bits/ 64 <75000000>;
1219 opp-hz = /bits/ 64 <150000000>;
1222 opp-hz = /bits/ 64 <200000000>;
1225 opp-hz = /bits/ 64 <300000000>;
1229 bus_jpeg_apb_opp_table: opp_table12 {
1230 compatible = "operating-points-v2";
1233 opp-hz = /bits/ 64 <84000000>;
1236 opp-hz = /bits/ 64 <111000000>;
1239 opp-hz = /bits/ 64 <134000000>;
1242 opp-hz = /bits/ 64 <167000000>;
1246 bus_disp1_fimd_opp_table: opp_table13 {
1247 compatible = "operating-points-v2";
1250 opp-hz = /bits/ 64 <120000000>;
1253 opp-hz = /bits/ 64 <200000000>;
1257 bus_disp1_opp_table: opp_table14 {
1258 compatible = "operating-points-v2";
1261 opp-hz = /bits/ 64 <120000000>;
1264 opp-hz = /bits/ 64 <200000000>;
1267 opp-hz = /bits/ 64 <300000000>;
1271 bus_gscl_opp_table: opp_table15 {
1272 compatible = "operating-points-v2";
1275 opp-hz = /bits/ 64 <150000000>;
1278 opp-hz = /bits/ 64 <200000000>;
1281 opp-hz = /bits/ 64 <300000000>;
1285 bus_mscl_opp_table: opp_table16 {
1286 compatible = "operating-points-v2";
1289 opp-hz = /bits/ 64 <84000000>;
1292 opp-hz = /bits/ 64 <167000000>;
1295 opp-hz = /bits/ 64 <222000000>;
1298 opp-hz = /bits/ 64 <333000000>;
1301 opp-hz = /bits/ 64 <400000000>;
1307 cpu0_thermal: cpu0-thermal {
1308 thermal-sensors = <&tmu_cpu0>;
1309 #include "exynos5420-trip-points.dtsi"
1311 cpu1_thermal: cpu1-thermal {
1312 thermal-sensors = <&tmu_cpu1>;
1313 #include "exynos5420-trip-points.dtsi"
1315 cpu2_thermal: cpu2-thermal {
1316 thermal-sensors = <&tmu_cpu2>;
1317 #include "exynos5420-trip-points.dtsi"
1319 cpu3_thermal: cpu3-thermal {
1320 thermal-sensors = <&tmu_cpu3>;
1321 #include "exynos5420-trip-points.dtsi"
1323 gpu_thermal: gpu-thermal {
1324 thermal-sensors = <&tmu_gpu>;
1325 #include "exynos5420-trip-points.dtsi"
1331 clocks = <&clock CLK_DP1>;
1335 power-domains = <&disp_pd>;
1339 compatible = "samsung,exynos5420-fimd";
1340 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1341 clock-names = "sclk_fimd", "fimd";
1342 power-domains = <&disp_pd>;
1343 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1344 iommu-names = "m0", "m1";
1348 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1349 clocks = <&clock CLK_G2D>;
1350 clock-names = "fimg2d";
1355 clocks = <&clock CLK_I2C0>;
1356 clock-names = "i2c";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&i2c0_bus>;
1362 clocks = <&clock CLK_I2C1>;
1363 clock-names = "i2c";
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&i2c1_bus>;
1369 clocks = <&clock CLK_I2C2>;
1370 clock-names = "i2c";
1371 pinctrl-names = "default";
1372 pinctrl-0 = <&i2c2_bus>;
1376 clocks = <&clock CLK_I2C3>;
1377 clock-names = "i2c";
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&i2c3_bus>;
1383 clocks = <&clock CLK_USI0>;
1384 clock-names = "hsi2c";
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&i2c4_hs_bus>;
1390 clocks = <&clock CLK_USI1>;
1391 clock-names = "hsi2c";
1392 pinctrl-names = "default";
1393 pinctrl-0 = <&i2c5_hs_bus>;
1397 clocks = <&clock CLK_USI2>;
1398 clock-names = "hsi2c";
1399 pinctrl-names = "default";
1400 pinctrl-0 = <&i2c6_hs_bus>;
1404 clocks = <&clock CLK_USI3>;
1405 clock-names = "hsi2c";
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&i2c7_hs_bus>;
1411 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1412 clock-names = "fin_pll", "mct";
1416 clocks = <&clock CLK_SSS>;
1417 clock-names = "secss";
1421 clocks = <&clock CLK_PWM>;
1422 clock-names = "timers";
1426 clocks = <&clock CLK_RTC>;
1427 clock-names = "rtc";
1428 interrupt-parent = <&pmu_system_controller>;
1429 status = "disabled";
1433 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1434 clock-names = "uart", "clk_uart_baud0";
1435 dmas = <&pdma0 13>, <&pdma0 14>;
1436 dma-names = "rx", "tx";
1440 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1441 clock-names = "uart", "clk_uart_baud0";
1442 dmas = <&pdma1 15>, <&pdma1 16>;
1443 dma-names = "rx", "tx";
1447 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1448 clock-names = "uart", "clk_uart_baud0";
1449 dmas = <&pdma0 15>, <&pdma0 16>;
1450 dma-names = "rx", "tx";
1454 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1455 clock-names = "uart", "clk_uart_baud0";
1456 dmas = <&pdma1 17>, <&pdma1 18>;
1457 dma-names = "rx", "tx";
1461 clocks = <&clock CLK_SSS>;
1462 clock-names = "secss";
1466 clocks = <&clock CLK_SSS>;
1467 clock-names = "secss";
1471 clocks = <&clock CLK_USBD300>;
1472 clock-names = "usbdrd30";
1476 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1477 clock-names = "phy", "ref";
1478 samsung,pmu-syscon = <&pmu_system_controller>;
1482 clocks = <&clock CLK_USBD301>;
1483 clock-names = "usbdrd30";
1487 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1491 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1492 clock-names = "phy", "ref";
1493 samsung,pmu-syscon = <&pmu_system_controller>;
1497 clocks = <&clock CLK_USBH20>;
1498 clock-names = "usbhost";
1502 clocks = <&clock CLK_USBH20>;
1503 clock-names = "usbhost";
1507 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1508 clock-names = "phy", "ref";
1509 samsung,sysreg-phandle = <&sysreg_system_controller>;
1510 samsung,pmureg-phandle = <&pmu_system_controller>;
1514 clocks = <&clock CLK_WDT>;
1515 clock-names = "watchdog";
1516 samsung,syscon-phandle = <&pmu_system_controller>;
1519 #include "exynos5420-pinctrl.dtsi"