arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos54xx.dtsi"
  17 #include <dt-bindings/clock/exynos5420.h>
  18 #include <dt-bindings/clock/exynos-audss-clk.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420", "samsung,exynos5";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c8 = &hsi2c_8;
  34                 i2c9 = &hsi2c_9;
  35                 i2c10 = &hsi2c_10;
  36                 gsc0 = &gsc_0;
  37                 gsc1 = &gsc_1;
  38                 spi0 = &spi_0;
  39                 spi1 = &spi_1;
  40                 spi2 = &spi_2;
  41         };
  42
  43         /*
  44          * The 'cpus' node is not present here but instead it is provided
  45          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
  46          */
  47
  48         soc: soc {
  49                 cluster_a15_opp_table: opp_table0 {
  50                         compatible = "operating-points-v2";
  51                         opp-shared;
  52                         opp-1800000000 {
  53                                 opp-hz = /bits/ 64 <1800000000>;
  54                                 opp-microvolt = <1250000>;
  55                                 clock-latency-ns = <140000>;
  56                         };
  57                         opp-1700000000 {
  58                                 opp-hz = /bits/ 64 <1700000000>;
  59                                 opp-microvolt = <1212500>;
  60                                 clock-latency-ns = <140000>;
  61                         };
  62                         opp-1600000000 {
  63                                 opp-hz = /bits/ 64 <1600000000>;
  64                                 opp-microvolt = <1175000>;
  65                                 clock-latency-ns = <140000>;
  66                         };
  67                         opp-1500000000 {
  68                                 opp-hz = /bits/ 64 <1500000000>;
  69                                 opp-microvolt = <1137500>;
  70                                 clock-latency-ns = <140000>;
  71                         };
  72                         opp-1400000000 {
  73                                 opp-hz = /bits/ 64 <1400000000>;
  74                                 opp-microvolt = <1112500>;
  75                                 clock-latency-ns = <140000>;
  76                         };
  77                         opp-1300000000 {
  78                                 opp-hz = /bits/ 64 <1300000000>;
  79                                 opp-microvolt = <1062500>;
  80                                 clock-latency-ns = <140000>;
  81                         };
  82                         opp-1200000000 {
  83                                 opp-hz = /bits/ 64 <1200000000>;
  84                                 opp-microvolt = <1037500>;
  85                                 clock-latency-ns = <140000>;
  86                         };
  87                         opp-1100000000 {
  88                                 opp-hz = /bits/ 64 <1100000000>;
  89                                 opp-microvolt = <1012500>;
  90                                 clock-latency-ns = <140000>;
  91                         };
  92                         opp-1000000000 {
  93                                 opp-hz = /bits/ 64 <1000000000>;
  94                                 opp-microvolt = < 987500>;
  95                                 clock-latency-ns = <140000>;
  96                         };
  97                         opp-900000000 {
  98                                 opp-hz = /bits/ 64 <900000000>;
  99                                 opp-microvolt = < 962500>;
 100                                 clock-latency-ns = <140000>;
 101                         };
 102                         opp-800000000 {
 103                                 opp-hz = /bits/ 64 <800000000>;
 104                                 opp-microvolt = < 937500>;
 105                                 clock-latency-ns = <140000>;
 106                         };
 107                         opp-700000000 {
 108                                 opp-hz = /bits/ 64 <700000000>;
 109                                 opp-microvolt = < 912500>;
 110                                 clock-latency-ns = <140000>;
 111                         };
 112                 };
 113
 114                 cluster_a7_opp_table: opp_table1 {
 115                         compatible = "operating-points-v2";
 116                         opp-shared;
 117                         opp-1300000000 {
 118                                 opp-hz = /bits/ 64 <1300000000>;
 119                                 opp-microvolt = <1275000>;
 120                                 clock-latency-ns = <140000>;
 121                         };
 122                         opp-1200000000 {
 123                                 opp-hz = /bits/ 64 <1200000000>;
 124                                 opp-microvolt = <1212500>;
 125                                 clock-latency-ns = <140000>;
 126                         };
 127                         opp-1100000000 {
 128                                 opp-hz = /bits/ 64 <1100000000>;
 129                                 opp-microvolt = <1162500>;
 130                                 clock-latency-ns = <140000>;
 131                         };
 132                         opp-1000000000 {
 133                                 opp-hz = /bits/ 64 <1000000000>;
 134                                 opp-microvolt = <1112500>;
 135                                 clock-latency-ns = <140000>;
 136                         };
 137                         opp-900000000 {
 138                                 opp-hz = /bits/ 64 <900000000>;
 139                                 opp-microvolt = <1062500>;
 140                                 clock-latency-ns = <140000>;
 141                         };
 142                         opp-800000000 {
 143                                 opp-hz = /bits/ 64 <800000000>;
 144                                 opp-microvolt = <1025000>;
 145                                 clock-latency-ns = <140000>;
 146                         };
 147                         opp-700000000 {
 148                                 opp-hz = /bits/ 64 <700000000>;
 149                                 opp-microvolt = <975000>;
 150                                 clock-latency-ns = <140000>;
 151                         };
 152                         opp-600000000 {
 153                                 opp-hz = /bits/ 64 <600000000>;
 154                                 opp-microvolt = <937500>;
 155                                 clock-latency-ns = <140000>;
 156                         };
 157                 };
 158
 159                 cci: cci@10d20000 {
 160                         compatible = "arm,cci-400";
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         reg = <0x10d20000 0x1000>;
 164                         ranges = <0x0 0x10d20000 0x6000>;
 165
 166                         cci_control0: slave-if@4000 {
 167                                 compatible = "arm,cci-400-ctrl-if";
 168                                 interface-type = "ace";
 169                                 reg = <0x4000 0x1000>;
 170                         };
 171                         cci_control1: slave-if@5000 {
 172                                 compatible = "arm,cci-400-ctrl-if";
 173                                 interface-type = "ace";
 174                                 reg = <0x5000 0x1000>;
 175                         };
 176                 };
 177
 178                 clock: clock-controller@10010000 {
 179                         compatible = "samsung,exynos5420-clock";
 180                         reg = <0x10010000 0x30000>;
 181                         #clock-cells = <1>;
 182                 };
 183
 184                 clock_audss: audss-clock-controller@3810000 {
 185                         compatible = "samsung,exynos5420-audss-clock";
 186                         reg = <0x03810000 0x0C>;
 187                         #clock-cells = <1>;
 188                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 189                                  <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 190                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 191                         power-domains = <&mau_pd>;
 192                 };
 193
 194                 mfc: codec@11000000 {
 195                         compatible = "samsung,mfc-v7";
 196                         reg = <0x11000000 0x10000>;
 197                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&clock CLK_MFC>;
 199                         clock-names = "mfc";
 200                         power-domains = <&mfc_pd>;
 201                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 202                         iommu-names = "left", "right";
 203                 };
 204
 205                 mmc_0: mmc@12200000 {
 206                         compatible = "samsung,exynos5420-dw-mshc-smu";
 207                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         reg = <0x12200000 0x2000>;
 211                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 212                         clock-names = "biu", "ciu";
 213                         fifo-depth = <0x40>;
 214                         status = "disabled";
 215                 };
 216
 217                 mmc_1: mmc@12210000 {
 218                         compatible = "samsung,exynos5420-dw-mshc-smu";
 219                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         reg = <0x12210000 0x2000>;
 223                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 224                         clock-names = "biu", "ciu";
 225                         fifo-depth = <0x40>;
 226                         status = "disabled";
 227                 };
 228
 229                 mmc_2: mmc@12220000 {
 230                         compatible = "samsung,exynos5420-dw-mshc";
 231                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         reg = <0x12220000 0x1000>;
 235                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 236                         clock-names = "biu", "ciu";
 237                         fifo-depth = <0x40>;
 238                         status = "disabled";
 239                 };
 240
 241                 nocp_mem0_0: nocp@10CA1000 {
 242                         compatible = "samsung,exynos5420-nocp";
 243                         reg = <0x10CA1000 0x200>;
 244                         status = "disabled";
 245                 };
 246
 247                 nocp_mem0_1: nocp@10CA1400 {
 248                         compatible = "samsung,exynos5420-nocp";
 249                         reg = <0x10CA1400 0x200>;
 250                         status = "disabled";
 251                 };
 252
 253                 nocp_mem1_0: nocp@10CA1800 {
 254                         compatible = "samsung,exynos5420-nocp";
 255                         reg = <0x10CA1800 0x200>;
 256                         status = "disabled";
 257                 };
 258
 259                 nocp_mem1_1: nocp@10CA1C00 {
 260                         compatible = "samsung,exynos5420-nocp";
 261                         reg = <0x10CA1C00 0x200>;
 262                         status = "disabled";
 263                 };
 264
 265                 nocp_g3d_0: nocp@11A51000 {
 266                         compatible = "samsung,exynos5420-nocp";
 267                         reg = <0x11A51000 0x200>;
 268                         status = "disabled";
 269                 };
 270
 271                 nocp_g3d_1: nocp@11A51400 {
 272                         compatible = "samsung,exynos5420-nocp";
 273                         reg = <0x11A51400 0x200>;
 274                         status = "disabled";
 275                 };
 276
 277                 gsc_pd: power-domain@10044000 {
 278                         compatible = "samsung,exynos4210-pd";
 279                         reg = <0x10044000 0x20>;
 280                         #power-domain-cells = <0>;
 281                         label = "GSC";
 282                         clocks = <&clock CLK_FIN_PLL>,
 283                                  <&clock CLK_MOUT_USER_ACLK300_GSCL>,
 284                                  <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 285                         clock-names = "oscclk", "clk0", "asb0", "asb1";
 286                 };
 287
 288                 isp_pd: power-domain@10044020 {
 289                         compatible = "samsung,exynos4210-pd";
 290                         reg = <0x10044020 0x20>;
 291                         #power-domain-cells = <0>;
 292                         label = "ISP";
 293                 };
 294
 295                 mfc_pd: power-domain@10044060 {
 296                         compatible = "samsung,exynos4210-pd";
 297                         reg = <0x10044060 0x20>;
 298                         clocks = <&clock CLK_FIN_PLL>,
 299                                  <&clock CLK_MOUT_USER_ACLK333>,
 300                                  <&clock CLK_ACLK333>;
 301                         clock-names = "oscclk", "clk0","asb0";
 302                         #power-domain-cells = <0>;
 303                         label = "MFC";
 304                 };
 305
 306                 msc_pd: power-domain@10044120 {
 307                         compatible = "samsung,exynos4210-pd";
 308                         reg = <0x10044120 0x20>;
 309                         #power-domain-cells = <0>;
 310                         label = "MSC";
 311                 };
 312
 313                 disp_pd: power-domain@100440C0 {
 314                         compatible = "samsung,exynos4210-pd";
 315                         reg = <0x100440C0 0x20>;
 316                         #power-domain-cells = <0>;
 317                         label = "DISP";
 318                         clocks = <&clock CLK_FIN_PLL>,
 319                                  <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 320                                  <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 321                                  <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 322                                  <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 323                         clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 324                 };
 325
 326                 mau_pd: power-domain@100440E0 {
 327                         compatible = "samsung,exynos4210-pd";
 328                         reg = <0x100440E0 0x20>;
 329                         #power-domain-cells = <0>;
 330                         label = "MAU";
 331                 };
 332
 333                 pinctrl_0: pinctrl@13400000 {
 334                         compatible = "samsung,exynos5420-pinctrl";
 335                         reg = <0x13400000 0x1000>;
 336                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 337
 338                         wakeup-interrupt-controller {
 339                                 compatible = "samsung,exynos4210-wakeup-eint";
 340                                 interrupt-parent = <&gic>;
 341                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 342                         };
 343                 };
 344
 345                 pinctrl_1: pinctrl@13410000 {
 346                         compatible = "samsung,exynos5420-pinctrl";
 347                         reg = <0x13410000 0x1000>;
 348                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 349                 };
 350
 351                 pinctrl_2: pinctrl@14000000 {
 352                         compatible = "samsung,exynos5420-pinctrl";
 353                         reg = <0x14000000 0x1000>;
 354                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 355                 };
 356
 357                 pinctrl_3: pinctrl@14010000 {
 358                         compatible = "samsung,exynos5420-pinctrl";
 359                         reg = <0x14010000 0x1000>;
 360                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 361                 };
 362
 363                 pinctrl_4: pinctrl@3860000 {
 364                         compatible = "samsung,exynos5420-pinctrl";
 365                         reg = <0x03860000 0x1000>;
 366                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 367                         power-domains = <&mau_pd>;
 368                 };
 369
 370                 amba {
 371                         #address-cells = <1>;
 372                         #size-cells = <1>;
 373                         compatible = "simple-bus";
 374                         interrupt-parent = <&gic>;
 375                         ranges;
 376
 377                         adma: adma@3880000 {
 378                                 compatible = "arm,pl330", "arm,primecell";
 379                                 reg = <0x03880000 0x1000>;
 380                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 381                                 clocks = <&clock_audss EXYNOS_ADMA>;
 382                                 clock-names = "apb_pclk";
 383                                 #dma-cells = <1>;
 384                                 #dma-channels = <6>;
 385                                 #dma-requests = <16>;
 386                                 power-domains = <&mau_pd>;
 387                         };
 388
 389                         pdma0: pdma@121A0000 {
 390                                 compatible = "arm,pl330", "arm,primecell";
 391                                 reg = <0x121A0000 0x1000>;
 392                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 393                                 clocks = <&clock CLK_PDMA0>;
 394                                 clock-names = "apb_pclk";
 395                                 #dma-cells = <1>;
 396                                 #dma-channels = <8>;
 397                                 #dma-requests = <32>;
 398                         };
 399
 400                         pdma1: pdma@121B0000 {
 401                                 compatible = "arm,pl330", "arm,primecell";
 402                                 reg = <0x121B0000 0x1000>;
 403                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 404                                 clocks = <&clock CLK_PDMA1>;
 405                                 clock-names = "apb_pclk";
 406                                 #dma-cells = <1>;
 407                                 #dma-channels = <8>;
 408                                 #dma-requests = <32>;
 409                         };
 410
 411                         mdma0: mdma@10800000 {
 412                                 compatible = "arm,pl330", "arm,primecell";
 413                                 reg = <0x10800000 0x1000>;
 414                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 415                                 clocks = <&clock CLK_MDMA0>;
 416                                 clock-names = "apb_pclk";
 417                                 #dma-cells = <1>;
 418                                 #dma-channels = <8>;
 419                                 #dma-requests = <1>;
 420                         };
 421
 422                         mdma1: mdma@11C10000 {
 423                                 compatible = "arm,pl330", "arm,primecell";
 424                                 reg = <0x11C10000 0x1000>;
 425                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 426                                 clocks = <&clock CLK_MDMA1>;
 427                                 clock-names = "apb_pclk";
 428                                 #dma-cells = <1>;
 429                                 #dma-channels = <8>;
 430                                 #dma-requests = <1>;
 431                                 /*
 432                                  * MDMA1 can support both secure and non-secure
 433                                  * AXI transactions. When this is enabled in
 434                                  * the kernel for boards that run in secure
 435                                  * mode, we are getting imprecise external
 436                                  * aborts causing the kernel to oops.
 437                                  */
 438                                 status = "disabled";
 439                         };
 440                 };
 441
 442                 i2s0: i2s@3830000 {
 443                         compatible = "samsung,exynos5420-i2s";
 444                         reg = <0x03830000 0x100>;
 445                         dmas = <&adma 0
 446                                 &adma 2
 447                                 &adma 1>;
 448                         dma-names = "tx", "rx", "tx-sec";
 449                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 450                                 <&clock_audss EXYNOS_I2S_BUS>,
 451                                 <&clock_audss EXYNOS_SCLK_I2S>;
 452                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 453                         #clock-cells = <1>;
 454                         clock-output-names = "i2s_cdclk0";
 455                         #sound-dai-cells = <1>;
 456                         samsung,idma-addr = <0x03000000>;
 457                         pinctrl-names = "default";
 458                         pinctrl-0 = <&i2s0_bus>;
 459                         power-domains = <&mau_pd>;
 460                         status = "disabled";
 461                 };
 462
 463                 i2s1: i2s@12D60000 {
 464                         compatible = "samsung,exynos5420-i2s";
 465                         reg = <0x12D60000 0x100>;
 466                         dmas = <&pdma1 12
 467                                 &pdma1 11>;
 468                         dma-names = "tx", "rx";
 469                         clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 470                         clock-names = "iis", "i2s_opclk0";
 471                         #clock-cells = <1>;
 472                         clock-output-names = "i2s_cdclk1";
 473                         #sound-dai-cells = <1>;
 474                         pinctrl-names = "default";
 475                         pinctrl-0 = <&i2s1_bus>;
 476                         status = "disabled";
 477                 };
 478
 479                 i2s2: i2s@12D70000 {
 480                         compatible = "samsung,exynos5420-i2s";
 481                         reg = <0x12D70000 0x100>;
 482                         dmas = <&pdma0 12
 483                                 &pdma0 11>;
 484                         dma-names = "tx", "rx";
 485                         clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 486                         clock-names = "iis", "i2s_opclk0";
 487                         #clock-cells = <1>;
 488                         clock-output-names = "i2s_cdclk2";
 489                         #sound-dai-cells = <1>;
 490                         pinctrl-names = "default";
 491                         pinctrl-0 = <&i2s2_bus>;
 492                         status = "disabled";
 493                 };
 494
 495                 spi_0: spi@12d20000 {
 496                         compatible = "samsung,exynos4210-spi";
 497                         reg = <0x12d20000 0x100>;
 498                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 499                         dmas = <&pdma0 5
 500                                 &pdma0 4>;
 501                         dma-names = "tx", "rx";
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&spi0_bus>;
 506                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 507                         clock-names = "spi", "spi_busclk0";
 508                         status = "disabled";
 509                 };
 510
 511                 spi_1: spi@12d30000 {
 512                         compatible = "samsung,exynos4210-spi";
 513                         reg = <0x12d30000 0x100>;
 514                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 515                         dmas = <&pdma1 5
 516                                 &pdma1 4>;
 517                         dma-names = "tx", "rx";
 518                         #address-cells = <1>;
 519                         #size-cells = <0>;
 520                         pinctrl-names = "default";
 521                         pinctrl-0 = <&spi1_bus>;
 522                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 523                         clock-names = "spi", "spi_busclk0";
 524                         status = "disabled";
 525                 };
 526
 527                 spi_2: spi@12d40000 {
 528                         compatible = "samsung,exynos4210-spi";
 529                         reg = <0x12d40000 0x100>;
 530                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 531                         dmas = <&pdma0 7
 532                                 &pdma0 6>;
 533                         dma-names = "tx", "rx";
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         pinctrl-names = "default";
 537                         pinctrl-0 = <&spi2_bus>;
 538                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 539                         clock-names = "spi", "spi_busclk0";
 540                         status = "disabled";
 541                 };
 542
 543                 dp_phy: dp-video-phy {
 544                         compatible = "samsung,exynos5420-dp-video-phy";
 545                         samsung,pmu-syscon = <&pmu_system_controller>;
 546                         #phy-cells = <0>;
 547                 };
 548
 549                 mipi_phy: mipi-video-phy {
 550                         compatible = "samsung,s5pv210-mipi-video-phy";
 551                         syscon = <&pmu_system_controller>;
 552                         #phy-cells = <1>;
 553                 };
 554
 555                 dsi@14500000 {
 556                         compatible = "samsung,exynos5410-mipi-dsi";
 557                         reg = <0x14500000 0x10000>;
 558                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 559                         phys = <&mipi_phy 1>;
 560                         phy-names = "dsim";
 561                         clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 562                         clock-names = "bus_clk", "pll_clk";
 563                         #address-cells = <1>;
 564                         #size-cells = <0>;
 565                         status = "disabled";
 566                 };
 567
 568                 adc: adc@12D10000 {
 569                         compatible = "samsung,exynos-adc-v2";
 570                         reg = <0x12D10000 0x100>;
 571                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&clock CLK_TSADC>;
 573                         clock-names = "adc";
 574                         #io-channel-cells = <1>;
 575                         io-channel-ranges;
 576                         samsung,syscon-phandle = <&pmu_system_controller>;
 577                         status = "disabled";
 578                 };
 579
 580                 hsi2c_8: i2c@12E00000 {
 581                         compatible = "samsung,exynos5250-hsi2c";
 582                         reg = <0x12E00000 0x1000>;
 583                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         pinctrl-names = "default";
 587                         pinctrl-0 = <&i2c8_hs_bus>;
 588                         clocks = <&clock CLK_USI4>;
 589                         clock-names = "hsi2c";
 590                         status = "disabled";
 591                 };
 592
 593                 hsi2c_9: i2c@12E10000 {
 594                         compatible = "samsung,exynos5250-hsi2c";
 595                         reg = <0x12E10000 0x1000>;
 596                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 597                         #address-cells = <1>;
 598                         #size-cells = <0>;
 599                         pinctrl-names = "default";
 600                         pinctrl-0 = <&i2c9_hs_bus>;
 601                         clocks = <&clock CLK_USI5>;
 602                         clock-names = "hsi2c";
 603                         status = "disabled";
 604                 };
 605
 606                 hsi2c_10: i2c@12E20000 {
 607                         compatible = "samsung,exynos5250-hsi2c";
 608                         reg = <0x12E20000 0x1000>;
 609                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                         pinctrl-names = "default";
 613                         pinctrl-0 = <&i2c10_hs_bus>;
 614                         clocks = <&clock CLK_USI6>;
 615                         clock-names = "hsi2c";
 616                         status = "disabled";
 617                 };
 618
 619                 hdmi: hdmi@14530000 {
 620                         compatible = "samsung,exynos5420-hdmi";
 621                         reg = <0x14530000 0x70000>;
 622                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 623                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 624                                  <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 625                                  <&clock CLK_MOUT_HDMI>;
 626                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 627                                 "sclk_hdmiphy", "mout_hdmi";
 628                         phy = <&hdmiphy>;
 629                         samsung,syscon-phandle = <&pmu_system_controller>;
 630                         status = "disabled";
 631                         power-domains = <&disp_pd>;
 632                         #sound-dai-cells = <0>;
 633                 };
 634
 635                 hdmiphy: hdmiphy@145D0000 {
 636                         reg = <0x145D0000 0x20>;
 637                 };
 638
 639                 hdmicec: cec@101B0000 {
 640                         compatible = "samsung,s5p-cec";
 641                         reg = <0x101B0000 0x200>;
 642                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 643                         clocks = <&clock CLK_HDMI_CEC>;
 644                         clock-names = "hdmicec";
 645                         samsung,syscon-phandle = <&pmu_system_controller>;
 646                         hdmi-phandle = <&hdmi>;
 647                         pinctrl-names = "default";
 648                         pinctrl-0 = <&hdmi_cec>;
 649                         status = "disabled";
 650                 };
 651
 652                 mixer: mixer@14450000 {
 653                         compatible = "samsung,exynos5420-mixer";
 654                         reg = <0x14450000 0x10000>;
 655                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 656                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 657                                  <&clock CLK_SCLK_HDMI>;
 658                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 659                         power-domains = <&disp_pd>;
 660                         iommus = <&sysmmu_tv>;
 661                         status = "disabled";
 662                 };
 663
 664                 rotator: rotator@11C00000 {
 665                         compatible = "samsung,exynos5250-rotator";
 666                         reg = <0x11C00000 0x64>;
 667                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 668                         clocks = <&clock CLK_ROTATOR>;
 669                         clock-names = "rotator";
 670                         iommus = <&sysmmu_rotator>;
 671                 };
 672
 673                 gsc_0: video-scaler@13e00000 {
 674                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 675                         reg = <0x13e00000 0x1000>;
 676                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 677                         clocks = <&clock CLK_GSCL0>;
 678                         clock-names = "gscl";
 679                         power-domains = <&gsc_pd>;
 680                         iommus = <&sysmmu_gscl0>;
 681                 };
 682
 683                 gsc_1: video-scaler@13e10000 {
 684                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 685                         reg = <0x13e10000 0x1000>;
 686                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 687                         clocks = <&clock CLK_GSCL1>;
 688                         clock-names = "gscl";
 689                         power-domains = <&gsc_pd>;
 690                         iommus = <&sysmmu_gscl1>;
 691                 };
 692
 693                 jpeg_0: jpeg@11F50000 {
 694                         compatible = "samsung,exynos5420-jpeg";
 695                         reg = <0x11F50000 0x1000>;
 696                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 697                         clock-names = "jpeg";
 698                         clocks = <&clock CLK_JPEG>;
 699                         iommus = <&sysmmu_jpeg0>;
 700                 };
 701
 702                 jpeg_1: jpeg@11F60000 {
 703                         compatible = "samsung,exynos5420-jpeg";
 704                         reg = <0x11F60000 0x1000>;
 705                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 706                         clock-names = "jpeg";
 707                         clocks = <&clock CLK_JPEG2>;
 708                         iommus = <&sysmmu_jpeg1>;
 709                 };
 710
 711                 pmu_system_controller: system-controller@10040000 {
 712                         compatible = "samsung,exynos5420-pmu", "syscon";
 713                         reg = <0x10040000 0x5000>;
 714                         clock-names = "clkout16";
 715                         clocks = <&clock CLK_FIN_PLL>;
 716                         #clock-cells = <1>;
 717                         interrupt-controller;
 718                         #interrupt-cells = <3>;
 719                         interrupt-parent = <&gic>;
 720                 };
 721
 722                 tmu_cpu0: tmu@10060000 {
 723                         compatible = "samsung,exynos5420-tmu";
 724                         reg = <0x10060000 0x100>;
 725                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 726                         clocks = <&clock CLK_TMU>;
 727                         clock-names = "tmu_apbif";
 728                         #include "exynos5420-tmu-sensor-conf.dtsi"
 729                 };
 730
 731                 tmu_cpu1: tmu@10064000 {
 732                         compatible = "samsung,exynos5420-tmu";
 733                         reg = <0x10064000 0x100>;
 734                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 735                         clocks = <&clock CLK_TMU>;
 736                         clock-names = "tmu_apbif";
 737                         #include "exynos5420-tmu-sensor-conf.dtsi"
 738                 };
 739
 740                 tmu_cpu2: tmu@10068000 {
 741                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 742                         reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 743                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 745                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 746                         #include "exynos5420-tmu-sensor-conf.dtsi"
 747                 };
 748
 749                 tmu_cpu3: tmu@1006c000 {
 750                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 751                         reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 752                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 753                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 754                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 755                         #include "exynos5420-tmu-sensor-conf.dtsi"
 756                 };
 757
 758                 tmu_gpu: tmu@100a0000 {
 759                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 760                         reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 761                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 762                         clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 763                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 764                         #include "exynos5420-tmu-sensor-conf.dtsi"
 765                 };
 766
 767                 sysmmu_g2dr: sysmmu@0x10A60000 {
 768                         compatible = "samsung,exynos-sysmmu";
 769                         reg = <0x10A60000 0x1000>;
 770                         interrupt-parent = <&combiner>;
 771                         interrupts = <24 5>;
 772                         clock-names = "sysmmu", "master";
 773                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 774                         #iommu-cells = <0>;
 775                 };
 776
 777                 sysmmu_g2dw: sysmmu@0x10A70000 {
 778                         compatible = "samsung,exynos-sysmmu";
 779                         reg = <0x10A70000 0x1000>;
 780                         interrupt-parent = <&combiner>;
 781                         interrupts = <22 2>;
 782                         clock-names = "sysmmu", "master";
 783                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 784                         #iommu-cells = <0>;
 785                 };
 786
 787                 sysmmu_tv: sysmmu@0x14650000 {
 788                         compatible = "samsung,exynos-sysmmu";
 789                         reg = <0x14650000 0x1000>;
 790                         interrupt-parent = <&combiner>;
 791                         interrupts = <7 4>;
 792                         clock-names = "sysmmu", "master";
 793                         clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
 794                         power-domains = <&disp_pd>;
 795                         #iommu-cells = <0>;
 796                 };
 797
 798                 sysmmu_gscl0: sysmmu@0x13E80000 {
 799                         compatible = "samsung,exynos-sysmmu";
 800                         reg = <0x13E80000 0x1000>;
 801                         interrupt-parent = <&combiner>;
 802                         interrupts = <2 0>;
 803                         clock-names = "sysmmu", "master";
 804                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 805                         power-domains = <&gsc_pd>;
 806                         #iommu-cells = <0>;
 807                 };
 808
 809                 sysmmu_gscl1: sysmmu@0x13E90000 {
 810                         compatible = "samsung,exynos-sysmmu";
 811                         reg = <0x13E90000 0x1000>;
 812                         interrupt-parent = <&combiner>;
 813                         interrupts = <2 2>;
 814                         clock-names = "sysmmu", "master";
 815                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 816                         power-domains = <&gsc_pd>;
 817                         #iommu-cells = <0>;
 818                 };
 819
 820                 sysmmu_scaler0r: sysmmu@0x12880000 {
 821                         compatible = "samsung,exynos-sysmmu";
 822                         reg = <0x12880000 0x1000>;
 823                         interrupt-parent = <&combiner>;
 824                         interrupts = <22 4>;
 825                         clock-names = "sysmmu", "master";
 826                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
 827                         #iommu-cells = <0>;
 828                 };
 829
 830                 sysmmu_scaler1r: sysmmu@0x12890000 {
 831                         compatible = "samsung,exynos-sysmmu";
 832                         reg = <0x12890000 0x1000>;
 833                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 834                         clock-names = "sysmmu", "master";
 835                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
 836                         #iommu-cells = <0>;
 837                 };
 838
 839                 sysmmu_scaler2r: sysmmu@0x128A0000 {
 840                         compatible = "samsung,exynos-sysmmu";
 841                         reg = <0x128A0000 0x1000>;
 842                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 843                         clock-names = "sysmmu", "master";
 844                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
 845                         #iommu-cells = <0>;
 846                 };
 847
 848                 sysmmu_scaler0w: sysmmu@0x128C0000 {
 849                         compatible = "samsung,exynos-sysmmu";
 850                         reg = <0x128C0000 0x1000>;
 851                         interrupt-parent = <&combiner>;
 852                         interrupts = <27 2>;
 853                         clock-names = "sysmmu", "master";
 854                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
 855                         #iommu-cells = <0>;
 856                 };
 857
 858                 sysmmu_scaler1w: sysmmu@0x128D0000 {
 859                         compatible = "samsung,exynos-sysmmu";
 860                         reg = <0x128D0000 0x1000>;
 861                         interrupt-parent = <&combiner>;
 862                         interrupts = <22 6>;
 863                         clock-names = "sysmmu", "master";
 864                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
 865                         #iommu-cells = <0>;
 866                 };
 867
 868                 sysmmu_scaler2w: sysmmu@0x128E0000 {
 869                         compatible = "samsung,exynos-sysmmu";
 870                         reg = <0x128E0000 0x1000>;
 871                         interrupt-parent = <&combiner>;
 872                         interrupts = <19 6>;
 873                         clock-names = "sysmmu", "master";
 874                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
 875                         #iommu-cells = <0>;
 876                 };
 877
 878                 sysmmu_rotator: sysmmu@0x11D40000 {
 879                         compatible = "samsung,exynos-sysmmu";
 880                         reg = <0x11D40000 0x1000>;
 881                         interrupt-parent = <&combiner>;
 882                         interrupts = <4 0>;
 883                         clock-names = "sysmmu", "master";
 884                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 885                         #iommu-cells = <0>;
 886                 };
 887
 888                 sysmmu_jpeg0: sysmmu@0x11F10000 {
 889                         compatible = "samsung,exynos-sysmmu";
 890                         reg = <0x11F10000 0x1000>;
 891                         interrupt-parent = <&combiner>;
 892                         interrupts = <4 2>;
 893                         clock-names = "sysmmu", "master";
 894                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 895                         #iommu-cells = <0>;
 896                 };
 897
 898                 sysmmu_jpeg1: sysmmu@0x11F20000 {
 899                         compatible = "samsung,exynos-sysmmu";
 900                         reg = <0x11F20000 0x1000>;
 901                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 902                         clock-names = "sysmmu", "master";
 903                         clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
 904                         #iommu-cells = <0>;
 905                 };
 906
 907                 sysmmu_mfc_l: sysmmu@0x11200000 {
 908                         compatible = "samsung,exynos-sysmmu";
 909                         reg = <0x11200000 0x1000>;
 910                         interrupt-parent = <&combiner>;
 911                         interrupts = <6 2>;
 912                         clock-names = "sysmmu", "master";
 913                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 914                         power-domains = <&mfc_pd>;
 915                         #iommu-cells = <0>;
 916                 };
 917
 918                 sysmmu_mfc_r: sysmmu@0x11210000 {
 919                         compatible = "samsung,exynos-sysmmu";
 920                         reg = <0x11210000 0x1000>;
 921                         interrupt-parent = <&combiner>;
 922                         interrupts = <8 5>;
 923                         clock-names = "sysmmu", "master";
 924                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 925                         power-domains = <&mfc_pd>;
 926                         #iommu-cells = <0>;
 927                 };
 928
 929                 sysmmu_fimd1_0: sysmmu@0x14640000 {
 930                         compatible = "samsung,exynos-sysmmu";
 931                         reg = <0x14640000 0x1000>;
 932                         interrupt-parent = <&combiner>;
 933                         interrupts = <3 2>;
 934                         clock-names = "sysmmu", "master";
 935                         clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
 936                         power-domains = <&disp_pd>;
 937                         #iommu-cells = <0>;
 938                 };
 939
 940                 sysmmu_fimd1_1: sysmmu@0x14680000 {
 941                         compatible = "samsung,exynos-sysmmu";
 942                         reg = <0x14680000 0x1000>;
 943                         interrupt-parent = <&combiner>;
 944                         interrupts = <3 0>;
 945                         clock-names = "sysmmu", "master";
 946                         clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
 947                         power-domains = <&disp_pd>;
 948                         #iommu-cells = <0>;
 949                 };
 950
 951                 bus_wcore: bus_wcore {
 952                         compatible = "samsung,exynos-bus";
 953                         clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
 954                         clock-names = "bus";
 955                         operating-points-v2 = <&bus_wcore_opp_table>;
 956                         status = "disabled";
 957                 };
 958
 959                 bus_noc: bus_noc {
 960                         compatible = "samsung,exynos-bus";
 961                         clocks = <&clock CLK_DOUT_ACLK100_NOC>;
 962                         clock-names = "bus";
 963                         operating-points-v2 = <&bus_noc_opp_table>;
 964                         status = "disabled";
 965                 };
 966
 967                 bus_fsys_apb: bus_fsys_apb {
 968                         compatible = "samsung,exynos-bus";
 969                         clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
 970                         clock-names = "bus";
 971                         operating-points-v2 = <&bus_fsys_apb_opp_table>;
 972                         status = "disabled";
 973                 };
 974
 975                 bus_fsys: bus_fsys {
 976                         compatible = "samsung,exynos-bus";
 977                         clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
 978                         clock-names = "bus";
 979                         operating-points-v2 = <&bus_fsys_apb_opp_table>;
 980                         status = "disabled";
 981                 };
 982
 983                 bus_fsys2: bus_fsys2 {
 984                         compatible = "samsung,exynos-bus";
 985                         clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
 986                         clock-names = "bus";
 987                         operating-points-v2 = <&bus_fsys2_opp_table>;
 988                         status = "disabled";
 989                 };
 990
 991                 bus_mfc: bus_mfc {
 992                         compatible = "samsung,exynos-bus";
 993                         clocks = <&clock CLK_DOUT_ACLK333>;
 994                         clock-names = "bus";
 995                         operating-points-v2 = <&bus_mfc_opp_table>;
 996                         status = "disabled";
 997                 };
 998
 999                 bus_gen: bus_gen {
1000                         compatible = "samsung,exynos-bus";
1001                         clocks = <&clock CLK_DOUT_ACLK266>;
1002                         clock-names = "bus";
1003                         operating-points-v2 = <&bus_gen_opp_table>;
1004                         status = "disabled";
1005                 };
1006
1007                 bus_peri: bus_peri {
1008                         compatible = "samsung,exynos-bus";
1009                         clocks = <&clock CLK_DOUT_ACLK66>;
1010                         clock-names = "bus";
1011                         operating-points-v2 = <&bus_peri_opp_table>;
1012                         status = "disabled";
1013                 };
1014
1015                 bus_g2d: bus_g2d {
1016                         compatible = "samsung,exynos-bus";
1017                         clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1018                         clock-names = "bus";
1019                         operating-points-v2 = <&bus_g2d_opp_table>;
1020                         status = "disabled";
1021                 };
1022
1023                 bus_g2d_acp: bus_g2d_acp {
1024                         compatible = "samsung,exynos-bus";
1025                         clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1026                         clock-names = "bus";
1027                         operating-points-v2 = <&bus_g2d_acp_opp_table>;
1028                         status = "disabled";
1029                 };
1030
1031                 bus_jpeg: bus_jpeg {
1032                         compatible = "samsung,exynos-bus";
1033                         clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1034                         clock-names = "bus";
1035                         operating-points-v2 = <&bus_jpeg_opp_table>;
1036                         status = "disabled";
1037                 };
1038
1039                 bus_jpeg_apb: bus_jpeg_apb {
1040                         compatible = "samsung,exynos-bus";
1041                         clocks = <&clock CLK_DOUT_ACLK166>;
1042                         clock-names = "bus";
1043                         operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1044                         status = "disabled";
1045                 };
1046
1047                 bus_disp1_fimd: bus_disp1_fimd {
1048                         compatible = "samsung,exynos-bus";
1049                         clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1050                         clock-names = "bus";
1051                         operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1052                         status = "disabled";
1053                 };
1054
1055                 bus_disp1: bus_disp1 {
1056                         compatible = "samsung,exynos-bus";
1057                         clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1058                         clock-names = "bus";
1059                         operating-points-v2 = <&bus_disp1_opp_table>;
1060                         status = "disabled";
1061                 };
1062
1063                 bus_gscl_scaler: bus_gscl_scaler {
1064                         compatible = "samsung,exynos-bus";
1065                         clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1066                         clock-names = "bus";
1067                         operating-points-v2 = <&bus_gscl_opp_table>;
1068                         status = "disabled";
1069                 };
1070
1071                 bus_mscl: bus_mscl {
1072                         compatible = "samsung,exynos-bus";
1073                         clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1074                         clock-names = "bus";
1075                         operating-points-v2 = <&bus_mscl_opp_table>;
1076                         status = "disabled";
1077                 };
1078
1079                 bus_wcore_opp_table: opp_table2 {
1080                         compatible = "operating-points-v2";
1081
1082                         opp00 {
1083                                 opp-hz = /bits/ 64 <84000000>;
1084                                 opp-microvolt = <925000>;
1085                         };
1086                         opp01 {
1087                                 opp-hz = /bits/ 64 <111000000>;
1088                                 opp-microvolt = <950000>;
1089                         };
1090                         opp02 {
1091                                 opp-hz = /bits/ 64 <222000000>;
1092                                 opp-microvolt = <950000>;
1093                         };
1094                         opp03 {
1095                                 opp-hz = /bits/ 64 <333000000>;
1096                                 opp-microvolt = <950000>;
1097                         };
1098                         opp04 {
1099                                 opp-hz = /bits/ 64 <400000000>;
1100                                 opp-microvolt = <987500>;
1101                         };
1102                 };
1103
1104                 bus_noc_opp_table: opp_table3 {
1105                         compatible = "operating-points-v2";
1106
1107                         opp00 {
1108                                 opp-hz = /bits/ 64 <67000000>;
1109                         };
1110                         opp01 {
1111                                 opp-hz = /bits/ 64 <75000000>;
1112                         };
1113                         opp02 {
1114                                 opp-hz = /bits/ 64 <86000000>;
1115                         };
1116                         opp03 {
1117                                 opp-hz = /bits/ 64 <100000000>;
1118                         };
1119                 };
1120
1121                 bus_fsys_apb_opp_table: opp_table4 {
1122                         compatible = "operating-points-v2";
1123                         opp-shared;
1124
1125                         opp00 {
1126                                 opp-hz = /bits/ 64 <100000000>;
1127                         };
1128                         opp01 {
1129                                 opp-hz = /bits/ 64 <200000000>;
1130                         };
1131                 };
1132
1133                 bus_fsys2_opp_table: opp_table5 {
1134                         compatible = "operating-points-v2";
1135
1136                         opp00 {
1137                                 opp-hz = /bits/ 64 <75000000>;
1138                         };
1139                         opp01 {
1140                                 opp-hz = /bits/ 64 <100000000>;
1141                         };
1142                         opp02 {
1143                                 opp-hz = /bits/ 64 <150000000>;
1144                         };
1145                 };
1146
1147                 bus_mfc_opp_table: opp_table6 {
1148                         compatible = "operating-points-v2";
1149
1150                         opp00 {
1151                                 opp-hz = /bits/ 64 <96000000>;
1152                         };
1153                         opp01 {
1154                                 opp-hz = /bits/ 64 <111000000>;
1155                         };
1156                         opp02 {
1157                                 opp-hz = /bits/ 64 <167000000>;
1158                         };
1159                         opp03 {
1160                                 opp-hz = /bits/ 64 <222000000>;
1161                         };
1162                         opp04 {
1163                                 opp-hz = /bits/ 64 <333000000>;
1164                         };
1165                 };
1166
1167                 bus_gen_opp_table: opp_table7 {
1168                         compatible = "operating-points-v2";
1169
1170                         opp00 {
1171                                 opp-hz = /bits/ 64 <89000000>;
1172                         };
1173                         opp01 {
1174                                 opp-hz = /bits/ 64 <133000000>;
1175                         };
1176                         opp02 {
1177                                 opp-hz = /bits/ 64 <178000000>;
1178                         };
1179                         opp03 {
1180                                 opp-hz = /bits/ 64 <267000000>;
1181                         };
1182                 };
1183
1184                 bus_peri_opp_table: opp_table8 {
1185                         compatible = "operating-points-v2";
1186
1187                         opp00 {
1188                                 opp-hz = /bits/ 64 <67000000>;
1189                         };
1190                 };
1191
1192                 bus_g2d_opp_table: opp_table9 {
1193                         compatible = "operating-points-v2";
1194
1195                         opp00 {
1196                                 opp-hz = /bits/ 64 <84000000>;
1197                         };
1198                         opp01 {
1199                                 opp-hz = /bits/ 64 <167000000>;
1200                         };
1201                         opp02 {
1202                                 opp-hz = /bits/ 64 <222000000>;
1203                         };
1204                         opp03 {
1205                                 opp-hz = /bits/ 64 <300000000>;
1206                         };
1207                         opp04 {
1208                                 opp-hz = /bits/ 64 <333000000>;
1209                         };
1210                 };
1211
1212                 bus_g2d_acp_opp_table: opp_table10 {
1213                         compatible = "operating-points-v2";
1214
1215                         opp00 {
1216                                 opp-hz = /bits/ 64 <67000000>;
1217                         };
1218                         opp01 {
1219                                 opp-hz = /bits/ 64 <133000000>;
1220                         };
1221                         opp02 {
1222                                 opp-hz = /bits/ 64 <178000000>;
1223                         };
1224                         opp03 {
1225                                 opp-hz = /bits/ 64 <267000000>;
1226                         };
1227                 };
1228
1229                 bus_jpeg_opp_table: opp_table11 {
1230                         compatible = "operating-points-v2";
1231
1232                         opp00 {
1233                                 opp-hz = /bits/ 64 <75000000>;
1234                         };
1235                         opp01 {
1236                                 opp-hz = /bits/ 64 <150000000>;
1237                         };
1238                         opp02 {
1239                                 opp-hz = /bits/ 64 <200000000>;
1240                         };
1241                         opp03 {
1242                                 opp-hz = /bits/ 64 <300000000>;
1243                         };
1244                 };
1245
1246                 bus_jpeg_apb_opp_table: opp_table12 {
1247                         compatible = "operating-points-v2";
1248
1249                         opp00 {
1250                                 opp-hz = /bits/ 64 <84000000>;
1251                         };
1252                         opp01 {
1253                                 opp-hz = /bits/ 64 <111000000>;
1254                         };
1255                         opp02 {
1256                                 opp-hz = /bits/ 64 <134000000>;
1257                         };
1258                         opp03 {
1259                                 opp-hz = /bits/ 64 <167000000>;
1260                         };
1261                 };
1262
1263                 bus_disp1_fimd_opp_table: opp_table13 {
1264                         compatible = "operating-points-v2";
1265
1266                         opp00 {
1267                                 opp-hz = /bits/ 64 <120000000>;
1268                         };
1269                         opp01 {
1270                                 opp-hz = /bits/ 64 <200000000>;
1271                         };
1272                 };
1273
1274                 bus_disp1_opp_table: opp_table14 {
1275                         compatible = "operating-points-v2";
1276
1277                         opp00 {
1278                                 opp-hz = /bits/ 64 <120000000>;
1279                         };
1280                         opp01 {
1281                                 opp-hz = /bits/ 64 <200000000>;
1282                         };
1283                         opp02 {
1284                                 opp-hz = /bits/ 64 <300000000>;
1285                         };
1286                 };
1287
1288                 bus_gscl_opp_table: opp_table15 {
1289                         compatible = "operating-points-v2";
1290
1291                         opp00 {
1292                                 opp-hz = /bits/ 64 <150000000>;
1293                         };
1294                         opp01 {
1295                                 opp-hz = /bits/ 64 <200000000>;
1296                         };
1297                         opp02 {
1298                                 opp-hz = /bits/ 64 <300000000>;
1299                         };
1300                 };
1301
1302                 bus_mscl_opp_table: opp_table16 {
1303                         compatible = "operating-points-v2";
1304
1305                         opp00 {
1306                                 opp-hz = /bits/ 64 <84000000>;
1307                         };
1308                         opp01 {
1309                                 opp-hz = /bits/ 64 <167000000>;
1310                         };
1311                         opp02 {
1312                                 opp-hz = /bits/ 64 <222000000>;
1313                         };
1314                         opp03 {
1315                                 opp-hz = /bits/ 64 <333000000>;
1316                         };
1317                         opp04 {
1318                                 opp-hz = /bits/ 64 <400000000>;
1319                         };
1320                 };
1321         };
1322
1323         thermal-zones {
1324                 cpu0_thermal: cpu0-thermal {
1325                         thermal-sensors = <&tmu_cpu0>;
1326                         #include "exynos5420-trip-points.dtsi"
1327                 };
1328                 cpu1_thermal: cpu1-thermal {
1329                        thermal-sensors = <&tmu_cpu1>;
1330                        #include "exynos5420-trip-points.dtsi"
1331                 };
1332                 cpu2_thermal: cpu2-thermal {
1333                        thermal-sensors = <&tmu_cpu2>;
1334                        #include "exynos5420-trip-points.dtsi"
1335                 };
1336                 cpu3_thermal: cpu3-thermal {
1337                        thermal-sensors = <&tmu_cpu3>;
1338                        #include "exynos5420-trip-points.dtsi"
1339                 };
1340                 gpu_thermal: gpu-thermal {
1341                        thermal-sensors = <&tmu_gpu>;
1342                        #include "exynos5420-trip-points.dtsi"
1343                 };
1344         };
1345 };
1346
1347 &dp {
1348         clocks = <&clock CLK_DP1>;
1349         clock-names = "dp";
1350         phys = <&dp_phy>;
1351         phy-names = "dp";
1352         power-domains = <&disp_pd>;
1353 };
1354
1355 &fimd {
1356         compatible = "samsung,exynos5420-fimd";
1357         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1358         clock-names = "sclk_fimd", "fimd";
1359         power-domains = <&disp_pd>;
1360         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1361         iommu-names = "m0", "m1";
1362 };
1363
1364 &g2d {
1365         iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1366         clocks = <&clock CLK_G2D>;
1367         clock-names = "fimg2d";
1368         status = "okay";
1369 };
1370
1371 &i2c_0 {
1372         clocks = <&clock CLK_I2C0>;
1373         clock-names = "i2c";
1374         pinctrl-names = "default";
1375         pinctrl-0 = <&i2c0_bus>;
1376 };
1377
1378 &i2c_1 {
1379         clocks = <&clock CLK_I2C1>;
1380         clock-names = "i2c";
1381         pinctrl-names = "default";
1382         pinctrl-0 = <&i2c1_bus>;
1383 };
1384
1385 &i2c_2 {
1386         clocks = <&clock CLK_I2C2>;
1387         clock-names = "i2c";
1388         pinctrl-names = "default";
1389         pinctrl-0 = <&i2c2_bus>;
1390 };
1391
1392 &i2c_3 {
1393         clocks = <&clock CLK_I2C3>;
1394         clock-names = "i2c";
1395         pinctrl-names = "default";
1396         pinctrl-0 = <&i2c3_bus>;
1397 };
1398
1399 &hsi2c_4 {
1400         clocks = <&clock CLK_USI0>;
1401         clock-names = "hsi2c";
1402         pinctrl-names = "default";
1403         pinctrl-0 = <&i2c4_hs_bus>;
1404 };
1405
1406 &hsi2c_5 {
1407         clocks = <&clock CLK_USI1>;
1408         clock-names = "hsi2c";
1409         pinctrl-names = "default";
1410         pinctrl-0 = <&i2c5_hs_bus>;
1411 };
1412
1413 &hsi2c_6 {
1414         clocks = <&clock CLK_USI2>;
1415         clock-names = "hsi2c";
1416         pinctrl-names = "default";
1417         pinctrl-0 = <&i2c6_hs_bus>;
1418 };
1419
1420 &hsi2c_7 {
1421         clocks = <&clock CLK_USI3>;
1422         clock-names = "hsi2c";
1423         pinctrl-names = "default";
1424         pinctrl-0 = <&i2c7_hs_bus>;
1425 };
1426
1427 &mct {
1428         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1429         clock-names = "fin_pll", "mct";
1430 };
1431
1432 &prng {
1433         clocks = <&clock CLK_SSS>;
1434         clock-names = "secss";
1435 };
1436
1437 &pwm {
1438         clocks = <&clock CLK_PWM>;
1439         clock-names = "timers";
1440 };
1441
1442 &rtc {
1443         clocks = <&clock CLK_RTC>;
1444         clock-names = "rtc";
1445         interrupt-parent = <&pmu_system_controller>;
1446         status = "disabled";
1447 };
1448
1449 &serial_0 {
1450         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1451         clock-names = "uart", "clk_uart_baud0";
1452         dmas = <&pdma0 13>, <&pdma0 14>;
1453         dma-names = "rx", "tx";
1454 };
1455
1456 &serial_1 {
1457         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1458         clock-names = "uart", "clk_uart_baud0";
1459         dmas = <&pdma1 15>, <&pdma1 16>;
1460         dma-names = "rx", "tx";
1461 };
1462
1463 &serial_2 {
1464         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1465         clock-names = "uart", "clk_uart_baud0";
1466         dmas = <&pdma0 15>, <&pdma0 16>;
1467         dma-names = "rx", "tx";
1468 };
1469
1470 &serial_3 {
1471         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1472         clock-names = "uart", "clk_uart_baud0";
1473         dmas = <&pdma1 17>, <&pdma1 18>;
1474         dma-names = "rx", "tx";
1475 };
1476
1477 &sss {
1478         clocks = <&clock CLK_SSS>;
1479         clock-names = "secss";
1480 };
1481
1482 &usbdrd3_0 {
1483         clocks = <&clock CLK_USBD300>;
1484         clock-names = "usbdrd30";
1485 };
1486
1487 &usbdrd_phy0 {
1488         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1489         clock-names = "phy", "ref";
1490         samsung,pmu-syscon = <&pmu_system_controller>;
1491 };
1492
1493 &usbdrd3_1 {
1494         clocks = <&clock CLK_USBD301>;
1495         clock-names = "usbdrd30";
1496 };
1497
1498 &usbdrd_dwc3_1 {
1499         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1500 };
1501
1502 &usbdrd_phy1 {
1503         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1504         clock-names = "phy", "ref";
1505         samsung,pmu-syscon = <&pmu_system_controller>;
1506 };
1507
1508 &usbhost1 {
1509         clocks = <&clock CLK_USBH20>;
1510         clock-names = "usbhost";
1511 };
1512
1513 &usbhost2 {
1514         clocks = <&clock CLK_USBH20>;
1515         clock-names = "usbhost";
1516 };
1517
1518 &usb2_phy {
1519         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1520         clock-names = "phy", "ref";
1521         samsung,sysreg-phandle = <&sysreg_system_controller>;
1522         samsung,pmureg-phandle = <&pmu_system_controller>;
1523 };
1524
1525 &watchdog {
1526         clocks = <&clock CLK_WDT>;
1527         clock-names = "watchdog";
1528         samsung,syscon-phandle = <&pmu_system_controller>;
1529 };
1530
1531 #include "exynos5420-pinctrl.dtsi"