arch/arm/boot/dts/exynos5420.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS5420 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   9  * EXYNOS5420 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  */
  12
  13 #include "exynos54xx.dtsi"
  14 #include <dt-bindings/clock/exynos5420.h>
  15 #include <dt-bindings/clock/exynos-audss-clk.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         compatible = "samsung,exynos5420", "samsung,exynos5";
  20
  21         aliases {
  22                 mshc0 = &mmc_0;
  23                 mshc1 = &mmc_1;
  24                 mshc2 = &mmc_2;
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 pinctrl4 = &pinctrl_4;
  30                 i2c8 = &hsi2c_8;
  31                 i2c9 = &hsi2c_9;
  32                 i2c10 = &hsi2c_10;
  33                 gsc0 = &gsc_0;
  34                 gsc1 = &gsc_1;
  35                 spi0 = &spi_0;
  36                 spi1 = &spi_1;
  37                 spi2 = &spi_2;
  38         };
  39
  40         /*
  41          * The 'cpus' node is not present here but instead it is provided
  42          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
  43          */
  44
  45         soc: soc {
  46                 cluster_a15_opp_table: opp_table0 {
  47                         compatible = "operating-points-v2";
  48                         opp-shared;
  49                         opp-1800000000 {
  50                                 opp-hz = /bits/ 64 <1800000000>;
  51                                 opp-microvolt = <1250000>;
  52                                 clock-latency-ns = <140000>;
  53                         };
  54                         opp-1700000000 {
  55                                 opp-hz = /bits/ 64 <1700000000>;
  56                                 opp-microvolt = <1212500>;
  57                                 clock-latency-ns = <140000>;
  58                         };
  59                         opp-1600000000 {
  60                                 opp-hz = /bits/ 64 <1600000000>;
  61                                 opp-microvolt = <1175000>;
  62                                 clock-latency-ns = <140000>;
  63                         };
  64                         opp-1500000000 {
  65                                 opp-hz = /bits/ 64 <1500000000>;
  66                                 opp-microvolt = <1137500>;
  67                                 clock-latency-ns = <140000>;
  68                         };
  69                         opp-1400000000 {
  70                                 opp-hz = /bits/ 64 <1400000000>;
  71                                 opp-microvolt = <1112500>;
  72                                 clock-latency-ns = <140000>;
  73                         };
  74                         opp-1300000000 {
  75                                 opp-hz = /bits/ 64 <1300000000>;
  76                                 opp-microvolt = <1062500>;
  77                                 clock-latency-ns = <140000>;
  78                         };
  79                         opp-1200000000 {
  80                                 opp-hz = /bits/ 64 <1200000000>;
  81                                 opp-microvolt = <1037500>;
  82                                 clock-latency-ns = <140000>;
  83                         };
  84                         opp-1100000000 {
  85                                 opp-hz = /bits/ 64 <1100000000>;
  86                                 opp-microvolt = <1012500>;
  87                                 clock-latency-ns = <140000>;
  88                         };
  89                         opp-1000000000 {
  90                                 opp-hz = /bits/ 64 <1000000000>;
  91                                 opp-microvolt = < 987500>;
  92                                 clock-latency-ns = <140000>;
  93                         };
  94                         opp-900000000 {
  95                                 opp-hz = /bits/ 64 <900000000>;
  96                                 opp-microvolt = < 962500>;
  97                                 clock-latency-ns = <140000>;
  98                         };
  99                         opp-800000000 {
 100                                 opp-hz = /bits/ 64 <800000000>;
 101                                 opp-microvolt = < 937500>;
 102                                 clock-latency-ns = <140000>;
 103                         };
 104                         opp-700000000 {
 105                                 opp-hz = /bits/ 64 <700000000>;
 106                                 opp-microvolt = < 912500>;
 107                                 clock-latency-ns = <140000>;
 108                         };
 109                 };
 110
 111                 cluster_a7_opp_table: opp_table1 {
 112                         compatible = "operating-points-v2";
 113                         opp-shared;
 114                         opp-1300000000 {
 115                                 opp-hz = /bits/ 64 <1300000000>;
 116                                 opp-microvolt = <1275000>;
 117                                 clock-latency-ns = <140000>;
 118                         };
 119                         opp-1200000000 {
 120                                 opp-hz = /bits/ 64 <1200000000>;
 121                                 opp-microvolt = <1212500>;
 122                                 clock-latency-ns = <140000>;
 123                         };
 124                         opp-1100000000 {
 125                                 opp-hz = /bits/ 64 <1100000000>;
 126                                 opp-microvolt = <1162500>;
 127                                 clock-latency-ns = <140000>;
 128                         };
 129                         opp-1000000000 {
 130                                 opp-hz = /bits/ 64 <1000000000>;
 131                                 opp-microvolt = <1112500>;
 132                                 clock-latency-ns = <140000>;
 133                         };
 134                         opp-900000000 {
 135                                 opp-hz = /bits/ 64 <900000000>;
 136                                 opp-microvolt = <1062500>;
 137                                 clock-latency-ns = <140000>;
 138                         };
 139                         opp-800000000 {
 140                                 opp-hz = /bits/ 64 <800000000>;
 141                                 opp-microvolt = <1025000>;
 142                                 clock-latency-ns = <140000>;
 143                         };
 144                         opp-700000000 {
 145                                 opp-hz = /bits/ 64 <700000000>;
 146                                 opp-microvolt = <975000>;
 147                                 clock-latency-ns = <140000>;
 148                         };
 149                         opp-600000000 {
 150                                 opp-hz = /bits/ 64 <600000000>;
 151                                 opp-microvolt = <937500>;
 152                                 clock-latency-ns = <140000>;
 153                         };
 154                 };
 155
 156                 cci: cci@10d20000 {
 157                         compatible = "arm,cci-400";
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         reg = <0x10d20000 0x1000>;
 161                         ranges = <0x0 0x10d20000 0x6000>;
 162
 163                         cci_control0: slave-if@4000 {
 164                                 compatible = "arm,cci-400-ctrl-if";
 165                                 interface-type = "ace";
 166                                 reg = <0x4000 0x1000>;
 167                         };
 168                         cci_control1: slave-if@5000 {
 169                                 compatible = "arm,cci-400-ctrl-if";
 170                                 interface-type = "ace";
 171                                 reg = <0x5000 0x1000>;
 172                         };
 173                 };
 174
 175                 clock: clock-controller@10010000 {
 176                         compatible = "samsung,exynos5420-clock";
 177                         reg = <0x10010000 0x30000>;
 178                         #clock-cells = <1>;
 179                 };
 180
 181                 clock_audss: audss-clock-controller@3810000 {
 182                         compatible = "samsung,exynos5420-audss-clock";
 183                         reg = <0x03810000 0x0C>;
 184                         #clock-cells = <1>;
 185                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 186                                  <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 187                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 188                         power-domains = <&mau_pd>;
 189                 };
 190
 191                 mfc: codec@11000000 {
 192                         compatible = "samsung,mfc-v7";
 193                         reg = <0x11000000 0x10000>;
 194                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 195                         clocks = <&clock CLK_MFC>;
 196                         clock-names = "mfc";
 197                         power-domains = <&mfc_pd>;
 198                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 199                         iommu-names = "left", "right";
 200                 };
 201
 202                 mmc_0: mmc@12200000 {
 203                         compatible = "samsung,exynos5420-dw-mshc-smu";
 204                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         reg = <0x12200000 0x2000>;
 208                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 209                         clock-names = "biu", "ciu";
 210                         fifo-depth = <0x40>;
 211                         status = "disabled";
 212                 };
 213
 214                 mmc_1: mmc@12210000 {
 215                         compatible = "samsung,exynos5420-dw-mshc-smu";
 216                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         reg = <0x12210000 0x2000>;
 220                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 221                         clock-names = "biu", "ciu";
 222                         fifo-depth = <0x40>;
 223                         status = "disabled";
 224                 };
 225
 226                 mmc_2: mmc@12220000 {
 227                         compatible = "samsung,exynos5420-dw-mshc";
 228                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         reg = <0x12220000 0x1000>;
 232                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 233                         clock-names = "biu", "ciu";
 234                         fifo-depth = <0x40>;
 235                         status = "disabled";
 236                 };
 237
 238                 nocp_mem0_0: nocp@10ca1000 {
 239                         compatible = "samsung,exynos5420-nocp";
 240                         reg = <0x10CA1000 0x200>;
 241                         status = "disabled";
 242                 };
 243
 244                 nocp_mem0_1: nocp@10ca1400 {
 245                         compatible = "samsung,exynos5420-nocp";
 246                         reg = <0x10CA1400 0x200>;
 247                         status = "disabled";
 248                 };
 249
 250                 nocp_mem1_0: nocp@10ca1800 {
 251                         compatible = "samsung,exynos5420-nocp";
 252                         reg = <0x10CA1800 0x200>;
 253                         status = "disabled";
 254                 };
 255
 256                 nocp_mem1_1: nocp@10ca1c00 {
 257                         compatible = "samsung,exynos5420-nocp";
 258                         reg = <0x10CA1C00 0x200>;
 259                         status = "disabled";
 260                 };
 261
 262                 nocp_g3d_0: nocp@11a51000 {
 263                         compatible = "samsung,exynos5420-nocp";
 264                         reg = <0x11A51000 0x200>;
 265                         status = "disabled";
 266                 };
 267
 268                 nocp_g3d_1: nocp@11a51400 {
 269                         compatible = "samsung,exynos5420-nocp";
 270                         reg = <0x11A51400 0x200>;
 271                         status = "disabled";
 272                 };
 273
 274                 gsc_pd: power-domain@10044000 {
 275                         compatible = "samsung,exynos4210-pd";
 276                         reg = <0x10044000 0x20>;
 277                         #power-domain-cells = <0>;
 278                         label = "GSC";
 279                 };
 280
 281                 isp_pd: power-domain@10044020 {
 282                         compatible = "samsung,exynos4210-pd";
 283                         reg = <0x10044020 0x20>;
 284                         #power-domain-cells = <0>;
 285                         label = "ISP";
 286                 };
 287
 288                 mfc_pd: power-domain@10044060 {
 289                         compatible = "samsung,exynos4210-pd";
 290                         reg = <0x10044060 0x20>;
 291                         #power-domain-cells = <0>;
 292                         label = "MFC";
 293                 };
 294
 295                 msc_pd: power-domain@10044120 {
 296                         compatible = "samsung,exynos4210-pd";
 297                         reg = <0x10044120 0x20>;
 298                         #power-domain-cells = <0>;
 299                         label = "MSC";
 300                 };
 301
 302                 disp_pd: power-domain@100440c0 {
 303                         compatible = "samsung,exynos4210-pd";
 304                         reg = <0x100440C0 0x20>;
 305                         #power-domain-cells = <0>;
 306                         label = "DISP";
 307                 };
 308
 309                 mau_pd: power-domain@100440e0 {
 310                         compatible = "samsung,exynos4210-pd";
 311                         reg = <0x100440E0 0x20>;
 312                         #power-domain-cells = <0>;
 313                         label = "MAU";
 314                 };
 315
 316                 pinctrl_0: pinctrl@13400000 {
 317                         compatible = "samsung,exynos5420-pinctrl";
 318                         reg = <0x13400000 0x1000>;
 319                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 320
 321                         wakeup-interrupt-controller {
 322                                 compatible = "samsung,exynos4210-wakeup-eint";
 323                                 interrupt-parent = <&gic>;
 324                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 325                         };
 326                 };
 327
 328                 pinctrl_1: pinctrl@13410000 {
 329                         compatible = "samsung,exynos5420-pinctrl";
 330                         reg = <0x13410000 0x1000>;
 331                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 332                 };
 333
 334                 pinctrl_2: pinctrl@14000000 {
 335                         compatible = "samsung,exynos5420-pinctrl";
 336                         reg = <0x14000000 0x1000>;
 337                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 338                 };
 339
 340                 pinctrl_3: pinctrl@14010000 {
 341                         compatible = "samsung,exynos5420-pinctrl";
 342                         reg = <0x14010000 0x1000>;
 343                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 344                 };
 345
 346                 pinctrl_4: pinctrl@3860000 {
 347                         compatible = "samsung,exynos5420-pinctrl";
 348                         reg = <0x03860000 0x1000>;
 349                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 350                         power-domains = <&mau_pd>;
 351                 };
 352
 353                 amba {
 354                         #address-cells = <1>;
 355                         #size-cells = <1>;
 356                         compatible = "simple-bus";
 357                         interrupt-parent = <&gic>;
 358                         ranges;
 359
 360                         adma: adma@3880000 {
 361                                 compatible = "arm,pl330", "arm,primecell";
 362                                 reg = <0x03880000 0x1000>;
 363                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 364                                 clocks = <&clock_audss EXYNOS_ADMA>;
 365                                 clock-names = "apb_pclk";
 366                                 #dma-cells = <1>;
 367                                 #dma-channels = <6>;
 368                                 #dma-requests = <16>;
 369                                 power-domains = <&mau_pd>;
 370                         };
 371
 372                         pdma0: pdma@121a0000 {
 373                                 compatible = "arm,pl330", "arm,primecell";
 374                                 reg = <0x121A0000 0x1000>;
 375                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clock CLK_PDMA0>;
 377                                 clock-names = "apb_pclk";
 378                                 #dma-cells = <1>;
 379                                 #dma-channels = <8>;
 380                                 #dma-requests = <32>;
 381                         };
 382
 383                         pdma1: pdma@121b0000 {
 384                                 compatible = "arm,pl330", "arm,primecell";
 385                                 reg = <0x121B0000 0x1000>;
 386                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&clock CLK_PDMA1>;
 388                                 clock-names = "apb_pclk";
 389                                 #dma-cells = <1>;
 390                                 #dma-channels = <8>;
 391                                 #dma-requests = <32>;
 392                         };
 393
 394                         mdma0: mdma@10800000 {
 395                                 compatible = "arm,pl330", "arm,primecell";
 396                                 reg = <0x10800000 0x1000>;
 397                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 398                                 clocks = <&clock CLK_MDMA0>;
 399                                 clock-names = "apb_pclk";
 400                                 #dma-cells = <1>;
 401                                 #dma-channels = <8>;
 402                                 #dma-requests = <1>;
 403                         };
 404
 405                         mdma1: mdma@11c10000 {
 406                                 compatible = "arm,pl330", "arm,primecell";
 407                                 reg = <0x11C10000 0x1000>;
 408                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 409                                 clocks = <&clock CLK_MDMA1>;
 410                                 clock-names = "apb_pclk";
 411                                 #dma-cells = <1>;
 412                                 #dma-channels = <8>;
 413                                 #dma-requests = <1>;
 414                                 /*
 415                                  * MDMA1 can support both secure and non-secure
 416                                  * AXI transactions. When this is enabled in
 417                                  * the kernel for boards that run in secure
 418                                  * mode, we are getting imprecise external
 419                                  * aborts causing the kernel to oops.
 420                                  */
 421                                 status = "disabled";
 422                         };
 423                 };
 424
 425                 i2s0: i2s@3830000 {
 426                         compatible = "samsung,exynos5420-i2s";
 427                         reg = <0x03830000 0x100>;
 428                         dmas = <&adma 0
 429                                 &adma 2
 430                                 &adma 1>;
 431                         dma-names = "tx", "rx", "tx-sec";
 432                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 433                                 <&clock_audss EXYNOS_I2S_BUS>,
 434                                 <&clock_audss EXYNOS_SCLK_I2S>;
 435                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 436                         #clock-cells = <1>;
 437                         clock-output-names = "i2s_cdclk0";
 438                         #sound-dai-cells = <1>;
 439                         samsung,idma-addr = <0x03000000>;
 440                         pinctrl-names = "default";
 441                         pinctrl-0 = <&i2s0_bus>;
 442                         power-domains = <&mau_pd>;
 443                         status = "disabled";
 444                 };
 445
 446                 i2s1: i2s@12d60000 {
 447                         compatible = "samsung,exynos5420-i2s";
 448                         reg = <0x12D60000 0x100>;
 449                         dmas = <&pdma1 12
 450                                 &pdma1 11>;
 451                         dma-names = "tx", "rx";
 452                         clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 453                         clock-names = "iis", "i2s_opclk0";
 454                         #clock-cells = <1>;
 455                         clock-output-names = "i2s_cdclk1";
 456                         #sound-dai-cells = <1>;
 457                         pinctrl-names = "default";
 458                         pinctrl-0 = <&i2s1_bus>;
 459                         status = "disabled";
 460                 };
 461
 462                 i2s2: i2s@12d70000 {
 463                         compatible = "samsung,exynos5420-i2s";
 464                         reg = <0x12D70000 0x100>;
 465                         dmas = <&pdma0 12
 466                                 &pdma0 11>;
 467                         dma-names = "tx", "rx";
 468                         clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 469                         clock-names = "iis", "i2s_opclk0";
 470                         #clock-cells = <1>;
 471                         clock-output-names = "i2s_cdclk2";
 472                         #sound-dai-cells = <1>;
 473                         pinctrl-names = "default";
 474                         pinctrl-0 = <&i2s2_bus>;
 475                         status = "disabled";
 476                 };
 477
 478                 spi_0: spi@12d20000 {
 479                         compatible = "samsung,exynos4210-spi";
 480                         reg = <0x12d20000 0x100>;
 481                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 482                         dmas = <&pdma0 5
 483                                 &pdma0 4>;
 484                         dma-names = "tx", "rx";
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                         pinctrl-names = "default";
 488                         pinctrl-0 = <&spi0_bus>;
 489                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 490                         clock-names = "spi", "spi_busclk0";
 491                         status = "disabled";
 492                 };
 493
 494                 spi_1: spi@12d30000 {
 495                         compatible = "samsung,exynos4210-spi";
 496                         reg = <0x12d30000 0x100>;
 497                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 498                         dmas = <&pdma1 5
 499                                 &pdma1 4>;
 500                         dma-names = "tx", "rx";
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         pinctrl-names = "default";
 504                         pinctrl-0 = <&spi1_bus>;
 505                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 506                         clock-names = "spi", "spi_busclk0";
 507                         status = "disabled";
 508                 };
 509
 510                 spi_2: spi@12d40000 {
 511                         compatible = "samsung,exynos4210-spi";
 512                         reg = <0x12d40000 0x100>;
 513                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 514                         dmas = <&pdma0 7
 515                                 &pdma0 6>;
 516                         dma-names = "tx", "rx";
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                         pinctrl-names = "default";
 520                         pinctrl-0 = <&spi2_bus>;
 521                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 522                         clock-names = "spi", "spi_busclk0";
 523                         status = "disabled";
 524                 };
 525
 526                 dp_phy: dp-video-phy {
 527                         compatible = "samsung,exynos5420-dp-video-phy";
 528                         samsung,pmu-syscon = <&pmu_system_controller>;
 529                         #phy-cells = <0>;
 530                 };
 531
 532                 mipi_phy: mipi-video-phy {
 533                         compatible = "samsung,s5pv210-mipi-video-phy";
 534                         syscon = <&pmu_system_controller>;
 535                         #phy-cells = <1>;
 536                 };
 537
 538                 dsi@14500000 {
 539                         compatible = "samsung,exynos5410-mipi-dsi";
 540                         reg = <0x14500000 0x10000>;
 541                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 542                         phys = <&mipi_phy 1>;
 543                         phy-names = "dsim";
 544                         clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 545                         clock-names = "bus_clk", "pll_clk";
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         status = "disabled";
 549                 };
 550
 551                 adc: adc@12d10000 {
 552                         compatible = "samsung,exynos-adc-v2";
 553                         reg = <0x12D10000 0x100>;
 554                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&clock CLK_TSADC>;
 556                         clock-names = "adc";
 557                         #io-channel-cells = <1>;
 558                         io-channel-ranges;
 559                         samsung,syscon-phandle = <&pmu_system_controller>;
 560                         status = "disabled";
 561                 };
 562
 563                 hsi2c_8: i2c@12e00000 {
 564                         compatible = "samsung,exynos5250-hsi2c";
 565                         reg = <0x12E00000 0x1000>;
 566                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         pinctrl-names = "default";
 570                         pinctrl-0 = <&i2c8_hs_bus>;
 571                         clocks = <&clock CLK_USI4>;
 572                         clock-names = "hsi2c";
 573                         status = "disabled";
 574                 };
 575
 576                 hsi2c_9: i2c@12e10000 {
 577                         compatible = "samsung,exynos5250-hsi2c";
 578                         reg = <0x12E10000 0x1000>;
 579                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         pinctrl-names = "default";
 583                         pinctrl-0 = <&i2c9_hs_bus>;
 584                         clocks = <&clock CLK_USI5>;
 585                         clock-names = "hsi2c";
 586                         status = "disabled";
 587                 };
 588
 589                 hsi2c_10: i2c@12e20000 {
 590                         compatible = "samsung,exynos5250-hsi2c";
 591                         reg = <0x12E20000 0x1000>;
 592                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         pinctrl-names = "default";
 596                         pinctrl-0 = <&i2c10_hs_bus>;
 597                         clocks = <&clock CLK_USI6>;
 598                         clock-names = "hsi2c";
 599                         status = "disabled";
 600                 };
 601
 602                 hdmi: hdmi@14530000 {
 603                         compatible = "samsung,exynos5420-hdmi";
 604                         reg = <0x14530000 0x70000>;
 605                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 607                                  <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 608                                  <&clock CLK_MOUT_HDMI>;
 609                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 610                                 "sclk_hdmiphy", "mout_hdmi";
 611                         phy = <&hdmiphy>;
 612                         samsung,syscon-phandle = <&pmu_system_controller>;
 613                         status = "disabled";
 614                         power-domains = <&disp_pd>;
 615                         #sound-dai-cells = <0>;
 616                 };
 617
 618                 hdmiphy: hdmiphy@145d0000 {
 619                         reg = <0x145D0000 0x20>;
 620                 };
 621
 622                 hdmicec: cec@101b0000 {
 623                         compatible = "samsung,s5p-cec";
 624                         reg = <0x101B0000 0x200>;
 625                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 626                         clocks = <&clock CLK_HDMI_CEC>;
 627                         clock-names = "hdmicec";
 628                         samsung,syscon-phandle = <&pmu_system_controller>;
 629                         hdmi-phandle = <&hdmi>;
 630                         pinctrl-names = "default";
 631                         pinctrl-0 = <&hdmi_cec>;
 632                         status = "disabled";
 633                 };
 634
 635                 mixer: mixer@14450000 {
 636                         compatible = "samsung,exynos5420-mixer";
 637                         reg = <0x14450000 0x10000>;
 638                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 639                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 640                                  <&clock CLK_SCLK_HDMI>;
 641                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 642                         power-domains = <&disp_pd>;
 643                         iommus = <&sysmmu_tv>;
 644                         status = "disabled";
 645                 };
 646
 647                 rotator: rotator@11c00000 {
 648                         compatible = "samsung,exynos5250-rotator";
 649                         reg = <0x11C00000 0x64>;
 650                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 651                         clocks = <&clock CLK_ROTATOR>;
 652                         clock-names = "rotator";
 653                         iommus = <&sysmmu_rotator>;
 654                 };
 655
 656                 gsc_0: video-scaler@13e00000 {
 657                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 658                         reg = <0x13e00000 0x1000>;
 659                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&clock CLK_GSCL0>;
 661                         clock-names = "gscl";
 662                         power-domains = <&gsc_pd>;
 663                         iommus = <&sysmmu_gscl0>;
 664                 };
 665
 666                 gsc_1: video-scaler@13e10000 {
 667                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 668                         reg = <0x13e10000 0x1000>;
 669                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 670                         clocks = <&clock CLK_GSCL1>;
 671                         clock-names = "gscl";
 672                         power-domains = <&gsc_pd>;
 673                         iommus = <&sysmmu_gscl1>;
 674                 };
 675
 676                 jpeg_0: jpeg@11f50000 {
 677                         compatible = "samsung,exynos5420-jpeg";
 678                         reg = <0x11F50000 0x1000>;
 679                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 680                         clock-names = "jpeg";
 681                         clocks = <&clock CLK_JPEG>;
 682                         iommus = <&sysmmu_jpeg0>;
 683                 };
 684
 685                 jpeg_1: jpeg@11f60000 {
 686                         compatible = "samsung,exynos5420-jpeg";
 687                         reg = <0x11F60000 0x1000>;
 688                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 689                         clock-names = "jpeg";
 690                         clocks = <&clock CLK_JPEG2>;
 691                         iommus = <&sysmmu_jpeg1>;
 692                 };
 693
 694                 pmu_system_controller: system-controller@10040000 {
 695                         compatible = "samsung,exynos5420-pmu", "syscon";
 696                         reg = <0x10040000 0x5000>;
 697                         clock-names = "clkout16";
 698                         clocks = <&clock CLK_FIN_PLL>;
 699                         #clock-cells = <1>;
 700                         interrupt-controller;
 701                         #interrupt-cells = <3>;
 702                         interrupt-parent = <&gic>;
 703                 };
 704
 705                 tmu_cpu0: tmu@10060000 {
 706                         compatible = "samsung,exynos5420-tmu";
 707                         reg = <0x10060000 0x100>;
 708                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&clock CLK_TMU>;
 710                         clock-names = "tmu_apbif";
 711                         #include "exynos5420-tmu-sensor-conf.dtsi"
 712                 };
 713
 714                 tmu_cpu1: tmu@10064000 {
 715                         compatible = "samsung,exynos5420-tmu";
 716                         reg = <0x10064000 0x100>;
 717                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 718                         clocks = <&clock CLK_TMU>;
 719                         clock-names = "tmu_apbif";
 720                         #include "exynos5420-tmu-sensor-conf.dtsi"
 721                 };
 722
 723                 tmu_cpu2: tmu@10068000 {
 724                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 725                         reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 726                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 727                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 728                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 729                         #include "exynos5420-tmu-sensor-conf.dtsi"
 730                 };
 731
 732                 tmu_cpu3: tmu@1006c000 {
 733                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 734                         reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 735                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 736                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 737                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 738                         #include "exynos5420-tmu-sensor-conf.dtsi"
 739                 };
 740
 741                 tmu_gpu: tmu@100a0000 {
 742                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 743                         reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 744                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 745                         clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 746                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 747                         #include "exynos5420-tmu-sensor-conf.dtsi"
 748                 };
 749
 750                 sysmmu_g2dr: sysmmu@0x10A60000 {
 751                         compatible = "samsung,exynos-sysmmu";
 752                         reg = <0x10A60000 0x1000>;
 753                         interrupt-parent = <&combiner>;
 754                         interrupts = <24 5>;
 755                         clock-names = "sysmmu", "master";
 756                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 757                         #iommu-cells = <0>;
 758                 };
 759
 760                 sysmmu_g2dw: sysmmu@0x10A70000 {
 761                         compatible = "samsung,exynos-sysmmu";
 762                         reg = <0x10A70000 0x1000>;
 763                         interrupt-parent = <&combiner>;
 764                         interrupts = <22 2>;
 765                         clock-names = "sysmmu", "master";
 766                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 767                         #iommu-cells = <0>;
 768                 };
 769
 770                 sysmmu_tv: sysmmu@0x14650000 {
 771                         compatible = "samsung,exynos-sysmmu";
 772                         reg = <0x14650000 0x1000>;
 773                         interrupt-parent = <&combiner>;
 774                         interrupts = <7 4>;
 775                         clock-names = "sysmmu", "master";
 776                         clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
 777                         power-domains = <&disp_pd>;
 778                         #iommu-cells = <0>;
 779                 };
 780
 781                 sysmmu_gscl0: sysmmu@0x13E80000 {
 782                         compatible = "samsung,exynos-sysmmu";
 783                         reg = <0x13E80000 0x1000>;
 784                         interrupt-parent = <&combiner>;
 785                         interrupts = <2 0>;
 786                         clock-names = "sysmmu", "master";
 787                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 788                         power-domains = <&gsc_pd>;
 789                         #iommu-cells = <0>;
 790                 };
 791
 792                 sysmmu_gscl1: sysmmu@0x13E90000 {
 793                         compatible = "samsung,exynos-sysmmu";
 794                         reg = <0x13E90000 0x1000>;
 795                         interrupt-parent = <&combiner>;
 796                         interrupts = <2 2>;
 797                         clock-names = "sysmmu", "master";
 798                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 799                         power-domains = <&gsc_pd>;
 800                         #iommu-cells = <0>;
 801                 };
 802
 803                 sysmmu_scaler0r: sysmmu@0x12880000 {
 804                         compatible = "samsung,exynos-sysmmu";
 805                         reg = <0x12880000 0x1000>;
 806                         interrupt-parent = <&combiner>;
 807                         interrupts = <22 4>;
 808                         clock-names = "sysmmu", "master";
 809                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
 810                         #iommu-cells = <0>;
 811                 };
 812
 813                 sysmmu_scaler1r: sysmmu@0x12890000 {
 814                         compatible = "samsung,exynos-sysmmu";
 815                         reg = <0x12890000 0x1000>;
 816                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 817                         clock-names = "sysmmu", "master";
 818                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
 819                         #iommu-cells = <0>;
 820                 };
 821
 822                 sysmmu_scaler2r: sysmmu@0x128A0000 {
 823                         compatible = "samsung,exynos-sysmmu";
 824                         reg = <0x128A0000 0x1000>;
 825                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 826                         clock-names = "sysmmu", "master";
 827                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
 828                         #iommu-cells = <0>;
 829                 };
 830
 831                 sysmmu_scaler0w: sysmmu@0x128C0000 {
 832                         compatible = "samsung,exynos-sysmmu";
 833                         reg = <0x128C0000 0x1000>;
 834                         interrupt-parent = <&combiner>;
 835                         interrupts = <27 2>;
 836                         clock-names = "sysmmu", "master";
 837                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
 838                         #iommu-cells = <0>;
 839                 };
 840
 841                 sysmmu_scaler1w: sysmmu@0x128D0000 {
 842                         compatible = "samsung,exynos-sysmmu";
 843                         reg = <0x128D0000 0x1000>;
 844                         interrupt-parent = <&combiner>;
 845                         interrupts = <22 6>;
 846                         clock-names = "sysmmu", "master";
 847                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
 848                         #iommu-cells = <0>;
 849                 };
 850
 851                 sysmmu_scaler2w: sysmmu@0x128E0000 {
 852                         compatible = "samsung,exynos-sysmmu";
 853                         reg = <0x128E0000 0x1000>;
 854                         interrupt-parent = <&combiner>;
 855                         interrupts = <19 6>;
 856                         clock-names = "sysmmu", "master";
 857                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
 858                         #iommu-cells = <0>;
 859                 };
 860
 861                 sysmmu_rotator: sysmmu@0x11D40000 {
 862                         compatible = "samsung,exynos-sysmmu";
 863                         reg = <0x11D40000 0x1000>;
 864                         interrupt-parent = <&combiner>;
 865                         interrupts = <4 0>;
 866                         clock-names = "sysmmu", "master";
 867                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 868                         #iommu-cells = <0>;
 869                 };
 870
 871                 sysmmu_jpeg0: sysmmu@0x11F10000 {
 872                         compatible = "samsung,exynos-sysmmu";
 873                         reg = <0x11F10000 0x1000>;
 874                         interrupt-parent = <&combiner>;
 875                         interrupts = <4 2>;
 876                         clock-names = "sysmmu", "master";
 877                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 878                         #iommu-cells = <0>;
 879                 };
 880
 881                 sysmmu_jpeg1: sysmmu@0x11F20000 {
 882                         compatible = "samsung,exynos-sysmmu";
 883                         reg = <0x11F20000 0x1000>;
 884                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 885                         clock-names = "sysmmu", "master";
 886                         clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
 887                         #iommu-cells = <0>;
 888                 };
 889
 890                 sysmmu_mfc_l: sysmmu@0x11200000 {
 891                         compatible = "samsung,exynos-sysmmu";
 892                         reg = <0x11200000 0x1000>;
 893                         interrupt-parent = <&combiner>;
 894                         interrupts = <6 2>;
 895                         clock-names = "sysmmu", "master";
 896                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 897                         power-domains = <&mfc_pd>;
 898                         #iommu-cells = <0>;
 899                 };
 900
 901                 sysmmu_mfc_r: sysmmu@0x11210000 {
 902                         compatible = "samsung,exynos-sysmmu";
 903                         reg = <0x11210000 0x1000>;
 904                         interrupt-parent = <&combiner>;
 905                         interrupts = <8 5>;
 906                         clock-names = "sysmmu", "master";
 907                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 908                         power-domains = <&mfc_pd>;
 909                         #iommu-cells = <0>;
 910                 };
 911
 912                 sysmmu_fimd1_0: sysmmu@0x14640000 {
 913                         compatible = "samsung,exynos-sysmmu";
 914                         reg = <0x14640000 0x1000>;
 915                         interrupt-parent = <&combiner>;
 916                         interrupts = <3 2>;
 917                         clock-names = "sysmmu", "master";
 918                         clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
 919                         power-domains = <&disp_pd>;
 920                         #iommu-cells = <0>;
 921                 };
 922
 923                 sysmmu_fimd1_1: sysmmu@0x14680000 {
 924                         compatible = "samsung,exynos-sysmmu";
 925                         reg = <0x14680000 0x1000>;
 926                         interrupt-parent = <&combiner>;
 927                         interrupts = <3 0>;
 928                         clock-names = "sysmmu", "master";
 929                         clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
 930                         power-domains = <&disp_pd>;
 931                         #iommu-cells = <0>;
 932                 };
 933
 934                 bus_wcore: bus_wcore {
 935                         compatible = "samsung,exynos-bus";
 936                         clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
 937                         clock-names = "bus";
 938                         operating-points-v2 = <&bus_wcore_opp_table>;
 939                         status = "disabled";
 940                 };
 941
 942                 bus_noc: bus_noc {
 943                         compatible = "samsung,exynos-bus";
 944                         clocks = <&clock CLK_DOUT_ACLK100_NOC>;
 945                         clock-names = "bus";
 946                         operating-points-v2 = <&bus_noc_opp_table>;
 947                         status = "disabled";
 948                 };
 949
 950                 bus_fsys_apb: bus_fsys_apb {
 951                         compatible = "samsung,exynos-bus";
 952                         clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
 953                         clock-names = "bus";
 954                         operating-points-v2 = <&bus_fsys_apb_opp_table>;
 955                         status = "disabled";
 956                 };
 957
 958                 bus_fsys: bus_fsys {
 959                         compatible = "samsung,exynos-bus";
 960                         clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
 961                         clock-names = "bus";
 962                         operating-points-v2 = <&bus_fsys_apb_opp_table>;
 963                         status = "disabled";
 964                 };
 965
 966                 bus_fsys2: bus_fsys2 {
 967                         compatible = "samsung,exynos-bus";
 968                         clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
 969                         clock-names = "bus";
 970                         operating-points-v2 = <&bus_fsys2_opp_table>;
 971                         status = "disabled";
 972                 };
 973
 974                 bus_mfc: bus_mfc {
 975                         compatible = "samsung,exynos-bus";
 976                         clocks = <&clock CLK_DOUT_ACLK333>;
 977                         clock-names = "bus";
 978                         operating-points-v2 = <&bus_mfc_opp_table>;
 979                         status = "disabled";
 980                 };
 981
 982                 bus_gen: bus_gen {
 983                         compatible = "samsung,exynos-bus";
 984                         clocks = <&clock CLK_DOUT_ACLK266>;
 985                         clock-names = "bus";
 986                         operating-points-v2 = <&bus_gen_opp_table>;
 987                         status = "disabled";
 988                 };
 989
 990                 bus_peri: bus_peri {
 991                         compatible = "samsung,exynos-bus";
 992                         clocks = <&clock CLK_DOUT_ACLK66>;
 993                         clock-names = "bus";
 994                         operating-points-v2 = <&bus_peri_opp_table>;
 995                         status = "disabled";
 996                 };
 997
 998                 bus_g2d: bus_g2d {
 999                         compatible = "samsung,exynos-bus";
1000                         clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1001                         clock-names = "bus";
1002                         operating-points-v2 = <&bus_g2d_opp_table>;
1003                         status = "disabled";
1004                 };
1005
1006                 bus_g2d_acp: bus_g2d_acp {
1007                         compatible = "samsung,exynos-bus";
1008                         clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1009                         clock-names = "bus";
1010                         operating-points-v2 = <&bus_g2d_acp_opp_table>;
1011                         status = "disabled";
1012                 };
1013
1014                 bus_jpeg: bus_jpeg {
1015                         compatible = "samsung,exynos-bus";
1016                         clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1017                         clock-names = "bus";
1018                         operating-points-v2 = <&bus_jpeg_opp_table>;
1019                         status = "disabled";
1020                 };
1021
1022                 bus_jpeg_apb: bus_jpeg_apb {
1023                         compatible = "samsung,exynos-bus";
1024                         clocks = <&clock CLK_DOUT_ACLK166>;
1025                         clock-names = "bus";
1026                         operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1027                         status = "disabled";
1028                 };
1029
1030                 bus_disp1_fimd: bus_disp1_fimd {
1031                         compatible = "samsung,exynos-bus";
1032                         clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1033                         clock-names = "bus";
1034                         operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1035                         status = "disabled";
1036                 };
1037
1038                 bus_disp1: bus_disp1 {
1039                         compatible = "samsung,exynos-bus";
1040                         clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1041                         clock-names = "bus";
1042                         operating-points-v2 = <&bus_disp1_opp_table>;
1043                         status = "disabled";
1044                 };
1045
1046                 bus_gscl_scaler: bus_gscl_scaler {
1047                         compatible = "samsung,exynos-bus";
1048                         clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1049                         clock-names = "bus";
1050                         operating-points-v2 = <&bus_gscl_opp_table>;
1051                         status = "disabled";
1052                 };
1053
1054                 bus_mscl: bus_mscl {
1055                         compatible = "samsung,exynos-bus";
1056                         clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1057                         clock-names = "bus";
1058                         operating-points-v2 = <&bus_mscl_opp_table>;
1059                         status = "disabled";
1060                 };
1061
1062                 bus_wcore_opp_table: opp_table2 {
1063                         compatible = "operating-points-v2";
1064
1065                         opp00 {
1066                                 opp-hz = /bits/ 64 <84000000>;
1067                                 opp-microvolt = <925000>;
1068                         };
1069                         opp01 {
1070                                 opp-hz = /bits/ 64 <111000000>;
1071                                 opp-microvolt = <950000>;
1072                         };
1073                         opp02 {
1074                                 opp-hz = /bits/ 64 <222000000>;
1075                                 opp-microvolt = <950000>;
1076                         };
1077                         opp03 {
1078                                 opp-hz = /bits/ 64 <333000000>;
1079                                 opp-microvolt = <950000>;
1080                         };
1081                         opp04 {
1082                                 opp-hz = /bits/ 64 <400000000>;
1083                                 opp-microvolt = <987500>;
1084                         };
1085                 };
1086
1087                 bus_noc_opp_table: opp_table3 {
1088                         compatible = "operating-points-v2";
1089
1090                         opp00 {
1091                                 opp-hz = /bits/ 64 <67000000>;
1092                         };
1093                         opp01 {
1094                                 opp-hz = /bits/ 64 <75000000>;
1095                         };
1096                         opp02 {
1097                                 opp-hz = /bits/ 64 <86000000>;
1098                         };
1099                         opp03 {
1100                                 opp-hz = /bits/ 64 <100000000>;
1101                         };
1102                 };
1103
1104                 bus_fsys_apb_opp_table: opp_table4 {
1105                         compatible = "operating-points-v2";
1106                         opp-shared;
1107
1108                         opp00 {
1109                                 opp-hz = /bits/ 64 <100000000>;
1110                         };
1111                         opp01 {
1112                                 opp-hz = /bits/ 64 <200000000>;
1113                         };
1114                 };
1115
1116                 bus_fsys2_opp_table: opp_table5 {
1117                         compatible = "operating-points-v2";
1118
1119                         opp00 {
1120                                 opp-hz = /bits/ 64 <75000000>;
1121                         };
1122                         opp01 {
1123                                 opp-hz = /bits/ 64 <100000000>;
1124                         };
1125                         opp02 {
1126                                 opp-hz = /bits/ 64 <150000000>;
1127                         };
1128                 };
1129
1130                 bus_mfc_opp_table: opp_table6 {
1131                         compatible = "operating-points-v2";
1132
1133                         opp00 {
1134                                 opp-hz = /bits/ 64 <96000000>;
1135                         };
1136                         opp01 {
1137                                 opp-hz = /bits/ 64 <111000000>;
1138                         };
1139                         opp02 {
1140                                 opp-hz = /bits/ 64 <167000000>;
1141                         };
1142                         opp03 {
1143                                 opp-hz = /bits/ 64 <222000000>;
1144                         };
1145                         opp04 {
1146                                 opp-hz = /bits/ 64 <333000000>;
1147                         };
1148                 };
1149
1150                 bus_gen_opp_table: opp_table7 {
1151                         compatible = "operating-points-v2";
1152
1153                         opp00 {
1154                                 opp-hz = /bits/ 64 <89000000>;
1155                         };
1156                         opp01 {
1157                                 opp-hz = /bits/ 64 <133000000>;
1158                         };
1159                         opp02 {
1160                                 opp-hz = /bits/ 64 <178000000>;
1161                         };
1162                         opp03 {
1163                                 opp-hz = /bits/ 64 <267000000>;
1164                         };
1165                 };
1166
1167                 bus_peri_opp_table: opp_table8 {
1168                         compatible = "operating-points-v2";
1169
1170                         opp00 {
1171                                 opp-hz = /bits/ 64 <67000000>;
1172                         };
1173                 };
1174
1175                 bus_g2d_opp_table: opp_table9 {
1176                         compatible = "operating-points-v2";
1177
1178                         opp00 {
1179                                 opp-hz = /bits/ 64 <84000000>;
1180                         };
1181                         opp01 {
1182                                 opp-hz = /bits/ 64 <167000000>;
1183                         };
1184                         opp02 {
1185                                 opp-hz = /bits/ 64 <222000000>;
1186                         };
1187                         opp03 {
1188                                 opp-hz = /bits/ 64 <300000000>;
1189                         };
1190                         opp04 {
1191                                 opp-hz = /bits/ 64 <333000000>;
1192                         };
1193                 };
1194
1195                 bus_g2d_acp_opp_table: opp_table10 {
1196                         compatible = "operating-points-v2";
1197
1198                         opp00 {
1199                                 opp-hz = /bits/ 64 <67000000>;
1200                         };
1201                         opp01 {
1202                                 opp-hz = /bits/ 64 <133000000>;
1203                         };
1204                         opp02 {
1205                                 opp-hz = /bits/ 64 <178000000>;
1206                         };
1207                         opp03 {
1208                                 opp-hz = /bits/ 64 <267000000>;
1209                         };
1210                 };
1211
1212                 bus_jpeg_opp_table: opp_table11 {
1213                         compatible = "operating-points-v2";
1214
1215                         opp00 {
1216                                 opp-hz = /bits/ 64 <75000000>;
1217                         };
1218                         opp01 {
1219                                 opp-hz = /bits/ 64 <150000000>;
1220                         };
1221                         opp02 {
1222                                 opp-hz = /bits/ 64 <200000000>;
1223                         };
1224                         opp03 {
1225                                 opp-hz = /bits/ 64 <300000000>;
1226                         };
1227                 };
1228
1229                 bus_jpeg_apb_opp_table: opp_table12 {
1230                         compatible = "operating-points-v2";
1231
1232                         opp00 {
1233                                 opp-hz = /bits/ 64 <84000000>;
1234                         };
1235                         opp01 {
1236                                 opp-hz = /bits/ 64 <111000000>;
1237                         };
1238                         opp02 {
1239                                 opp-hz = /bits/ 64 <134000000>;
1240                         };
1241                         opp03 {
1242                                 opp-hz = /bits/ 64 <167000000>;
1243                         };
1244                 };
1245
1246                 bus_disp1_fimd_opp_table: opp_table13 {
1247                         compatible = "operating-points-v2";
1248
1249                         opp00 {
1250                                 opp-hz = /bits/ 64 <120000000>;
1251                         };
1252                         opp01 {
1253                                 opp-hz = /bits/ 64 <200000000>;
1254                         };
1255                 };
1256
1257                 bus_disp1_opp_table: opp_table14 {
1258                         compatible = "operating-points-v2";
1259
1260                         opp00 {
1261                                 opp-hz = /bits/ 64 <120000000>;
1262                         };
1263                         opp01 {
1264                                 opp-hz = /bits/ 64 <200000000>;
1265                         };
1266                         opp02 {
1267                                 opp-hz = /bits/ 64 <300000000>;
1268                         };
1269                 };
1270
1271                 bus_gscl_opp_table: opp_table15 {
1272                         compatible = "operating-points-v2";
1273
1274                         opp00 {
1275                                 opp-hz = /bits/ 64 <150000000>;
1276                         };
1277                         opp01 {
1278                                 opp-hz = /bits/ 64 <200000000>;
1279                         };
1280                         opp02 {
1281                                 opp-hz = /bits/ 64 <300000000>;
1282                         };
1283                 };
1284
1285                 bus_mscl_opp_table: opp_table16 {
1286                         compatible = "operating-points-v2";
1287
1288                         opp00 {
1289                                 opp-hz = /bits/ 64 <84000000>;
1290                         };
1291                         opp01 {
1292                                 opp-hz = /bits/ 64 <167000000>;
1293                         };
1294                         opp02 {
1295                                 opp-hz = /bits/ 64 <222000000>;
1296                         };
1297                         opp03 {
1298                                 opp-hz = /bits/ 64 <333000000>;
1299                         };
1300                         opp04 {
1301                                 opp-hz = /bits/ 64 <400000000>;
1302                         };
1303                 };
1304         };
1305
1306         thermal-zones {
1307                 cpu0_thermal: cpu0-thermal {
1308                         thermal-sensors = <&tmu_cpu0>;
1309                         #include "exynos5420-trip-points.dtsi"
1310                 };
1311                 cpu1_thermal: cpu1-thermal {
1312                        thermal-sensors = <&tmu_cpu1>;
1313                        #include "exynos5420-trip-points.dtsi"
1314                 };
1315                 cpu2_thermal: cpu2-thermal {
1316                        thermal-sensors = <&tmu_cpu2>;
1317                        #include "exynos5420-trip-points.dtsi"
1318                 };
1319                 cpu3_thermal: cpu3-thermal {
1320                        thermal-sensors = <&tmu_cpu3>;
1321                        #include "exynos5420-trip-points.dtsi"
1322                 };
1323                 gpu_thermal: gpu-thermal {
1324                        thermal-sensors = <&tmu_gpu>;
1325                        #include "exynos5420-trip-points.dtsi"
1326                 };
1327         };
1328 };
1329
1330 &dp {
1331         clocks = <&clock CLK_DP1>;
1332         clock-names = "dp";
1333         phys = <&dp_phy>;
1334         phy-names = "dp";
1335         power-domains = <&disp_pd>;
1336 };
1337
1338 &fimd {
1339         compatible = "samsung,exynos5420-fimd";
1340         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1341         clock-names = "sclk_fimd", "fimd";
1342         power-domains = <&disp_pd>;
1343         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1344         iommu-names = "m0", "m1";
1345 };
1346
1347 &g2d {
1348         iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1349         clocks = <&clock CLK_G2D>;
1350         clock-names = "fimg2d";
1351         status = "okay";
1352 };
1353
1354 &i2c_0 {
1355         clocks = <&clock CLK_I2C0>;
1356         clock-names = "i2c";
1357         pinctrl-names = "default";
1358         pinctrl-0 = <&i2c0_bus>;
1359 };
1360
1361 &i2c_1 {
1362         clocks = <&clock CLK_I2C1>;
1363         clock-names = "i2c";
1364         pinctrl-names = "default";
1365         pinctrl-0 = <&i2c1_bus>;
1366 };
1367
1368 &i2c_2 {
1369         clocks = <&clock CLK_I2C2>;
1370         clock-names = "i2c";
1371         pinctrl-names = "default";
1372         pinctrl-0 = <&i2c2_bus>;
1373 };
1374
1375 &i2c_3 {
1376         clocks = <&clock CLK_I2C3>;
1377         clock-names = "i2c";
1378         pinctrl-names = "default";
1379         pinctrl-0 = <&i2c3_bus>;
1380 };
1381
1382 &hsi2c_4 {
1383         clocks = <&clock CLK_USI0>;
1384         clock-names = "hsi2c";
1385         pinctrl-names = "default";
1386         pinctrl-0 = <&i2c4_hs_bus>;
1387 };
1388
1389 &hsi2c_5 {
1390         clocks = <&clock CLK_USI1>;
1391         clock-names = "hsi2c";
1392         pinctrl-names = "default";
1393         pinctrl-0 = <&i2c5_hs_bus>;
1394 };
1395
1396 &hsi2c_6 {
1397         clocks = <&clock CLK_USI2>;
1398         clock-names = "hsi2c";
1399         pinctrl-names = "default";
1400         pinctrl-0 = <&i2c6_hs_bus>;
1401 };
1402
1403 &hsi2c_7 {
1404         clocks = <&clock CLK_USI3>;
1405         clock-names = "hsi2c";
1406         pinctrl-names = "default";
1407         pinctrl-0 = <&i2c7_hs_bus>;
1408 };
1409
1410 &mct {
1411         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1412         clock-names = "fin_pll", "mct";
1413 };
1414
1415 &prng {
1416         clocks = <&clock CLK_SSS>;
1417         clock-names = "secss";
1418 };
1419
1420 &pwm {
1421         clocks = <&clock CLK_PWM>;
1422         clock-names = "timers";
1423 };
1424
1425 &rtc {
1426         clocks = <&clock CLK_RTC>;
1427         clock-names = "rtc";
1428         interrupt-parent = <&pmu_system_controller>;
1429         status = "disabled";
1430 };
1431
1432 &serial_0 {
1433         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1434         clock-names = "uart", "clk_uart_baud0";
1435         dmas = <&pdma0 13>, <&pdma0 14>;
1436         dma-names = "rx", "tx";
1437 };
1438
1439 &serial_1 {
1440         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1441         clock-names = "uart", "clk_uart_baud0";
1442         dmas = <&pdma1 15>, <&pdma1 16>;
1443         dma-names = "rx", "tx";
1444 };
1445
1446 &serial_2 {
1447         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1448         clock-names = "uart", "clk_uart_baud0";
1449         dmas = <&pdma0 15>, <&pdma0 16>;
1450         dma-names = "rx", "tx";
1451 };
1452
1453 &serial_3 {
1454         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1455         clock-names = "uart", "clk_uart_baud0";
1456         dmas = <&pdma1 17>, <&pdma1 18>;
1457         dma-names = "rx", "tx";
1458 };
1459
1460 &sss {
1461         clocks = <&clock CLK_SSS>;
1462         clock-names = "secss";
1463 };
1464
1465 &trng {
1466         clocks = <&clock CLK_SSS>;
1467         clock-names = "secss";
1468 };
1469
1470 &usbdrd3_0 {
1471         clocks = <&clock CLK_USBD300>;
1472         clock-names = "usbdrd30";
1473 };
1474
1475 &usbdrd_phy0 {
1476         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1477         clock-names = "phy", "ref";
1478         samsung,pmu-syscon = <&pmu_system_controller>;
1479 };
1480
1481 &usbdrd3_1 {
1482         clocks = <&clock CLK_USBD301>;
1483         clock-names = "usbdrd30";
1484 };
1485
1486 &usbdrd_dwc3_1 {
1487         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1488 };
1489
1490 &usbdrd_phy1 {
1491         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1492         clock-names = "phy", "ref";
1493         samsung,pmu-syscon = <&pmu_system_controller>;
1494 };
1495
1496 &usbhost1 {
1497         clocks = <&clock CLK_USBH20>;
1498         clock-names = "usbhost";
1499 };
1500
1501 &usbhost2 {
1502         clocks = <&clock CLK_USBH20>;
1503         clock-names = "usbhost";
1504 };
1505
1506 &usb2_phy {
1507         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1508         clock-names = "phy", "ref";
1509         samsung,sysreg-phandle = <&sysreg_system_controller>;
1510         samsung,pmureg-phandle = <&pmu_system_controller>;
1511 };
1512
1513 &watchdog {
1514         clocks = <&clock CLK_WDT>;
1515         clock-names = "watchdog";
1516         samsung,syscon-phandle = <&pmu_system_controller>;
1517 };
1518
1519 #include "exynos5420-pinctrl.dtsi"
1520 #include "exynos-syscon-restart.dtsi"