arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos5.dtsi"
  17 #include "exynos5420-pinctrl.dtsi"
  18
  19 #include <dt-bindings/clk/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &hsi2c_4;
  38                 i2c5 = &hsi2c_5;
  39                 i2c6 = &hsi2c_6;
  40                 i2c7 = &hsi2c_7;
  41                 i2c8 = &hsi2c_8;
  42                 i2c9 = &hsi2c_9;
  43                 i2c10 = &hsi2c_10;
  44                 gsc0 = &gsc_0;
  45                 gsc1 = &gsc_1;
  46                 spi0 = &spi_0;
  47                 spi1 = &spi_1;
  48                 spi2 = &spi_2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x0>;
  59                         clock-frequency = <1800000000>;
  60                 };
  61
  62                 cpu1: cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                         clock-frequency = <1800000000>;
  67                 };
  68
  69                 cpu2: cpu@2 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a15";
  72                         reg = <0x2>;
  73                         clock-frequency = <1800000000>;
  74                 };
  75
  76                 cpu3: cpu@3 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a15";
  79                         reg = <0x3>;
  80                         clock-frequency = <1800000000>;
  81                 };
  82
  83                 cpu4: cpu@100 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a7";
  86                         reg = <0x100>;
  87                         clock-frequency = <1000000000>;
  88                 };
  89
  90                 cpu5: cpu@101 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x101>;
  94                         clock-frequency = <1000000000>;
  95                 };
  96
  97                 cpu6: cpu@102 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a7";
 100                         reg = <0x102>;
 101                         clock-frequency = <1000000000>;
 102                 };
 103
 104                 cpu7: cpu@103 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a7";
 107                         reg = <0x103>;
 108                         clock-frequency = <1000000000>;
 109                 };
 110         };
 111
 112         clock: clock-controller@10010000 {
 113                 compatible = "samsung,exynos5420-clock";
 114                 reg = <0x10010000 0x30000>;
 115                 #clock-cells = <1>;
 116         };
 117
 118         clock_audss: audss-clock-controller@3810000 {
 119                 compatible = "samsung,exynos5420-audss-clock";
 120                 reg = <0x03810000 0x0C>;
 121                 #clock-cells = <1>;
 122                 clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
 123                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 124         };
 125
 126         codec@11000000 {
 127                 compatible = "samsung,mfc-v7";
 128                 reg = <0x11000000 0x10000>;
 129                 interrupts = <0 96 0>;
 130                 clocks = <&clock 401>;
 131                 clock-names = "mfc";
 132         };
 133
 134         mmc_0: mmc@12200000 {
 135                 compatible = "samsung,exynos5420-dw-mshc-smu";
 136                 interrupts = <0 75 0>;
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139                 reg = <0x12200000 0x2000>;
 140                 clocks = <&clock 351>, <&clock 132>;
 141                 clock-names = "biu", "ciu";
 142                 fifo-depth = <0x40>;
 143                 status = "disabled";
 144         };
 145
 146         mmc_1: mmc@12210000 {
 147                 compatible = "samsung,exynos5420-dw-mshc-smu";
 148                 interrupts = <0 76 0>;
 149                 #address-cells = <1>;
 150                 #size-cells = <0>;
 151                 reg = <0x12210000 0x2000>;
 152                 clocks = <&clock 352>, <&clock 133>;
 153                 clock-names = "biu", "ciu";
 154                 fifo-depth = <0x40>;
 155                 status = "disabled";
 156         };
 157
 158         mmc_2: mmc@12220000 {
 159                 compatible = "samsung,exynos5420-dw-mshc";
 160                 interrupts = <0 77 0>;
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 reg = <0x12220000 0x1000>;
 164                 clocks = <&clock 353>, <&clock 134>;
 165                 clock-names = "biu", "ciu";
 166                 fifo-depth = <0x40>;
 167                 status = "disabled";
 168         };
 169
 170         mct@101C0000 {
 171                 compatible = "samsung,exynos4210-mct";
 172                 reg = <0x101C0000 0x800>;
 173                 interrupt-controller;
 174                 #interrups-cells = <1>;
 175                 interrupt-parent = <&mct_map>;
 176                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 177                                 <8>, <9>, <10>, <11>;
 178                 clocks = <&clock 1>, <&clock 315>;
 179                 clock-names = "fin_pll", "mct";
 180
 181                 mct_map: mct-map {
 182                         #interrupt-cells = <1>;
 183                         #address-cells = <0>;
 184                         #size-cells = <0>;
 185                         interrupt-map = <0 &combiner 23 3>,
 186                                         <1 &combiner 23 4>,
 187                                         <2 &combiner 25 2>,
 188                                         <3 &combiner 25 3>,
 189                                         <4 &gic 0 120 0>,
 190                                         <5 &gic 0 121 0>,
 191                                         <6 &gic 0 122 0>,
 192                                         <7 &gic 0 123 0>,
 193                                         <8 &gic 0 128 0>,
 194                                         <9 &gic 0 129 0>,
 195                                         <10 &gic 0 130 0>,
 196                                         <11 &gic 0 131 0>;
 197                 };
 198         };
 199
 200         gsc_pd: power-domain@10044000 {
 201                 compatible = "samsung,exynos4210-pd";
 202                 reg = <0x10044000 0x20>;
 203         };
 204
 205         isp_pd: power-domain@10044020 {
 206                 compatible = "samsung,exynos4210-pd";
 207                 reg = <0x10044020 0x20>;
 208         };
 209
 210         mfc_pd: power-domain@10044060 {
 211                 compatible = "samsung,exynos4210-pd";
 212                 reg = <0x10044060 0x20>;
 213         };
 214
 215         disp_pd: power-domain@100440C0 {
 216                 compatible = "samsung,exynos4210-pd";
 217                 reg = <0x100440C0 0x20>;
 218         };
 219
 220         mau_pd: power-domain@100440E0 {
 221                 compatible = "samsung,exynos4210-pd";
 222                 reg = <0x100440E0 0x20>;
 223         };
 224
 225         g2d_pd: power-domain@10044100 {
 226                 compatible = "samsung,exynos4210-pd";
 227                 reg = <0x10044100 0x20>;
 228         };
 229
 230         msc_pd: power-domain@10044120 {
 231                 compatible = "samsung,exynos4210-pd";
 232                 reg = <0x10044120 0x20>;
 233         };
 234
 235         pinctrl_0: pinctrl@13400000 {
 236                 compatible = "samsung,exynos5420-pinctrl";
 237                 reg = <0x13400000 0x1000>;
 238                 interrupts = <0 45 0>;
 239
 240                 wakeup-interrupt-controller {
 241                         compatible = "samsung,exynos4210-wakeup-eint";
 242                         interrupt-parent = <&gic>;
 243                         interrupts = <0 32 0>;
 244                 };
 245         };
 246
 247         pinctrl_1: pinctrl@13410000 {
 248                 compatible = "samsung,exynos5420-pinctrl";
 249                 reg = <0x13410000 0x1000>;
 250                 interrupts = <0 78 0>;
 251         };
 252
 253         pinctrl_2: pinctrl@14000000 {
 254                 compatible = "samsung,exynos5420-pinctrl";
 255                 reg = <0x14000000 0x1000>;
 256                 interrupts = <0 46 0>;
 257         };
 258
 259         pinctrl_3: pinctrl@14010000 {
 260                 compatible = "samsung,exynos5420-pinctrl";
 261                 reg = <0x14010000 0x1000>;
 262                 interrupts = <0 50 0>;
 263         };
 264
 265         pinctrl_4: pinctrl@03860000 {
 266                 compatible = "samsung,exynos5420-pinctrl";
 267                 reg = <0x03860000 0x1000>;
 268                 interrupts = <0 47 0>;
 269         };
 270
 271         rtc@101E0000 {
 272                 clocks = <&clock 317>;
 273                 clock-names = "rtc";
 274                 status = "okay";
 275         };
 276
 277         amba {
 278                 #address-cells = <1>;
 279                 #size-cells = <1>;
 280                 compatible = "arm,amba-bus";
 281                 interrupt-parent = <&gic>;
 282                 ranges;
 283
 284                 pdma0: pdma@121A0000 {
 285                         compatible = "arm,pl330", "arm,primecell";
 286                         reg = <0x121A0000 0x1000>;
 287                         interrupts = <0 34 0>;
 288                         clocks = <&clock 362>;
 289                         clock-names = "apb_pclk";
 290                         #dma-cells = <1>;
 291                         #dma-channels = <8>;
 292                         #dma-requests = <32>;
 293                 };
 294
 295                 pdma1: pdma@121B0000 {
 296                         compatible = "arm,pl330", "arm,primecell";
 297                         reg = <0x121B0000 0x1000>;
 298                         interrupts = <0 35 0>;
 299                         clocks = <&clock 363>;
 300                         clock-names = "apb_pclk";
 301                         #dma-cells = <1>;
 302                         #dma-channels = <8>;
 303                         #dma-requests = <32>;
 304                 };
 305
 306                 mdma0: mdma@10800000 {
 307                         compatible = "arm,pl330", "arm,primecell";
 308                         reg = <0x10800000 0x1000>;
 309                         interrupts = <0 33 0>;
 310                         clocks = <&clock 473>;
 311                         clock-names = "apb_pclk";
 312                         #dma-cells = <1>;
 313                         #dma-channels = <8>;
 314                         #dma-requests = <1>;
 315                 };
 316
 317                 mdma1: mdma@11C10000 {
 318                         compatible = "arm,pl330", "arm,primecell";
 319                         reg = <0x11C10000 0x1000>;
 320                         interrupts = <0 124 0>;
 321                         clocks = <&clock 442>;
 322                         clock-names = "apb_pclk";
 323                         #dma-cells = <1>;
 324                         #dma-channels = <8>;
 325                         #dma-requests = <1>;
 326                         /*
 327                          * MDMA1 can support both secure and non-secure
 328                          * AXI transactions. When this is enabled in the kernel
 329                          * for boards that run in secure mode, we are getting
 330                          * imprecise external aborts causing the kernel to oops.
 331                          */
 332                         status = "disabled";
 333                 };
 334         };
 335
 336         spi_0: spi@12d20000 {
 337                 compatible = "samsung,exynos4210-spi";
 338                 reg = <0x12d20000 0x100>;
 339                 interrupts = <0 66 0>;
 340                 dmas = <&pdma0 5
 341                         &pdma0 4>;
 342                 dma-names = "tx", "rx";
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&spi0_bus>;
 347                 clocks = <&clock 271>, <&clock 135>;
 348                 clock-names = "spi", "spi_busclk0";
 349                 status = "disabled";
 350         };
 351
 352         spi_1: spi@12d30000 {
 353                 compatible = "samsung,exynos4210-spi";
 354                 reg = <0x12d30000 0x100>;
 355                 interrupts = <0 67 0>;
 356                 dmas = <&pdma1 5
 357                         &pdma1 4>;
 358                 dma-names = "tx", "rx";
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&spi1_bus>;
 363                 clocks = <&clock 272>, <&clock 136>;
 364                 clock-names = "spi", "spi_busclk0";
 365                 status = "disabled";
 366         };
 367
 368         spi_2: spi@12d40000 {
 369                 compatible = "samsung,exynos4210-spi";
 370                 reg = <0x12d40000 0x100>;
 371                 interrupts = <0 68 0>;
 372                 dmas = <&pdma0 7
 373                         &pdma0 6>;
 374                 dma-names = "tx", "rx";
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&spi2_bus>;
 379                 clocks = <&clock 273>, <&clock 137>;
 380                 clock-names = "spi", "spi_busclk0";
 381                 status = "disabled";
 382         };
 383
 384         serial@12C00000 {
 385                 clocks = <&clock 257>, <&clock 128>;
 386                 clock-names = "uart", "clk_uart_baud0";
 387         };
 388
 389         serial@12C10000 {
 390                 clocks = <&clock 258>, <&clock 129>;
 391                 clock-names = "uart", "clk_uart_baud0";
 392         };
 393
 394         serial@12C20000 {
 395                 clocks = <&clock 259>, <&clock 130>;
 396                 clock-names = "uart", "clk_uart_baud0";
 397         };
 398
 399         serial@12C30000 {
 400                 clocks = <&clock 260>, <&clock 131>;
 401                 clock-names = "uart", "clk_uart_baud0";
 402         };
 403
 404         pwm: pwm@12dd0000 {
 405                 compatible = "samsung,exynos4210-pwm";
 406                 reg = <0x12dd0000 0x100>;
 407                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 408                 #pwm-cells = <3>;
 409                 clocks = <&clock 279>;
 410                 clock-names = "timers";
 411         };
 412
 413         dp_phy: video-phy@10040728 {
 414                 compatible = "samsung,exynos5250-dp-video-phy";
 415                 reg = <0x10040728 4>;
 416                 #phy-cells = <0>;
 417         };
 418
 419         dp-controller@145B0000 {
 420                 clocks = <&clock 412>;
 421                 clock-names = "dp";
 422                 phys = <&dp_phy>;
 423                 phy-names = "dp";
 424         };
 425
 426         fimd@14400000 {
 427                 samsung,power-domain = <&disp_pd>;
 428                 clocks = <&clock 147>, <&clock 421>;
 429                 clock-names = "sclk_fimd", "fimd";
 430         };
 431
 432         adc: adc@12D10000 {
 433                 compatible = "samsung,exynos-adc-v2";
 434                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 435                 interrupts = <0 106 0>;
 436                 clocks = <&clock 270>;
 437                 clock-names = "adc";
 438                 #io-channel-cells = <1>;
 439                 io-channel-ranges;
 440                 status = "disabled";
 441         };
 442
 443         i2c_0: i2c@12C60000 {
 444                 compatible = "samsung,s3c2440-i2c";
 445                 reg = <0x12C60000 0x100>;
 446                 interrupts = <0 56 0>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 clocks = <&clock 261>;
 450                 clock-names = "i2c";
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&i2c0_bus>;
 453                 status = "disabled";
 454         };
 455
 456         i2c_1: i2c@12C70000 {
 457                 compatible = "samsung,s3c2440-i2c";
 458                 reg = <0x12C70000 0x100>;
 459                 interrupts = <0 57 0>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clocks = <&clock 262>;
 463                 clock-names = "i2c";
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&i2c1_bus>;
 466                 status = "disabled";
 467         };
 468
 469         i2c_2: i2c@12C80000 {
 470                 compatible = "samsung,s3c2440-i2c";
 471                 reg = <0x12C80000 0x100>;
 472                 interrupts = <0 58 0>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 clocks = <&clock 263>;
 476                 clock-names = "i2c";
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&i2c2_bus>;
 479                 status = "disabled";
 480         };
 481
 482         i2c_3: i2c@12C90000 {
 483                 compatible = "samsung,s3c2440-i2c";
 484                 reg = <0x12C90000 0x100>;
 485                 interrupts = <0 59 0>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 clocks = <&clock 264>;
 489                 clock-names = "i2c";
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c3_bus>;
 492                 status = "disabled";
 493         };
 494
 495         hsi2c_4: i2c@12CA0000 {
 496                 compatible = "samsung,exynos5-hsi2c";
 497                 reg = <0x12CA0000 0x1000>;
 498                 interrupts = <0 60 0>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&i2c4_hs_bus>;
 503                 clocks = <&clock 265>;
 504                 clock-names = "hsi2c";
 505                 status = "disabled";
 506         };
 507
 508         hsi2c_5: i2c@12CB0000 {
 509                 compatible = "samsung,exynos5-hsi2c";
 510                 reg = <0x12CB0000 0x1000>;
 511                 interrupts = <0 61 0>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&i2c5_hs_bus>;
 516                 clocks = <&clock 266>;
 517                 clock-names = "hsi2c";
 518                 status = "disabled";
 519         };
 520
 521         hsi2c_6: i2c@12CC0000 {
 522                 compatible = "samsung,exynos5-hsi2c";
 523                 reg = <0x12CC0000 0x1000>;
 524                 interrupts = <0 62 0>;
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&i2c6_hs_bus>;
 529                 clocks = <&clock 267>;
 530                 clock-names = "hsi2c";
 531                 status = "disabled";
 532         };
 533
 534         hsi2c_7: i2c@12CD0000 {
 535                 compatible = "samsung,exynos5-hsi2c";
 536                 reg = <0x12CD0000 0x1000>;
 537                 interrupts = <0 63 0>;
 538                 #address-cells = <1>;
 539                 #size-cells = <0>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c7_hs_bus>;
 542                 clocks = <&clock 268>;
 543                 clock-names = "hsi2c";
 544                 status = "disabled";
 545         };
 546
 547         hsi2c_8: i2c@12E00000 {
 548                 compatible = "samsung,exynos5-hsi2c";
 549                 reg = <0x12E00000 0x1000>;
 550                 interrupts = <0 87 0>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&i2c8_hs_bus>;
 555                 clocks = <&clock 281>;
 556                 clock-names = "hsi2c";
 557                 status = "disabled";
 558         };
 559
 560         hsi2c_9: i2c@12E10000 {
 561                 compatible = "samsung,exynos5-hsi2c";
 562                 reg = <0x12E10000 0x1000>;
 563                 interrupts = <0 88 0>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c9_hs_bus>;
 568                 clocks = <&clock 282>;
 569                 clock-names = "hsi2c";
 570                 status = "disabled";
 571         };
 572
 573         hsi2c_10: i2c@12E20000 {
 574                 compatible = "samsung,exynos5-hsi2c";
 575                 reg = <0x12E20000 0x1000>;
 576                 interrupts = <0 203 0>;
 577                 #address-cells = <1>;
 578                 #size-cells = <0>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c10_hs_bus>;
 581                 clocks = <&clock 283>;
 582                 clock-names = "hsi2c";
 583                 status = "disabled";
 584         };
 585
 586         hdmi@14530000 {
 587                 compatible = "samsung,exynos4212-hdmi";
 588                 reg = <0x14530000 0x70000>;
 589                 interrupts = <0 95 0>;
 590                 clocks = <&clock 413>, <&clock 143>, <&clock 768>,
 591                         <&clock 158>, <&clock 640>;
 592                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 593                         "sclk_hdmiphy", "mout_hdmi";
 594                 status = "disabled";
 595         };
 596
 597         mixer@14450000 {
 598                 compatible = "samsung,exynos5420-mixer";
 599                 reg = <0x14450000 0x10000>;
 600                 interrupts = <0 94 0>;
 601                 clocks = <&clock 431>, <&clock 143>;
 602                 clock-names = "mixer", "sclk_hdmi";
 603         };
 604
 605         gsc_0: video-scaler@13e00000 {
 606                 compatible = "samsung,exynos5-gsc";
 607                 reg = <0x13e00000 0x1000>;
 608                 interrupts = <0 85 0>;
 609                 clocks = <&clock 465>;
 610                 clock-names = "gscl";
 611                 samsung,power-domain = <&gsc_pd>;
 612         };
 613
 614         gsc_1: video-scaler@13e10000 {
 615                 compatible = "samsung,exynos5-gsc";
 616                 reg = <0x13e10000 0x1000>;
 617                 interrupts = <0 86 0>;
 618                 clocks = <&clock 466>;
 619                 clock-names = "gscl";
 620                 samsung,power-domain = <&gsc_pd>;
 621         };
 622
 623         tmu_cpu0: tmu@10060000 {
 624                 compatible = "samsung,exynos5420-tmu";
 625                 reg = <0x10060000 0x100>;
 626                 interrupts = <0 65 0>;
 627                 clocks = <&clock 318>;
 628                 clock-names = "tmu_apbif";
 629         };
 630
 631         tmu_cpu1: tmu@10064000 {
 632                 compatible = "samsung,exynos5420-tmu";
 633                 reg = <0x10064000 0x100>;
 634                 interrupts = <0 183 0>;
 635                 clocks = <&clock 318>;
 636                 clock-names = "tmu_apbif";
 637         };
 638
 639         tmu_cpu2: tmu@10068000 {
 640                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 641                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 642                 interrupts = <0 184 0>;
 643                 clocks = <&clock 318>, <&clock 318>;
 644                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 645         };
 646
 647         tmu_cpu3: tmu@1006c000 {
 648                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 649                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 650                 interrupts = <0 185 0>;
 651                 clocks = <&clock 318>, <&clock 319>;
 652                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 653         };
 654
 655         tmu_gpu: tmu@100a0000 {
 656                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 657                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 658                 interrupts = <0 215 0>;
 659                 clocks = <&clock 319>, <&clock 318>;
 660                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 661         };
 662 };