2 * SAMSUNG EXYNOS5410 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
8 * EXYNOS5410 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include "exynos54xx.dtsi"
17 #include "exynos-syscon-restart.dtsi"
18 #include <dt-bindings/clock/exynos5410.h>
19 #include <dt-bindings/clock/exynos-audss-clk.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 compatible = "samsung,exynos5410", "samsung,exynos5";
24 interrupt-parent = <&gic>;
27 pinctrl0 = &pinctrl_0;
28 pinctrl1 = &pinctrl_1;
29 pinctrl2 = &pinctrl_2;
30 pinctrl3 = &pinctrl_3;
39 compatible = "arm,cortex-a15";
41 clock-frequency = <1600000000>;
46 compatible = "arm,cortex-a15";
48 clock-frequency = <1600000000>;
53 compatible = "arm,cortex-a15";
55 clock-frequency = <1600000000>;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1600000000>;
67 compatible = "simple-bus";
72 pmu_system_controller: system-controller@10040000 {
73 compatible = "samsung,exynos5410-pmu", "syscon";
74 reg = <0x10040000 0x5000>;
75 clock-names = "clkout16";
79 #interrupt-cells = <3>;
80 interrupt-parent = <&gic>;
83 clock: clock-controller@10010000 {
84 compatible = "samsung,exynos5410-clock";
85 reg = <0x10010000 0x30000>;
89 clock_audss: audss-clock-controller@3810000 {
90 compatible = "samsung,exynos5410-audss-clock";
91 reg = <0x03810000 0x0C>;
93 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
94 clock-names = "pll_ref", "pll_in";
97 tmu_cpu0: tmu@10060000 {
98 compatible = "samsung,exynos5420-tmu";
99 reg = <0x10060000 0x100>;
100 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&clock CLK_TMU>;
102 clock-names = "tmu_apbif";
103 #include "exynos4412-tmu-sensor-conf.dtsi"
106 tmu_cpu1: tmu@10064000 {
107 compatible = "samsung,exynos5420-tmu";
108 reg = <0x10064000 0x100>;
109 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&clock CLK_TMU>;
111 clock-names = "tmu_apbif";
112 #include "exynos4412-tmu-sensor-conf.dtsi"
115 tmu_cpu2: tmu@10068000 {
116 compatible = "samsung,exynos5420-tmu";
117 reg = <0x10068000 0x100>;
118 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&clock CLK_TMU>;
120 clock-names = "tmu_apbif";
121 #include "exynos4412-tmu-sensor-conf.dtsi"
124 tmu_cpu3: tmu@1006c000 {
125 compatible = "samsung,exynos5420-tmu";
126 reg = <0x1006c000 0x100>;
127 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&clock CLK_TMU>;
129 clock-names = "tmu_apbif";
130 #include "exynos4412-tmu-sensor-conf.dtsi"
133 mmc_0: mmc@12200000 {
134 compatible = "samsung,exynos5250-dw-mshc";
135 reg = <0x12200000 0x1000>;
136 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
137 #address-cells = <1>;
139 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
140 clock-names = "biu", "ciu";
145 mmc_1: mmc@12210000 {
146 compatible = "samsung,exynos5250-dw-mshc";
147 reg = <0x12210000 0x1000>;
148 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
149 #address-cells = <1>;
151 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
152 clock-names = "biu", "ciu";
157 mmc_2: mmc@12220000 {
158 compatible = "samsung,exynos5250-dw-mshc";
159 reg = <0x12220000 0x1000>;
160 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
161 #address-cells = <1>;
163 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
164 clock-names = "biu", "ciu";
169 pinctrl_0: pinctrl@13400000 {
170 compatible = "samsung,exynos5410-pinctrl";
171 reg = <0x13400000 0x1000>;
172 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
174 wakeup-interrupt-controller {
175 compatible = "samsung,exynos4210-wakeup-eint";
176 interrupt-parent = <&gic>;
177 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl_1: pinctrl@14000000 {
182 compatible = "samsung,exynos5410-pinctrl";
183 reg = <0x14000000 0x1000>;
184 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
187 pinctrl_2: pinctrl@10d10000 {
188 compatible = "samsung,exynos5410-pinctrl";
189 reg = <0x10d10000 0x1000>;
190 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
193 pinctrl_3: pinctrl@3860000 {
194 compatible = "samsung,exynos5410-pinctrl";
195 reg = <0x03860000 0x1000>;
196 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
200 #address-cells = <1>;
202 compatible = "simple-bus";
203 interrupt-parent = <&gic>;
206 pdma0: pdma@12680000 {
207 compatible = "arm,pl330", "arm,primecell";
208 reg = <0x121A0000 0x1000>;
209 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clock CLK_PDMA0>;
211 clock-names = "apb_pclk";
214 #dma-requests = <32>;
217 pdma1: pdma@12690000 {
218 compatible = "arm,pl330", "arm,primecell";
219 reg = <0x121B0000 0x1000>;
220 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&clock CLK_PDMA1>;
222 clock-names = "apb_pclk";
225 #dma-requests = <32>;
229 audi2s0: i2s@3830000 {
230 compatible = "samsung,exynos5420-i2s";
231 reg = <0x03830000 0x100>;
235 dma-names = "tx", "rx", "tx-sec";
236 clocks = <&clock_audss EXYNOS_I2S_BUS>,
237 <&clock_audss EXYNOS_I2S_BUS>,
238 <&clock_audss EXYNOS_SCLK_I2S>;
239 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
241 clock-output-names = "i2s_cdclk0";
242 #sound-dai-cells = <1>;
243 samsung,idma-addr = <0x03000000>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&audi2s0_bus>;
251 cpu0_thermal: cpu0-thermal {
252 thermal-sensors = <&tmu_cpu0>;
253 #include "exynos5420-trip-points.dtsi"
255 cpu1_thermal: cpu1-thermal {
256 thermal-sensors = <&tmu_cpu1>;
257 #include "exynos5420-trip-points.dtsi"
259 cpu2_thermal: cpu2-thermal {
260 thermal-sensors = <&tmu_cpu2>;
261 #include "exynos5420-trip-points.dtsi"
263 cpu3_thermal: cpu3-thermal {
264 thermal-sensors = <&tmu_cpu3>;
265 #include "exynos5420-trip-points.dtsi"
271 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
276 clocks = <&clock CLK_I2C0>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c0_bus>;
283 clocks = <&clock CLK_I2C1>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c1_bus>;
290 clocks = <&clock CLK_I2C2>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&i2c2_bus>;
297 clocks = <&clock CLK_I2C3>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2c3_bus>;
304 clocks = <&clock CLK_USI0>;
305 clock-names = "hsi2c";
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c4_hs_bus>;
311 clocks = <&clock CLK_USI1>;
312 clock-names = "hsi2c";
313 pinctrl-names = "default";
314 pinctrl-0 = <&i2c5_hs_bus>;
318 clocks = <&clock CLK_USI2>;
319 clock-names = "hsi2c";
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c6_hs_bus>;
325 clocks = <&clock CLK_USI3>;
326 clock-names = "hsi2c";
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c7_hs_bus>;
332 clocks = <&fin_pll>, <&clock CLK_MCT>;
333 clock-names = "fin_pll", "mct";
337 clocks = <&clock CLK_SSS>;
338 clock-names = "secss";
342 clocks = <&clock CLK_PWM>;
343 clock-names = "timers";
347 clocks = <&clock CLK_RTC>;
349 interrupt-parent = <&pmu_system_controller>;
354 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
355 clock-names = "uart", "clk_uart_baud0";
356 dmas = <&pdma0 13>, <&pdma0 14>;
357 dma-names = "rx", "tx";
361 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
362 clock-names = "uart", "clk_uart_baud0";
363 dmas = <&pdma1 15>, <&pdma1 16>;
364 dma-names = "rx", "tx";
368 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
369 clock-names = "uart", "clk_uart_baud0";
370 dmas = <&pdma0 15>, <&pdma0 16>;
371 dma-names = "rx", "tx";
375 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
376 clock-names = "uart", "clk_uart_baud0";
377 dmas = <&pdma1 17>, <&pdma1 18>;
378 dma-names = "rx", "tx";
382 clocks = <&clock CLK_SSS>;
383 clock-names = "secss";
387 #address-cells = <2>;
389 ranges = <0 0 0x04000000 0x20000
390 1 0 0x05000000 0x20000
391 2 0 0x06000000 0x20000
392 3 0 0x07000000 0x20000>;
396 clocks = <&clock CLK_USBD300>;
397 clock-names = "usbdrd30";
401 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
402 clock-names = "phy", "ref";
403 samsung,pmu-syscon = <&pmu_system_controller>;
407 clocks = <&clock CLK_USBD301>;
408 clock-names = "usbdrd30";
412 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
417 clock-names = "phy", "ref";
418 samsung,pmu-syscon = <&pmu_system_controller>;
422 clocks = <&clock CLK_USBH20>;
423 clock-names = "usbhost";
427 clocks = <&clock CLK_USBH20>;
428 clock-names = "usbhost";
432 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
433 clock-names = "phy", "ref";
434 samsung,sysreg-phandle = <&sysreg_system_controller>;
435 samsung,pmureg-phandle = <&pmu_system_controller>;
439 clocks = <&clock CLK_WDT>;
440 clock-names = "watchdog";
441 samsung,syscon-phandle = <&pmu_system_controller>;
444 #include "exynos5410-pinctrl.dtsi"