arch/arm/boot/dts/exynos5410.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5410 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   8  * EXYNOS5410 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos54xx.dtsi"
  17 #include "exynos-syscon-restart.dtsi"
  18 #include <dt-bindings/clock/exynos5410.h>
  19 #include <dt-bindings/clock/exynos-audss-clk.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21
  22 / {
  23         compatible = "samsung,exynos5410", "samsung,exynos5";
  24         interrupt-parent = <&gic>;
  25
  26         aliases {
  27                 pinctrl0 = &pinctrl_0;
  28                 pinctrl1 = &pinctrl_1;
  29                 pinctrl2 = &pinctrl_2;
  30                 pinctrl3 = &pinctrl_3;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu0: cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a15";
  40                         reg = <0x0>;
  41                         clock-frequency = <1600000000>;
  42                 };
  43
  44                 cpu1: cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a15";
  47                         reg = <0x1>;
  48                         clock-frequency = <1600000000>;
  49                 };
  50
  51                 cpu2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <0x2>;
  55                         clock-frequency = <1600000000>;
  56                 };
  57
  58                 cpu3: cpu@3 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a15";
  61                         reg = <0x3>;
  62                         clock-frequency = <1600000000>;
  63                 };
  64         };
  65
  66         soc: soc {
  67                 compatible = "simple-bus";
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 ranges;
  71
  72                 pmu_system_controller: system-controller@10040000 {
  73                         compatible = "samsung,exynos5410-pmu", "syscon";
  74                         reg = <0x10040000 0x5000>;
  75                         clock-names = "clkout16";
  76                         clocks = <&fin_pll>;
  77                         #clock-cells = <1>;
  78                         interrupt-controller;
  79                         #interrupt-cells = <3>;
  80                         interrupt-parent = <&gic>;
  81                 };
  82
  83                 clock: clock-controller@10010000 {
  84                         compatible = "samsung,exynos5410-clock";
  85                         reg = <0x10010000 0x30000>;
  86                         #clock-cells = <1>;
  87                 };
  88
  89                 clock_audss: audss-clock-controller@3810000 {
  90                         compatible = "samsung,exynos5410-audss-clock";
  91                         reg = <0x03810000 0x0C>;
  92                         #clock-cells = <1>;
  93                         clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
  94                         clock-names = "pll_ref", "pll_in";
  95                 };
  96
  97                 tmu_cpu0: tmu@10060000 {
  98                         compatible = "samsung,exynos5420-tmu";
  99                         reg = <0x10060000 0x100>;
 100                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 101                         clocks = <&clock CLK_TMU>;
 102                         clock-names = "tmu_apbif";
 103                         #include "exynos4412-tmu-sensor-conf.dtsi"
 104                 };
 105
 106                 tmu_cpu1: tmu@10064000 {
 107                         compatible = "samsung,exynos5420-tmu";
 108                         reg = <0x10064000 0x100>;
 109                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 110                         clocks = <&clock CLK_TMU>;
 111                         clock-names = "tmu_apbif";
 112                         #include "exynos4412-tmu-sensor-conf.dtsi"
 113                 };
 114
 115                 tmu_cpu2: tmu@10068000 {
 116                         compatible = "samsung,exynos5420-tmu";
 117                         reg = <0x10068000 0x100>;
 118                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&clock CLK_TMU>;
 120                         clock-names = "tmu_apbif";
 121                         #include "exynos4412-tmu-sensor-conf.dtsi"
 122                 };
 123
 124                 tmu_cpu3: tmu@1006c000 {
 125                         compatible = "samsung,exynos5420-tmu";
 126                         reg = <0x1006c000 0x100>;
 127                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 128                         clocks = <&clock CLK_TMU>;
 129                         clock-names = "tmu_apbif";
 130                         #include "exynos4412-tmu-sensor-conf.dtsi"
 131                 };
 132
 133                 mmc_0: mmc@12200000 {
 134                         compatible = "samsung,exynos5250-dw-mshc";
 135                         reg = <0x12200000 0x1000>;
 136                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 140                         clock-names = "biu", "ciu";
 141                         fifo-depth = <0x80>;
 142                         status = "disabled";
 143                 };
 144
 145                 mmc_1: mmc@12210000 {
 146                         compatible = "samsung,exynos5250-dw-mshc";
 147                         reg = <0x12210000 0x1000>;
 148                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 152                         clock-names = "biu", "ciu";
 153                         fifo-depth = <0x80>;
 154                         status = "disabled";
 155                 };
 156
 157                 mmc_2: mmc@12220000 {
 158                         compatible = "samsung,exynos5250-dw-mshc";
 159                         reg = <0x12220000 0x1000>;
 160                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 164                         clock-names = "biu", "ciu";
 165                         fifo-depth = <0x80>;
 166                         status = "disabled";
 167                 };
 168
 169                 pinctrl_0: pinctrl@13400000 {
 170                         compatible = "samsung,exynos5410-pinctrl";
 171                         reg = <0x13400000 0x1000>;
 172                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 173
 174                         wakeup-interrupt-controller {
 175                                 compatible = "samsung,exynos4210-wakeup-eint";
 176                                 interrupt-parent = <&gic>;
 177                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 178                         };
 179                 };
 180
 181                 pinctrl_1: pinctrl@14000000 {
 182                         compatible = "samsung,exynos5410-pinctrl";
 183                         reg = <0x14000000 0x1000>;
 184                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 185                 };
 186
 187                 pinctrl_2: pinctrl@10d10000 {
 188                         compatible = "samsung,exynos5410-pinctrl";
 189                         reg = <0x10d10000 0x1000>;
 190                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 191                 };
 192
 193                 pinctrl_3: pinctrl@3860000 {
 194                         compatible = "samsung,exynos5410-pinctrl";
 195                         reg = <0x03860000 0x1000>;
 196                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 197                 };
 198
 199                 amba {
 200                         #address-cells = <1>;
 201                         #size-cells = <1>;
 202                         compatible = "simple-bus";
 203                         interrupt-parent = <&gic>;
 204                         ranges;
 205
 206                         pdma0: pdma@12680000 {
 207                                 compatible = "arm,pl330", "arm,primecell";
 208                                 reg = <0x121A0000 0x1000>;
 209                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 210                                 clocks = <&clock CLK_PDMA0>;
 211                                 clock-names = "apb_pclk";
 212                                 #dma-cells = <1>;
 213                                 #dma-channels = <8>;
 214                                 #dma-requests = <32>;
 215                         };
 216
 217                         pdma1: pdma@12690000 {
 218                                 compatible = "arm,pl330", "arm,primecell";
 219                                 reg = <0x121B0000 0x1000>;
 220                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 221                                 clocks = <&clock CLK_PDMA1>;
 222                                 clock-names = "apb_pclk";
 223                                 #dma-cells = <1>;
 224                                 #dma-channels = <8>;
 225                                 #dma-requests = <32>;
 226                         };
 227                 };
 228
 229                 audi2s0: i2s@3830000 {
 230                         compatible = "samsung,exynos5420-i2s";
 231                         reg = <0x03830000 0x100>;
 232                         dmas = <&pdma0 10
 233                                 &pdma0 9
 234                                 &pdma0 8>;
 235                         dma-names = "tx", "rx", "tx-sec";
 236                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 237                                 <&clock_audss EXYNOS_I2S_BUS>,
 238                                 <&clock_audss EXYNOS_SCLK_I2S>;
 239                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 240                         #clock-cells = <1>;
 241                         clock-output-names = "i2s_cdclk0";
 242                         #sound-dai-cells = <1>;
 243                         samsung,idma-addr = <0x03000000>;
 244                         pinctrl-names = "default";
 245                         pinctrl-0 = <&audi2s0_bus>;
 246                         status = "disabled";
 247                 };
 248         };
 249
 250         thermal-zones {
 251                 cpu0_thermal: cpu0-thermal {
 252                         thermal-sensors = <&tmu_cpu0>;
 253                         #include "exynos5420-trip-points.dtsi"
 254                 };
 255                 cpu1_thermal: cpu1-thermal {
 256                        thermal-sensors = <&tmu_cpu1>;
 257                        #include "exynos5420-trip-points.dtsi"
 258                 };
 259                 cpu2_thermal: cpu2-thermal {
 260                        thermal-sensors = <&tmu_cpu2>;
 261                        #include "exynos5420-trip-points.dtsi"
 262                 };
 263                 cpu3_thermal: cpu3-thermal {
 264                        thermal-sensors = <&tmu_cpu3>;
 265                        #include "exynos5420-trip-points.dtsi"
 266                 };
 267         };
 268 };
 269
 270 &arm_a15_pmu {
 271         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 272         status = "okay";
 273 };
 274
 275 &i2c_0 {
 276         clocks = <&clock CLK_I2C0>;
 277         clock-names = "i2c";
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&i2c0_bus>;
 280 };
 281
 282 &i2c_1 {
 283         clocks = <&clock CLK_I2C1>;
 284         clock-names = "i2c";
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&i2c1_bus>;
 287 };
 288
 289 &i2c_2 {
 290         clocks = <&clock CLK_I2C2>;
 291         clock-names = "i2c";
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&i2c2_bus>;
 294 };
 295
 296 &i2c_3 {
 297         clocks = <&clock CLK_I2C3>;
 298         clock-names = "i2c";
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&i2c3_bus>;
 301 };
 302
 303 &hsi2c_4 {
 304         clocks = <&clock CLK_USI0>;
 305         clock-names = "hsi2c";
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&i2c4_hs_bus>;
 308 };
 309
 310 &hsi2c_5 {
 311         clocks = <&clock CLK_USI1>;
 312         clock-names = "hsi2c";
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&i2c5_hs_bus>;
 315 };
 316
 317 &hsi2c_6 {
 318         clocks = <&clock CLK_USI2>;
 319         clock-names = "hsi2c";
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&i2c6_hs_bus>;
 322 };
 323
 324 &hsi2c_7 {
 325         clocks = <&clock CLK_USI3>;
 326         clock-names = "hsi2c";
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&i2c7_hs_bus>;
 329 };
 330
 331 &mct {
 332         clocks = <&fin_pll>, <&clock CLK_MCT>;
 333         clock-names = "fin_pll", "mct";
 334 };
 335
 336 &pwm {
 337         clocks = <&clock CLK_PWM>;
 338         clock-names = "timers";
 339 };
 340
 341 &rtc {
 342         clocks = <&clock CLK_RTC>;
 343         clock-names = "rtc";
 344         interrupt-parent = <&pmu_system_controller>;
 345         status = "disabled";
 346 };
 347
 348 &serial_0 {
 349         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 350         clock-names = "uart", "clk_uart_baud0";
 351         dmas = <&pdma0 13>, <&pdma0 14>;
 352         dma-names = "rx", "tx";
 353 };
 354
 355 &serial_1 {
 356         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 357         clock-names = "uart", "clk_uart_baud0";
 358         dmas = <&pdma1 15>, <&pdma1 16>;
 359         dma-names = "rx", "tx";
 360 };
 361
 362 &serial_2 {
 363         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 364         clock-names = "uart", "clk_uart_baud0";
 365         dmas = <&pdma0 15>, <&pdma0 16>;
 366         dma-names = "rx", "tx";
 367 };
 368
 369 &serial_3 {
 370         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 371         clock-names = "uart", "clk_uart_baud0";
 372         dmas = <&pdma1 17>, <&pdma1 18>;
 373         dma-names = "rx", "tx";
 374 };
 375
 376 &sss {
 377         clocks = <&clock CLK_SSS>;
 378         clock-names = "secss";
 379 };
 380
 381 &sromc {
 382         #address-cells = <2>;
 383         #size-cells = <1>;
 384         ranges = <0 0 0x04000000 0x20000
 385                   1 0 0x05000000 0x20000
 386                   2 0 0x06000000 0x20000
 387                   3 0 0x07000000 0x20000>;
 388 };
 389
 390 &usbdrd3_0 {
 391         clocks = <&clock CLK_USBD300>;
 392         clock-names = "usbdrd30";
 393 };
 394
 395 &usbdrd_phy0 {
 396         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 397         clock-names = "phy", "ref";
 398         samsung,pmu-syscon = <&pmu_system_controller>;
 399 };
 400
 401 &usbdrd3_1 {
 402         clocks = <&clock CLK_USBD301>;
 403         clock-names = "usbdrd30";
 404 };
 405
 406 &usbdrd_dwc3_1 {
 407         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 408 };
 409
 410 &usbdrd_phy1 {
 411         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 412         clock-names = "phy", "ref";
 413         samsung,pmu-syscon = <&pmu_system_controller>;
 414 };
 415
 416 &usbhost1 {
 417         clocks = <&clock CLK_USBH20>;
 418         clock-names = "usbhost";
 419 };
 420
 421 &usbhost2 {
 422         clocks = <&clock CLK_USBH20>;
 423         clock-names = "usbhost";
 424 };
 425
 426 &usb2_phy {
 427         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 428         clock-names = "phy", "ref";
 429         samsung,sysreg-phandle = <&sysreg_system_controller>;
 430         samsung,pmureg-phandle = <&pmu_system_controller>;
 431 };
 432
 433 &watchdog {
 434         clocks = <&clock CLK_WDT>;
 435         clock-names = "watchdog";
 436         samsung,syscon-phandle = <&pmu_system_controller>;
 437 };
 438
 439 #include "exynos5410-pinctrl.dtsi"