arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos4-cpu-thermal.dtsi"
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24
  25 / {
  26         compatible = "samsung,exynos5250", "samsung,exynos5";
  27
  28         aliases {
  29                 spi0 = &spi_0;
  30                 spi1 = &spi_1;
  31                 spi2 = &spi_2;
  32                 gsc0 = &gsc_0;
  33                 gsc1 = &gsc_1;
  34                 gsc2 = &gsc_2;
  35                 gsc3 = &gsc_3;
  36                 mshc0 = &mmc_0;
  37                 mshc1 = &mmc_1;
  38                 mshc2 = &mmc_2;
  39                 mshc3 = &mmc_3;
  40                 i2c4 = &i2c_4;
  41                 i2c5 = &i2c_5;
  42                 i2c6 = &i2c_6;
  43                 i2c7 = &i2c_7;
  44                 i2c8 = &i2c_8;
  45                 i2c9 = &i2c_9;
  46                 pinctrl0 = &pinctrl_0;
  47                 pinctrl1 = &pinctrl_1;
  48                 pinctrl2 = &pinctrl_2;
  49                 pinctrl3 = &pinctrl_3;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0>;
  60                         clock-frequency = <1700000000>;
  61                         clocks = <&clock CLK_ARM_CLK>;
  62                         clock-names = "cpu";
  63                         clock-latency = <140000>;
  64
  65                         operating-points = <
  66                                 1700000 1300000
  67                                 1600000 1250000
  68                                 1500000 1225000
  69                                 1400000 1200000
  70                                 1300000 1150000
  71                                 1200000 1125000
  72                                 1100000 1100000
  73                                 1000000 1075000
  74                                  900000 1050000
  75                                  800000 1025000
  76                                  700000 1012500
  77                                  600000 1000000
  78                                  500000  975000
  79                                  400000  950000
  80                                  300000  937500
  81                                  200000  925000
  82                         >;
  83                         cooling-min-level = <15>;
  84                         cooling-max-level = <9>;
  85                         #cooling-cells = <2>; /* min followed by max */
  86                 };
  87                 cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a15";
  90                         reg = <1>;
  91                         clock-frequency = <1700000000>;
  92                 };
  93         };
  94
  95         soc: soc {
  96                 sysram@2020000 {
  97                         compatible = "mmio-sram";
  98                         reg = <0x02020000 0x30000>;
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges = <0 0x02020000 0x30000>;
 102
 103                         smp-sysram@0 {
 104                                 compatible = "samsung,exynos4210-sysram";
 105                                 reg = <0x0 0x1000>;
 106                         };
 107
 108                         smp-sysram@2f000 {
 109                                 compatible = "samsung,exynos4210-sysram-ns";
 110                                 reg = <0x2f000 0x1000>;
 111                         };
 112                 };
 113
 114                 pd_gsc: power-domain@10044000 {
 115                         compatible = "samsung,exynos4210-pd";
 116                         reg = <0x10044000 0x20>;
 117                         #power-domain-cells = <0>;
 118                         label = "GSC";
 119                 };
 120
 121                 pd_mfc: power-domain@10044040 {
 122                         compatible = "samsung,exynos4210-pd";
 123                         reg = <0x10044040 0x20>;
 124                         #power-domain-cells = <0>;
 125                         label = "MFC";
 126                 };
 127
 128                 pd_g3d: power-domain@10044060 {
 129                         compatible = "samsung,exynos4210-pd";
 130                         reg = <0x10044060 0x20>;
 131                         #power-domain-cells = <0>;
 132                         label = "G3D";
 133                 };
 134
 135                 pd_disp1: power-domain@100440A0 {
 136                         compatible = "samsung,exynos4210-pd";
 137                         reg = <0x100440A0 0x20>;
 138                         #power-domain-cells = <0>;
 139                         label = "DISP1";
 140                         clocks = <&clock CLK_FIN_PLL>,
 141                                  <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
 142                                  <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
 143                         clock-names = "oscclk", "clk0", "clk1";
 144                 };
 145
 146                 pd_mau: power-domain@100440C0 {
 147                         compatible = "samsung,exynos4210-pd";
 148                         reg = <0x100440C0 0x20>;
 149                         #power-domain-cells = <0>;
 150                         label = "MAU";
 151                 };
 152
 153                 clock: clock-controller@10010000 {
 154                         compatible = "samsung,exynos5250-clock";
 155                         reg = <0x10010000 0x30000>;
 156                         #clock-cells = <1>;
 157                 };
 158
 159                 clock_audss: audss-clock-controller@3810000 {
 160                         compatible = "samsung,exynos5250-audss-clock";
 161                         reg = <0x03810000 0x0C>;
 162                         #clock-cells = <1>;
 163                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 164                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 165                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 166                         power-domains = <&pd_mau>;
 167                 };
 168
 169                 timer {
 170                         compatible = "arm,armv7-timer";
 171                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 172                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 173                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 174                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 175                         /*
 176                          * Unfortunately we need this since some versions
 177                          * of U-Boot on Exynos don't set the CNTFRQ register,
 178                          * so we need the value from DT.
 179                          */
 180                         clock-frequency = <24000000>;
 181                 };
 182
 183                 mct@101C0000 {
 184                         compatible = "samsung,exynos4210-mct";
 185                         reg = <0x101C0000 0x800>;
 186                         interrupt-controller;
 187                         #interrupt-cells = <2>;
 188                         interrupt-parent = <&mct_map>;
 189                         interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 190                                      <4 0>, <5 0>;
 191                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 192                         clock-names = "fin_pll", "mct";
 193
 194                         mct_map: mct-map {
 195                                 #interrupt-cells = <2>;
 196                                 #address-cells = <0>;
 197                                 #size-cells = <0>;
 198                                 interrupt-map = <0x0 0 &combiner 23 3>,
 199                                                 <0x1 0 &combiner 23 4>,
 200                                                 <0x2 0 &combiner 25 2>,
 201                                                 <0x3 0 &combiner 25 3>,
 202                                                 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
 203                                                 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
 204                         };
 205                 };
 206
 207                 pmu {
 208                         compatible = "arm,cortex-a15-pmu";
 209                         interrupt-parent = <&combiner>;
 210                         interrupts = <1 2>, <22 4>;
 211                 };
 212
 213                 pinctrl_0: pinctrl@11400000 {
 214                         compatible = "samsung,exynos5250-pinctrl";
 215                         reg = <0x11400000 0x1000>;
 216                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 217
 218                         wakup_eint: wakeup-interrupt-controller {
 219                                 compatible = "samsung,exynos4210-wakeup-eint";
 220                                 interrupt-parent = <&gic>;
 221                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 222                         };
 223                 };
 224
 225                 pinctrl_1: pinctrl@13400000 {
 226                         compatible = "samsung,exynos5250-pinctrl";
 227                         reg = <0x13400000 0x1000>;
 228                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 229                 };
 230
 231                 pinctrl_2: pinctrl@10d10000 {
 232                         compatible = "samsung,exynos5250-pinctrl";
 233                         reg = <0x10d10000 0x1000>;
 234                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 235                 };
 236
 237                 pinctrl_3: pinctrl@3860000 {
 238                         compatible = "samsung,exynos5250-pinctrl";
 239                         reg = <0x03860000 0x1000>;
 240                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 241                         power-domains = <&pd_mau>;
 242                 };
 243
 244                 pmu_system_controller: system-controller@10040000 {
 245                         compatible = "samsung,exynos5250-pmu", "syscon";
 246                         reg = <0x10040000 0x5000>;
 247                         clock-names = "clkout16";
 248                         clocks = <&clock CLK_FIN_PLL>;
 249                         #clock-cells = <1>;
 250                         interrupt-controller;
 251                         #interrupt-cells = <3>;
 252                         interrupt-parent = <&gic>;
 253                 };
 254
 255                 watchdog@101D0000 {
 256                         compatible = "samsung,exynos5250-wdt";
 257                         reg = <0x101D0000 0x100>;
 258                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 259                         clocks = <&clock CLK_WDT>;
 260                         clock-names = "watchdog";
 261                         samsung,syscon-phandle = <&pmu_system_controller>;
 262                 };
 263
 264                 mfc: codec@11000000 {
 265                         compatible = "samsung,mfc-v6";
 266                         reg = <0x11000000 0x10000>;
 267                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 268                         power-domains = <&pd_mfc>;
 269                         clocks = <&clock CLK_MFC>;
 270                         clock-names = "mfc";
 271                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 272                         iommu-names = "left", "right";
 273                 };
 274
 275                 rotator: rotator@11C00000 {
 276                         compatible = "samsung,exynos5250-rotator";
 277                         reg = <0x11C00000 0x64>;
 278                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&clock CLK_ROTATOR>;
 280                         clock-names = "rotator";
 281                         iommus = <&sysmmu_rotator>;
 282                 };
 283
 284                 tmu: tmu@10060000 {
 285                         compatible = "samsung,exynos5250-tmu";
 286                         reg = <0x10060000 0x100>;
 287                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&clock CLK_TMU>;
 289                         clock-names = "tmu_apbif";
 290                         #include "exynos4412-tmu-sensor-conf.dtsi"
 291                 };
 292
 293                 sata: sata@122F0000 {
 294                         compatible = "snps,dwc-ahci";
 295                         samsung,sata-freq = <66>;
 296                         reg = <0x122F0000 0x1ff>;
 297                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 298                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 299                         clock-names = "sata", "sclk_sata";
 300                         phys = <&sata_phy>;
 301                         phy-names = "sata-phy";
 302                         status = "disabled";
 303                 };
 304
 305                 sata_phy: sata-phy@12170000 {
 306                         compatible = "samsung,exynos5250-sata-phy";
 307                         reg = <0x12170000 0x1ff>;
 308                         clocks = <&clock CLK_SATA_PHYCTRL>;
 309                         clock-names = "sata_phyctrl";
 310                         #phy-cells = <0>;
 311                         samsung,syscon-phandle = <&pmu_system_controller>;
 312                         status = "disabled";
 313                 };
 314
 315                 /* i2c_0-3 are defined in exynos5.dtsi */
 316                 i2c_4: i2c@12CA0000 {
 317                         compatible = "samsung,s3c2440-i2c";
 318                         reg = <0x12CA0000 0x100>;
 319                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         clocks = <&clock CLK_I2C4>;
 323                         clock-names = "i2c";
 324                         pinctrl-names = "default";
 325                         pinctrl-0 = <&i2c4_bus>;
 326                         status = "disabled";
 327                 };
 328
 329                 i2c_5: i2c@12CB0000 {
 330                         compatible = "samsung,s3c2440-i2c";
 331                         reg = <0x12CB0000 0x100>;
 332                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         clocks = <&clock CLK_I2C5>;
 336                         clock-names = "i2c";
 337                         pinctrl-names = "default";
 338                         pinctrl-0 = <&i2c5_bus>;
 339                         status = "disabled";
 340                 };
 341
 342                 i2c_6: i2c@12CC0000 {
 343                         compatible = "samsung,s3c2440-i2c";
 344                         reg = <0x12CC0000 0x100>;
 345                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         clocks = <&clock CLK_I2C6>;
 349                         clock-names = "i2c";
 350                         pinctrl-names = "default";
 351                         pinctrl-0 = <&i2c6_bus>;
 352                         status = "disabled";
 353                 };
 354
 355                 i2c_7: i2c@12CD0000 {
 356                         compatible = "samsung,s3c2440-i2c";
 357                         reg = <0x12CD0000 0x100>;
 358                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         clocks = <&clock CLK_I2C7>;
 362                         clock-names = "i2c";
 363                         pinctrl-names = "default";
 364                         pinctrl-0 = <&i2c7_bus>;
 365                         status = "disabled";
 366                 };
 367
 368                 i2c_8: i2c@12CE0000 {
 369                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 370                         reg = <0x12CE0000 0x1000>;
 371                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         clocks = <&clock CLK_I2C_HDMI>;
 375                         clock-names = "i2c";
 376                         status = "disabled";
 377
 378                         hdmiphy: hdmiphy@38 {
 379                                 compatible = "samsung,exynos4212-hdmiphy";
 380                                 reg = <0x38>;
 381                         };
 382                 };
 383
 384                 i2c_9: i2c@121D0000 {
 385                         compatible = "samsung,exynos5-sata-phy-i2c";
 386                         reg = <0x121D0000 0x100>;
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         clocks = <&clock CLK_SATA_PHYI2C>;
 390                         clock-names = "i2c";
 391                         status = "disabled";
 392                 };
 393
 394                 spi_0: spi@12d20000 {
 395                         compatible = "samsung,exynos4210-spi";
 396                         status = "disabled";
 397                         reg = <0x12d20000 0x100>;
 398                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 399                         dmas = <&pdma0 5
 400                                 &pdma0 4>;
 401                         dma-names = "tx", "rx";
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 405                         clock-names = "spi", "spi_busclk0";
 406                         pinctrl-names = "default";
 407                         pinctrl-0 = <&spi0_bus>;
 408                 };
 409
 410                 spi_1: spi@12d30000 {
 411                         compatible = "samsung,exynos4210-spi";
 412                         status = "disabled";
 413                         reg = <0x12d30000 0x100>;
 414                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 415                         dmas = <&pdma1 5
 416                                 &pdma1 4>;
 417                         dma-names = "tx", "rx";
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 421                         clock-names = "spi", "spi_busclk0";
 422                         pinctrl-names = "default";
 423                         pinctrl-0 = <&spi1_bus>;
 424                 };
 425
 426                 spi_2: spi@12d40000 {
 427                         compatible = "samsung,exynos4210-spi";
 428                         status = "disabled";
 429                         reg = <0x12d40000 0x100>;
 430                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 431                         dmas = <&pdma0 7
 432                                 &pdma0 6>;
 433                         dma-names = "tx", "rx";
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 437                         clock-names = "spi", "spi_busclk0";
 438                         pinctrl-names = "default";
 439                         pinctrl-0 = <&spi2_bus>;
 440                 };
 441
 442                 mmc_0: mmc@12200000 {
 443                         compatible = "samsung,exynos5250-dw-mshc";
 444                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         reg = <0x12200000 0x1000>;
 448                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 449                         clock-names = "biu", "ciu";
 450                         fifo-depth = <0x80>;
 451                         status = "disabled";
 452                 };
 453
 454                 mmc_1: mmc@12210000 {
 455                         compatible = "samsung,exynos5250-dw-mshc";
 456                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         reg = <0x12210000 0x1000>;
 460                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 461                         clock-names = "biu", "ciu";
 462                         fifo-depth = <0x80>;
 463                         status = "disabled";
 464                 };
 465
 466                 mmc_2: mmc@12220000 {
 467                         compatible = "samsung,exynos5250-dw-mshc";
 468                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         reg = <0x12220000 0x1000>;
 472                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 473                         clock-names = "biu", "ciu";
 474                         fifo-depth = <0x80>;
 475                         status = "disabled";
 476                 };
 477
 478                 mmc_3: mmc@12230000 {
 479                         compatible = "samsung,exynos5250-dw-mshc";
 480                         reg = <0x12230000 0x1000>;
 481                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 485                         clock-names = "biu", "ciu";
 486                         fifo-depth = <0x80>;
 487                         status = "disabled";
 488                 };
 489
 490                 i2s0: i2s@3830000 {
 491                         compatible = "samsung,s5pv210-i2s";
 492                         status = "disabled";
 493                         reg = <0x03830000 0x100>;
 494                         dmas = <&pdma0 10
 495                                 &pdma0 9
 496                                 &pdma0 8>;
 497                         dma-names = "tx", "rx", "tx-sec";
 498                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 499                                 <&clock_audss EXYNOS_I2S_BUS>,
 500                                 <&clock_audss EXYNOS_SCLK_I2S>;
 501                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 502                         samsung,idma-addr = <0x03000000>;
 503                         pinctrl-names = "default";
 504                         pinctrl-0 = <&i2s0_bus>;
 505                         power-domains = <&pd_mau>;
 506                 };
 507
 508                 i2s1: i2s@12D60000 {
 509                         compatible = "samsung,s3c6410-i2s";
 510                         status = "disabled";
 511                         reg = <0x12D60000 0x100>;
 512                         dmas = <&pdma1 12
 513                                 &pdma1 11>;
 514                         dma-names = "tx", "rx";
 515                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 516                         clock-names = "iis", "i2s_opclk0";
 517                         pinctrl-names = "default";
 518                         pinctrl-0 = <&i2s1_bus>;
 519                         power-domains = <&pd_mau>;
 520                 };
 521
 522                 i2s2: i2s@12D70000 {
 523                         compatible = "samsung,s3c6410-i2s";
 524                         status = "disabled";
 525                         reg = <0x12D70000 0x100>;
 526                         dmas = <&pdma0 12
 527                                 &pdma0 11>;
 528                         dma-names = "tx", "rx";
 529                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 530                         clock-names = "iis", "i2s_opclk0";
 531                         pinctrl-names = "default";
 532                         pinctrl-0 = <&i2s2_bus>;
 533                         power-domains = <&pd_mau>;
 534                 };
 535
 536                 usb_dwc3 {
 537                         compatible = "samsung,exynos5250-dwusb3";
 538                         clocks = <&clock CLK_USB3>;
 539                         clock-names = "usbdrd30";
 540                         #address-cells = <1>;
 541                         #size-cells = <1>;
 542                         ranges;
 543
 544                         usbdrd_dwc3: dwc3@12000000 {
 545                                 compatible = "synopsys,dwc3";
 546                                 reg = <0x12000000 0x10000>;
 547                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 548                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 549                                 phy-names = "usb2-phy", "usb3-phy";
 550                         };
 551                 };
 552
 553                 usbdrd_phy: phy@12100000 {
 554                         compatible = "samsung,exynos5250-usbdrd-phy";
 555                         reg = <0x12100000 0x100>;
 556                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 557                         clock-names = "phy", "ref";
 558                         samsung,pmu-syscon = <&pmu_system_controller>;
 559                         #phy-cells = <1>;
 560                 };
 561
 562                 ehci: usb@12110000 {
 563                         compatible = "samsung,exynos4210-ehci";
 564                         reg = <0x12110000 0x100>;
 565                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 566
 567                         clocks = <&clock CLK_USB2>;
 568                         clock-names = "usbhost";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                         port@0 {
 572                                 reg = <0>;
 573                                 phys = <&usb2_phy_gen 1>;
 574                         };
 575                 };
 576
 577                 ohci: usb@12120000 {
 578                         compatible = "samsung,exynos4210-ohci";
 579                         reg = <0x12120000 0x100>;
 580                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 581
 582                         clocks = <&clock CLK_USB2>;
 583                         clock-names = "usbhost";
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         port@0 {
 587                                 reg = <0>;
 588                                 phys = <&usb2_phy_gen 1>;
 589                         };
 590                 };
 591
 592                 usb2_phy_gen: phy@12130000 {
 593                         compatible = "samsung,exynos5250-usb2-phy";
 594                         reg = <0x12130000 0x100>;
 595                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 596                         clock-names = "phy", "ref";
 597                         #phy-cells = <1>;
 598                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 599                         samsung,pmureg-phandle = <&pmu_system_controller>;
 600                 };
 601
 602                 amba {
 603                         #address-cells = <1>;
 604                         #size-cells = <1>;
 605                         compatible = "simple-bus";
 606                         interrupt-parent = <&gic>;
 607                         ranges;
 608
 609                         pdma0: pdma@121A0000 {
 610                                 compatible = "arm,pl330", "arm,primecell";
 611                                 reg = <0x121A0000 0x1000>;
 612                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 613                                 clocks = <&clock CLK_PDMA0>;
 614                                 clock-names = "apb_pclk";
 615                                 #dma-cells = <1>;
 616                                 #dma-channels = <8>;
 617                                 #dma-requests = <32>;
 618                         };
 619
 620                         pdma1: pdma@121B0000 {
 621                                 compatible = "arm,pl330", "arm,primecell";
 622                                 reg = <0x121B0000 0x1000>;
 623                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 624                                 clocks = <&clock CLK_PDMA1>;
 625                                 clock-names = "apb_pclk";
 626                                 #dma-cells = <1>;
 627                                 #dma-channels = <8>;
 628                                 #dma-requests = <32>;
 629                         };
 630
 631                         mdma0: mdma@10800000 {
 632                                 compatible = "arm,pl330", "arm,primecell";
 633                                 reg = <0x10800000 0x1000>;
 634                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 635                                 clocks = <&clock CLK_MDMA0>;
 636                                 clock-names = "apb_pclk";
 637                                 #dma-cells = <1>;
 638                                 #dma-channels = <8>;
 639                                 #dma-requests = <1>;
 640                         };
 641
 642                         mdma1: mdma@11C10000 {
 643                                 compatible = "arm,pl330", "arm,primecell";
 644                                 reg = <0x11C10000 0x1000>;
 645                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 646                                 clocks = <&clock CLK_MDMA1>;
 647                                 clock-names = "apb_pclk";
 648                                 #dma-cells = <1>;
 649                                 #dma-channels = <8>;
 650                                 #dma-requests = <1>;
 651                         };
 652                 };
 653
 654                 gsc_0:  gsc@13e00000 {
 655                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 656                         reg = <0x13e00000 0x1000>;
 657                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 658                         power-domains = <&pd_gsc>;
 659                         clocks = <&clock CLK_GSCL0>;
 660                         clock-names = "gscl";
 661                         iommu = <&sysmmu_gsc0>;
 662                 };
 663
 664                 gsc_1:  gsc@13e10000 {
 665                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 666                         reg = <0x13e10000 0x1000>;
 667                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 668                         power-domains = <&pd_gsc>;
 669                         clocks = <&clock CLK_GSCL1>;
 670                         clock-names = "gscl";
 671                         iommu = <&sysmmu_gsc1>;
 672                 };
 673
 674                 gsc_2:  gsc@13e20000 {
 675                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 676                         reg = <0x13e20000 0x1000>;
 677                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 678                         power-domains = <&pd_gsc>;
 679                         clocks = <&clock CLK_GSCL2>;
 680                         clock-names = "gscl";
 681                         iommu = <&sysmmu_gsc2>;
 682                 };
 683
 684                 gsc_3:  gsc@13e30000 {
 685                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 686                         reg = <0x13e30000 0x1000>;
 687                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 688                         power-domains = <&pd_gsc>;
 689                         clocks = <&clock CLK_GSCL3>;
 690                         clock-names = "gscl";
 691                         iommu = <&sysmmu_gsc3>;
 692                 };
 693
 694                 hdmi: hdmi@14530000 {
 695                         compatible = "samsung,exynos4212-hdmi";
 696                         reg = <0x14530000 0x70000>;
 697                         power-domains = <&pd_disp1>;
 698                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 699                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 700                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 701                                  <&clock CLK_MOUT_HDMI>;
 702                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 703                                         "sclk_hdmiphy", "mout_hdmi";
 704                         samsung,syscon-phandle = <&pmu_system_controller>;
 705                         phy = <&hdmiphy>;
 706                         status = "disabled";
 707                 };
 708
 709                 hdmicec: cec@101B0000 {
 710                         compatible = "samsung,s5p-cec";
 711                         reg = <0x101B0000 0x200>;
 712                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 713                         clocks = <&clock CLK_HDMI_CEC>;
 714                         clock-names = "hdmicec";
 715                         samsung,syscon-phandle = <&pmu_system_controller>;
 716                         hdmi-phandle = <&hdmi>;
 717                         pinctrl-names = "default";
 718                         pinctrl-0 = <&hdmi_cec>;
 719                         status = "disabled";
 720                 };
 721
 722                 mixer: mixer@14450000 {
 723                         compatible = "samsung,exynos5250-mixer";
 724                         reg = <0x14450000 0x10000>;
 725                         power-domains = <&pd_disp1>;
 726                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 727                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 728                                  <&clock CLK_SCLK_HDMI>;
 729                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 730                         iommus = <&sysmmu_tv>;
 731                         status = "disabled";
 732                 };
 733
 734                 dp_phy: video-phy {
 735                         compatible = "samsung,exynos5250-dp-video-phy";
 736                         samsung,pmu-syscon = <&pmu_system_controller>;
 737                         #phy-cells = <0>;
 738                 };
 739
 740                 adc: adc@12D10000 {
 741                         compatible = "samsung,exynos-adc-v1";
 742                         reg = <0x12D10000 0x100>;
 743                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&clock CLK_ADC>;
 745                         clock-names = "adc";
 746                         #io-channel-cells = <1>;
 747                         io-channel-ranges;
 748                         samsung,syscon-phandle = <&pmu_system_controller>;
 749                         status = "disabled";
 750                 };
 751
 752                 sysmmu_g2d: sysmmu@10A60000 {
 753                         compatible = "samsung,exynos-sysmmu";
 754                         reg = <0x10A60000 0x1000>;
 755                         interrupt-parent = <&combiner>;
 756                         interrupts = <24 5>;
 757                         clock-names = "sysmmu", "master";
 758                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 759                         #iommu-cells = <0>;
 760                 };
 761
 762                 sysmmu_mfc_r: sysmmu@11200000 {
 763                         compatible = "samsung,exynos-sysmmu";
 764                         reg = <0x11200000 0x1000>;
 765                         interrupt-parent = <&combiner>;
 766                         interrupts = <6 2>;
 767                         power-domains = <&pd_mfc>;
 768                         clock-names = "sysmmu", "master";
 769                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 770                         #iommu-cells = <0>;
 771                 };
 772
 773                 sysmmu_mfc_l: sysmmu@11210000 {
 774                         compatible = "samsung,exynos-sysmmu";
 775                         reg = <0x11210000 0x1000>;
 776                         interrupt-parent = <&combiner>;
 777                         interrupts = <8 5>;
 778                         power-domains = <&pd_mfc>;
 779                         clock-names = "sysmmu", "master";
 780                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 781                         #iommu-cells = <0>;
 782                 };
 783
 784                 sysmmu_rotator: sysmmu@11D40000 {
 785                         compatible = "samsung,exynos-sysmmu";
 786                         reg = <0x11D40000 0x1000>;
 787                         interrupt-parent = <&combiner>;
 788                         interrupts = <4 0>;
 789                         clock-names = "sysmmu", "master";
 790                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 791                         #iommu-cells = <0>;
 792                 };
 793
 794                 sysmmu_jpeg: sysmmu@11F20000 {
 795                         compatible = "samsung,exynos-sysmmu";
 796                         reg = <0x11F20000 0x1000>;
 797                         interrupt-parent = <&combiner>;
 798                         interrupts = <4 2>;
 799                         power-domains = <&pd_gsc>;
 800                         clock-names = "sysmmu", "master";
 801                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 802                         #iommu-cells = <0>;
 803                 };
 804
 805                 sysmmu_fimc_isp: sysmmu@13260000 {
 806                         compatible = "samsung,exynos-sysmmu";
 807                         reg = <0x13260000 0x1000>;
 808                         interrupt-parent = <&combiner>;
 809                         interrupts = <10 6>;
 810                         clock-names = "sysmmu";
 811                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
 812                         #iommu-cells = <0>;
 813                 };
 814
 815                 sysmmu_fimc_drc: sysmmu@13270000 {
 816                         compatible = "samsung,exynos-sysmmu";
 817                         reg = <0x13270000 0x1000>;
 818                         interrupt-parent = <&combiner>;
 819                         interrupts = <11 6>;
 820                         clock-names = "sysmmu";
 821                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
 822                         #iommu-cells = <0>;
 823                 };
 824
 825                 sysmmu_fimc_fd: sysmmu@132A0000 {
 826                         compatible = "samsung,exynos-sysmmu";
 827                         reg = <0x132A0000 0x1000>;
 828                         interrupt-parent = <&combiner>;
 829                         interrupts = <5 0>;
 830                         clock-names = "sysmmu";
 831                         clocks = <&clock CLK_SMMU_FIMC_FD>;
 832                         #iommu-cells = <0>;
 833                 };
 834
 835                 sysmmu_fimc_scc: sysmmu@13280000 {
 836                         compatible = "samsung,exynos-sysmmu";
 837                         reg = <0x13280000 0x1000>;
 838                         interrupt-parent = <&combiner>;
 839                         interrupts = <5 2>;
 840                         clock-names = "sysmmu";
 841                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
 842                         #iommu-cells = <0>;
 843                 };
 844
 845                 sysmmu_fimc_scp: sysmmu@13290000 {
 846                         compatible = "samsung,exynos-sysmmu";
 847                         reg = <0x13290000 0x1000>;
 848                         interrupt-parent = <&combiner>;
 849                         interrupts = <3 6>;
 850                         clock-names = "sysmmu";
 851                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
 852                         #iommu-cells = <0>;
 853                 };
 854
 855                 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
 856                         compatible = "samsung,exynos-sysmmu";
 857                         reg = <0x132B0000 0x1000>;
 858                         interrupt-parent = <&combiner>;
 859                         interrupts = <5 4>;
 860                         clock-names = "sysmmu";
 861                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
 862                         #iommu-cells = <0>;
 863                 };
 864
 865                 sysmmu_fimc_odc: sysmmu@132C0000 {
 866                         compatible = "samsung,exynos-sysmmu";
 867                         reg = <0x132C0000 0x1000>;
 868                         interrupt-parent = <&combiner>;
 869                         interrupts = <11 0>;
 870                         clock-names = "sysmmu";
 871                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
 872                         #iommu-cells = <0>;
 873                 };
 874
 875                 sysmmu_fimc_dis0: sysmmu@132D0000 {
 876                         compatible = "samsung,exynos-sysmmu";
 877                         reg = <0x132D0000 0x1000>;
 878                         interrupt-parent = <&combiner>;
 879                         interrupts = <10 4>;
 880                         clock-names = "sysmmu";
 881                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 882                         #iommu-cells = <0>;
 883                 };
 884
 885                 sysmmu_fimc_dis1: sysmmu@132E0000{
 886                         compatible = "samsung,exynos-sysmmu";
 887                         reg = <0x132E0000 0x1000>;
 888                         interrupt-parent = <&combiner>;
 889                         interrupts = <9 4>;
 890                         clock-names = "sysmmu";
 891                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 892                         #iommu-cells = <0>;
 893                 };
 894
 895                 sysmmu_fimc_3dnr: sysmmu@132F0000 {
 896                         compatible = "samsung,exynos-sysmmu";
 897                         reg = <0x132F0000 0x1000>;
 898                         interrupt-parent = <&combiner>;
 899                         interrupts = <5 6>;
 900                         clock-names = "sysmmu";
 901                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
 902                         #iommu-cells = <0>;
 903                 };
 904
 905                 sysmmu_fimc_lite0: sysmmu@13C40000 {
 906                         compatible = "samsung,exynos-sysmmu";
 907                         reg = <0x13C40000 0x1000>;
 908                         interrupt-parent = <&combiner>;
 909                         interrupts = <3 4>;
 910                         power-domains = <&pd_gsc>;
 911                         clock-names = "sysmmu", "master";
 912                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
 913                         #iommu-cells = <0>;
 914                 };
 915
 916                 sysmmu_fimc_lite1: sysmmu@13C50000 {
 917                         compatible = "samsung,exynos-sysmmu";
 918                         reg = <0x13C50000 0x1000>;
 919                         interrupt-parent = <&combiner>;
 920                         interrupts = <24 1>;
 921                         power-domains = <&pd_gsc>;
 922                         clock-names = "sysmmu", "master";
 923                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
 924                         #iommu-cells = <0>;
 925                 };
 926
 927                 sysmmu_gsc0: sysmmu@13E80000 {
 928                         compatible = "samsung,exynos-sysmmu";
 929                         reg = <0x13E80000 0x1000>;
 930                         interrupt-parent = <&combiner>;
 931                         interrupts = <2 0>;
 932                         power-domains = <&pd_gsc>;
 933                         clock-names = "sysmmu", "master";
 934                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 935                         #iommu-cells = <0>;
 936                 };
 937
 938                 sysmmu_gsc1: sysmmu@13E90000 {
 939                         compatible = "samsung,exynos-sysmmu";
 940                         reg = <0x13E90000 0x1000>;
 941                         interrupt-parent = <&combiner>;
 942                         interrupts = <2 2>;
 943                         power-domains = <&pd_gsc>;
 944                         clock-names = "sysmmu", "master";
 945                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 946                         #iommu-cells = <0>;
 947                 };
 948
 949                 sysmmu_gsc2: sysmmu@13EA0000 {
 950                         compatible = "samsung,exynos-sysmmu";
 951                         reg = <0x13EA0000 0x1000>;
 952                         interrupt-parent = <&combiner>;
 953                         interrupts = <2 4>;
 954                         power-domains = <&pd_gsc>;
 955                         clock-names = "sysmmu", "master";
 956                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
 957                         #iommu-cells = <0>;
 958                 };
 959
 960                 sysmmu_gsc3: sysmmu@13EB0000 {
 961                         compatible = "samsung,exynos-sysmmu";
 962                         reg = <0x13EB0000 0x1000>;
 963                         interrupt-parent = <&combiner>;
 964                         interrupts = <2 6>;
 965                         power-domains = <&pd_gsc>;
 966                         clock-names = "sysmmu", "master";
 967                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
 968                         #iommu-cells = <0>;
 969                 };
 970
 971                 sysmmu_fimd1: sysmmu@14640000 {
 972                         compatible = "samsung,exynos-sysmmu";
 973                         reg = <0x14640000 0x1000>;
 974                         interrupt-parent = <&combiner>;
 975                         interrupts = <3 2>;
 976                         power-domains = <&pd_disp1>;
 977                         clock-names = "sysmmu", "master";
 978                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 979                         #iommu-cells = <0>;
 980                 };
 981
 982                 sysmmu_tv: sysmmu@14650000 {
 983                         compatible = "samsung,exynos-sysmmu";
 984                         reg = <0x14650000 0x1000>;
 985                         interrupt-parent = <&combiner>;
 986                         interrupts = <7 4>;
 987                         power-domains = <&pd_disp1>;
 988                         clock-names = "sysmmu", "master";
 989                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 990                         #iommu-cells = <0>;
 991                 };
 992         };
 993
 994         thermal-zones {
 995                 cpu_thermal: cpu-thermal {
 996                         polling-delay-passive = <0>;
 997                         polling-delay = <0>;
 998                         thermal-sensors = <&tmu 0>;
 999
1000                         cooling-maps {
1001                                 map0 {
1002                                      /* Corresponds to 800MHz at freq_table */
1003                                      cooling-device = <&cpu0 9 9>;
1004                                 };
1005                                 map1 {
1006                                      /* Corresponds to 200MHz at freq_table */
1007                                      cooling-device = <&cpu0 15 15>;
1008                                };
1009                        };
1010                 };
1011         };
1012 };
1013
1014 &dp {
1015         power-domains = <&pd_disp1>;
1016         clocks = <&clock CLK_DP>;
1017         clock-names = "dp";
1018         phys = <&dp_phy>;
1019         phy-names = "dp";
1020 };
1021
1022 &fimd {
1023         power-domains = <&pd_disp1>;
1024         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1025         clock-names = "sclk_fimd", "fimd";
1026         iommus = <&sysmmu_fimd1>;
1027 };
1028
1029 &g2d {
1030         iommus = <&sysmmu_g2d>;
1031         clocks = <&clock CLK_G2D>;
1032         clock-names = "fimg2d";
1033         status = "okay";
1034 };
1035
1036 &i2c_0 {
1037         clocks = <&clock CLK_I2C0>;
1038         clock-names = "i2c";
1039         pinctrl-names = "default";
1040         pinctrl-0 = <&i2c0_bus>;
1041 };
1042
1043 &i2c_1 {
1044         clocks = <&clock CLK_I2C1>;
1045         clock-names = "i2c";
1046         pinctrl-names = "default";
1047         pinctrl-0 = <&i2c1_bus>;
1048 };
1049
1050 &i2c_2 {
1051         clocks = <&clock CLK_I2C2>;
1052         clock-names = "i2c";
1053         pinctrl-names = "default";
1054         pinctrl-0 = <&i2c2_bus>;
1055 };
1056
1057 &i2c_3 {
1058         clocks = <&clock CLK_I2C3>;
1059         clock-names = "i2c";
1060         pinctrl-names = "default";
1061         pinctrl-0 = <&i2c3_bus>;
1062 };
1063
1064 &pwm {
1065         clocks = <&clock CLK_PWM>;
1066         clock-names = "timers";
1067 };
1068
1069 &rtc {
1070         clocks = <&clock CLK_RTC>;
1071         clock-names = "rtc";
1072         interrupt-parent = <&pmu_system_controller>;
1073         status = "disabled";
1074 };
1075
1076 &serial_0 {
1077         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1078         clock-names = "uart", "clk_uart_baud0";
1079         dmas = <&pdma0 13>, <&pdma0 14>;
1080         dma-names = "rx", "tx";
1081 };
1082
1083 &serial_1 {
1084         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1085         clock-names = "uart", "clk_uart_baud0";
1086         dmas = <&pdma1 15>, <&pdma1 16>;
1087         dma-names = "rx", "tx";
1088 };
1089
1090 &serial_2 {
1091         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1092         clock-names = "uart", "clk_uart_baud0";
1093         dmas = <&pdma0 15>, <&pdma0 16>;
1094         dma-names = "rx", "tx";
1095 };
1096
1097 &serial_3 {
1098         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1099         clock-names = "uart", "clk_uart_baud0";
1100         dmas = <&pdma1 17>, <&pdma1 18>;
1101         dma-names = "rx", "tx";
1102 };
1103
1104 &sss {
1105         clocks = <&clock CLK_SSS>;
1106         clock-names = "secss";
1107 };
1108
1109 #include "exynos5250-pinctrl.dtsi"