arch/arm/boot/dts/exynos5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos5 SoC series common device tree source
   4  *
   5  * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
   9  * SoCs from Exynos5 series can include this file and provide values for SoCs
  10  * specfic bindings.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include "exynos-syscon-restart.dtsi"
  16
  17 / {
  18         interrupt-parent = <&gic>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         aliases {
  23                 i2c0 = &i2c_0;
  24                 i2c1 = &i2c_1;
  25                 i2c2 = &i2c_2;
  26                 i2c3 = &i2c_3;
  27                 serial0 = &serial_0;
  28                 serial1 = &serial_1;
  29                 serial2 = &serial_2;
  30                 serial3 = &serial_3;
  31         };
  32
  33         soc: soc {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges;
  38
  39                 chipid@10000000 {
  40                         compatible = "samsung,exynos4210-chipid";
  41                         reg = <0x10000000 0x100>;
  42                 };
  43
  44                 sromc: memory-controller@12250000 {
  45                         compatible = "samsung,exynos4210-srom";
  46                         reg = <0x12250000 0x14>;
  47                 };
  48
  49                 combiner: interrupt-controller@10440000 {
  50                         compatible = "samsung,exynos4210-combiner";
  51                         #interrupt-cells = <2>;
  52                         interrupt-controller;
  53                         samsung,combiner-nr = <32>;
  54                         reg = <0x10440000 0x1000>;
  55                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  56                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  57                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  58                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  59                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  60                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  61                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  62                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  63                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  64                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  65                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  66                                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  67                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  71                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  72                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  73                                      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  74                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  75                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  76                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  77                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  87                 };
  88
  89                 gic: interrupt-controller@10481000 {
  90                         compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  91                         #interrupt-cells = <3>;
  92                         interrupt-controller;
  93                         reg =   <0x10481000 0x1000>,
  94                                 <0x10482000 0x2000>,
  95                                 <0x10484000 0x2000>,
  96                                 <0x10486000 0x2000>;
  97                         interrupts = <GIC_PPI 9
  98                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  99                 };
 100
 101                 sysreg_system_controller: syscon@10050000 {
 102                         compatible = "samsung,exynos5-sysreg", "syscon";
 103                         reg = <0x10050000 0x5000>;
 104                 };
 105
 106                 serial_0: serial@12c00000 {
 107                         compatible = "samsung,exynos4210-uart";
 108                         reg = <0x12C00000 0x100>;
 109                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 110                 };
 111
 112                 serial_1: serial@12c10000 {
 113                         compatible = "samsung,exynos4210-uart";
 114                         reg = <0x12C10000 0x100>;
 115                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 116                 };
 117
 118                 serial_2: serial@12c20000 {
 119                         compatible = "samsung,exynos4210-uart";
 120                         reg = <0x12C20000 0x100>;
 121                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 122                 };
 123
 124                 serial_3: serial@12c30000 {
 125                         compatible = "samsung,exynos4210-uart";
 126                         reg = <0x12C30000 0x100>;
 127                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 128                 };
 129
 130                 i2c_0: i2c@12c60000 {
 131                         compatible = "samsung,s3c2440-i2c";
 132                         reg = <0x12C60000 0x100>;
 133                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 134                         #address-cells = <1>;
 135                         #size-cells = <0>;
 136                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 137                         status = "disabled";
 138                 };
 139
 140                 i2c_1: i2c@12c70000 {
 141                         compatible = "samsung,s3c2440-i2c";
 142                         reg = <0x12C70000 0x100>;
 143                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 147                         status = "disabled";
 148                 };
 149
 150                 i2c_2: i2c@12c80000 {
 151                         compatible = "samsung,s3c2440-i2c";
 152                         reg = <0x12C80000 0x100>;
 153                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 157                         status = "disabled";
 158                 };
 159
 160                 i2c_3: i2c@12c90000 {
 161                         compatible = "samsung,s3c2440-i2c";
 162                         reg = <0x12C90000 0x100>;
 163                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 167                         status = "disabled";
 168                 };
 169
 170                 pwm: pwm@12dd0000 {
 171                         compatible = "samsung,exynos4210-pwm";
 172                         reg = <0x12DD0000 0x100>;
 173                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 174                         #pwm-cells = <3>;
 175                 };
 176
 177                 rtc: rtc@101e0000 {
 178                         compatible = "samsung,s3c6410-rtc";
 179                         reg = <0x101E0000 0x100>;
 180                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 182                         status = "disabled";
 183                 };
 184
 185                 fimd: fimd@14400000 {
 186                         compatible = "samsung,exynos5250-fimd";
 187                         interrupt-parent = <&combiner>;
 188                         reg = <0x14400000 0x40000>;
 189                         interrupt-names = "fifo", "vsync", "lcd_sys";
 190                         interrupts = <18 4>, <18 5>, <18 6>;
 191                         samsung,sysreg = <&sysreg_system_controller>;
 192                         status = "disabled";
 193                 };
 194
 195                 dp: dp-controller@145b0000 {
 196                         compatible = "samsung,exynos5-dp";
 197                         reg = <0x145B0000 0x1000>;
 198                         interrupts = <10 3>;
 199                         interrupt-parent = <&combiner>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         status = "disabled";
 203                 };
 204
 205                 sss: sss@10830000 {
 206                         compatible = "samsung,exynos4210-secss";
 207                         reg = <0x10830000 0x300>;
 208                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 209                 };
 210
 211                 prng: rng@10830400 {
 212                       compatible = "samsung,exynos5250-prng";
 213                       reg = <0x10830400 0x200>;
 214                 };
 215
 216                 trng: rng@10830600 {
 217                       compatible = "samsung,exynos5250-trng";
 218                       reg = <0x10830600 0x100>;
 219                 };
 220
 221                 g2d: g2d@10850000 {
 222                         compatible = "samsung,exynos5250-g2d";
 223                         reg = <0x10850000 0x1000>;
 224                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 225                         status = "disabled";
 226                 };
 227         };
 228 };