2 * Device Tree Source for DRA7xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 atl_clkin0_ck: atl_clkin0_ck {
13 compatible = "ti,dra7-atl-clock";
14 clocks = <&atl_gfclk_mux>;
17 atl_clkin1_ck: atl_clkin1_ck {
19 compatible = "ti,dra7-atl-clock";
20 clocks = <&atl_gfclk_mux>;
23 atl_clkin2_ck: atl_clkin2_ck {
25 compatible = "ti,dra7-atl-clock";
26 clocks = <&atl_gfclk_mux>;
29 atl_clkin3_ck: atl_clkin3_ck {
31 compatible = "ti,dra7-atl-clock";
32 clocks = <&atl_gfclk_mux>;
35 hdmi_clkin_ck: hdmi_clkin_ck {
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
41 mlb_clkin_ck: mlb_clkin_ck {
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
47 mlbp_clkin_ck: mlbp_clkin_ck {
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
59 ref_clkin0_ck: ref_clkin0_ck {
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
65 ref_clkin1_ck: ref_clkin1_ck {
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
71 ref_clkin2_ck: ref_clkin2_ck {
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
77 ref_clkin3_ck: ref_clkin3_ck {
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
83 rmii_clk_ck: rmii_clk_ck {
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
101 sys_clk32_crystal_ck: sys_clk32_crystal_ck {
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
107 sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
109 compatible = "fixed-factor-clock";
110 clocks = <&sys_clkin1>;
115 virt_12000000_ck: virt_12000000_ck {
117 compatible = "fixed-clock";
118 clock-frequency = <12000000>;
121 virt_13000000_ck: virt_13000000_ck {
123 compatible = "fixed-clock";
124 clock-frequency = <13000000>;
127 virt_16800000_ck: virt_16800000_ck {
129 compatible = "fixed-clock";
130 clock-frequency = <16800000>;
133 virt_19200000_ck: virt_19200000_ck {
135 compatible = "fixed-clock";
136 clock-frequency = <19200000>;
139 virt_20000000_ck: virt_20000000_ck {
141 compatible = "fixed-clock";
142 clock-frequency = <20000000>;
145 virt_26000000_ck: virt_26000000_ck {
147 compatible = "fixed-clock";
148 clock-frequency = <26000000>;
151 virt_27000000_ck: virt_27000000_ck {
153 compatible = "fixed-clock";
154 clock-frequency = <27000000>;
157 virt_38400000_ck: virt_38400000_ck {
159 compatible = "fixed-clock";
160 clock-frequency = <38400000>;
163 sys_clkin2: sys_clkin2 {
165 compatible = "fixed-clock";
166 clock-frequency = <22579200>;
169 usb_otg_clkin_ck: usb_otg_clkin_ck {
171 compatible = "fixed-clock";
172 clock-frequency = <0>;
175 video1_clkin_ck: video1_clkin_ck {
177 compatible = "fixed-clock";
178 clock-frequency = <0>;
181 video1_m2_clkin_ck: video1_m2_clkin_ck {
183 compatible = "fixed-clock";
184 clock-frequency = <0>;
187 video2_clkin_ck: video2_clkin_ck {
189 compatible = "fixed-clock";
190 clock-frequency = <0>;
193 video2_m2_clkin_ck: video2_m2_clkin_ck {
195 compatible = "fixed-clock";
196 clock-frequency = <0>;
199 dpll_abe_ck: dpll_abe_ck@1e0 {
201 compatible = "ti,omap4-dpll-m4xen-clock";
202 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
203 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
206 dpll_abe_x2_ck: dpll_abe_x2_ck {
208 compatible = "ti,omap4-dpll-x2-clock";
209 clocks = <&dpll_abe_ck>;
212 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
214 compatible = "ti,divider-clock";
215 clocks = <&dpll_abe_x2_ck>;
217 ti,autoidle-shift = <8>;
219 ti,index-starts-at-one;
220 ti,invert-autoidle-bit;
223 abe_clk: abe_clk@108 {
225 compatible = "ti,divider-clock";
226 clocks = <&dpll_abe_m2x2_ck>;
229 ti,index-power-of-two;
232 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
234 compatible = "ti,divider-clock";
235 clocks = <&dpll_abe_ck>;
237 ti,autoidle-shift = <8>;
239 ti,index-starts-at-one;
240 ti,invert-autoidle-bit;
243 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
245 compatible = "ti,divider-clock";
246 clocks = <&dpll_abe_x2_ck>;
248 ti,autoidle-shift = <8>;
250 ti,index-starts-at-one;
251 ti,invert-autoidle-bit;
254 dpll_core_byp_mux: dpll_core_byp_mux@12c {
256 compatible = "ti,mux-clock";
257 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
262 dpll_core_ck: dpll_core_ck@120 {
264 compatible = "ti,omap4-dpll-core-clock";
265 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
266 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
269 dpll_core_x2_ck: dpll_core_x2_ck {
271 compatible = "ti,omap4-dpll-x2-clock";
272 clocks = <&dpll_core_ck>;
275 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
277 compatible = "ti,divider-clock";
278 clocks = <&dpll_core_x2_ck>;
280 ti,autoidle-shift = <8>;
282 ti,index-starts-at-one;
283 ti,invert-autoidle-bit;
286 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
288 compatible = "fixed-factor-clock";
289 clocks = <&dpll_core_h12x2_ck>;
294 dpll_mpu_ck: dpll_mpu_ck@160 {
296 compatible = "ti,omap5-mpu-dpll-clock";
297 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
298 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
301 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
303 compatible = "ti,divider-clock";
304 clocks = <&dpll_mpu_ck>;
306 ti,autoidle-shift = <8>;
308 ti,index-starts-at-one;
309 ti,invert-autoidle-bit;
312 mpu_dclk_div: mpu_dclk_div {
314 compatible = "fixed-factor-clock";
315 clocks = <&dpll_mpu_m2_ck>;
320 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
322 compatible = "fixed-factor-clock";
323 clocks = <&dpll_core_h12x2_ck>;
328 dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
330 compatible = "ti,mux-clock";
331 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
336 dpll_dsp_ck: dpll_dsp_ck@234 {
338 compatible = "ti,omap4-dpll-clock";
339 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
340 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
341 assigned-clocks = <&dpll_dsp_ck>;
342 assigned-clock-rates = <600000000>;
345 dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
347 compatible = "ti,divider-clock";
348 clocks = <&dpll_dsp_ck>;
350 ti,autoidle-shift = <8>;
352 ti,index-starts-at-one;
353 ti,invert-autoidle-bit;
354 assigned-clocks = <&dpll_dsp_m2_ck>;
355 assigned-clock-rates = <600000000>;
358 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
360 compatible = "fixed-factor-clock";
361 clocks = <&dpll_core_h12x2_ck>;
366 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
368 compatible = "ti,mux-clock";
369 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
374 dpll_iva_ck: dpll_iva_ck@1a0 {
376 compatible = "ti,omap4-dpll-clock";
377 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
378 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
381 dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
383 compatible = "ti,divider-clock";
384 clocks = <&dpll_iva_ck>;
386 ti,autoidle-shift = <8>;
388 ti,index-starts-at-one;
389 ti,invert-autoidle-bit;
394 compatible = "fixed-factor-clock";
395 clocks = <&dpll_iva_m2_ck>;
400 dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
402 compatible = "ti,mux-clock";
403 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
408 dpll_gpu_ck: dpll_gpu_ck@2d8 {
410 compatible = "ti,omap4-dpll-clock";
411 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
412 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
415 dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
417 compatible = "ti,divider-clock";
418 clocks = <&dpll_gpu_ck>;
420 ti,autoidle-shift = <8>;
422 ti,index-starts-at-one;
423 ti,invert-autoidle-bit;
426 dpll_core_m2_ck: dpll_core_m2_ck@130 {
428 compatible = "ti,divider-clock";
429 clocks = <&dpll_core_ck>;
431 ti,autoidle-shift = <8>;
433 ti,index-starts-at-one;
434 ti,invert-autoidle-bit;
437 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
439 compatible = "fixed-factor-clock";
440 clocks = <&dpll_core_m2_ck>;
445 dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
447 compatible = "ti,mux-clock";
448 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
453 dpll_ddr_ck: dpll_ddr_ck@210 {
455 compatible = "ti,omap4-dpll-clock";
456 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
457 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
460 dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
462 compatible = "ti,divider-clock";
463 clocks = <&dpll_ddr_ck>;
465 ti,autoidle-shift = <8>;
467 ti,index-starts-at-one;
468 ti,invert-autoidle-bit;
471 dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
473 compatible = "ti,mux-clock";
474 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
479 dpll_gmac_ck: dpll_gmac_ck@2a8 {
481 compatible = "ti,omap4-dpll-clock";
482 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
483 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
486 dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
488 compatible = "ti,divider-clock";
489 clocks = <&dpll_gmac_ck>;
491 ti,autoidle-shift = <8>;
493 ti,index-starts-at-one;
494 ti,invert-autoidle-bit;
497 video2_dclk_div: video2_dclk_div {
499 compatible = "fixed-factor-clock";
500 clocks = <&video2_m2_clkin_ck>;
505 video1_dclk_div: video1_dclk_div {
507 compatible = "fixed-factor-clock";
508 clocks = <&video1_m2_clkin_ck>;
513 hdmi_dclk_div: hdmi_dclk_div {
515 compatible = "fixed-factor-clock";
516 clocks = <&hdmi_clkin_ck>;
521 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
523 compatible = "fixed-factor-clock";
524 clocks = <&dpll_abe_m3x2_ck>;
529 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
531 compatible = "fixed-factor-clock";
532 clocks = <&dpll_abe_m3x2_ck>;
537 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
539 compatible = "fixed-factor-clock";
540 clocks = <&dpll_core_h12x2_ck>;
545 dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
547 compatible = "ti,mux-clock";
548 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
553 dpll_eve_ck: dpll_eve_ck@284 {
555 compatible = "ti,omap4-dpll-clock";
556 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
557 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
560 dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
562 compatible = "ti,divider-clock";
563 clocks = <&dpll_eve_ck>;
565 ti,autoidle-shift = <8>;
567 ti,index-starts-at-one;
568 ti,invert-autoidle-bit;
571 eve_dclk_div: eve_dclk_div {
573 compatible = "fixed-factor-clock";
574 clocks = <&dpll_eve_m2_ck>;
579 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
581 compatible = "ti,divider-clock";
582 clocks = <&dpll_core_x2_ck>;
584 ti,autoidle-shift = <8>;
586 ti,index-starts-at-one;
587 ti,invert-autoidle-bit;
590 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
592 compatible = "ti,divider-clock";
593 clocks = <&dpll_core_x2_ck>;
595 ti,autoidle-shift = <8>;
597 ti,index-starts-at-one;
598 ti,invert-autoidle-bit;
601 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
603 compatible = "ti,divider-clock";
604 clocks = <&dpll_core_x2_ck>;
606 ti,autoidle-shift = <8>;
608 ti,index-starts-at-one;
609 ti,invert-autoidle-bit;
612 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
614 compatible = "ti,divider-clock";
615 clocks = <&dpll_core_x2_ck>;
617 ti,autoidle-shift = <8>;
619 ti,index-starts-at-one;
620 ti,invert-autoidle-bit;
623 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
625 compatible = "ti,divider-clock";
626 clocks = <&dpll_core_x2_ck>;
628 ti,autoidle-shift = <8>;
630 ti,index-starts-at-one;
631 ti,invert-autoidle-bit;
634 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
636 compatible = "ti,omap4-dpll-x2-clock";
637 clocks = <&dpll_ddr_ck>;
640 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
642 compatible = "ti,divider-clock";
643 clocks = <&dpll_ddr_x2_ck>;
645 ti,autoidle-shift = <8>;
647 ti,index-starts-at-one;
648 ti,invert-autoidle-bit;
651 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
653 compatible = "ti,omap4-dpll-x2-clock";
654 clocks = <&dpll_dsp_ck>;
657 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
659 compatible = "ti,divider-clock";
660 clocks = <&dpll_dsp_x2_ck>;
662 ti,autoidle-shift = <8>;
664 ti,index-starts-at-one;
665 ti,invert-autoidle-bit;
666 assigned-clocks = <&dpll_dsp_m3x2_ck>;
667 assigned-clock-rates = <400000000>;
670 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
672 compatible = "ti,omap4-dpll-x2-clock";
673 clocks = <&dpll_gmac_ck>;
676 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
678 compatible = "ti,divider-clock";
679 clocks = <&dpll_gmac_x2_ck>;
681 ti,autoidle-shift = <8>;
683 ti,index-starts-at-one;
684 ti,invert-autoidle-bit;
687 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
689 compatible = "ti,divider-clock";
690 clocks = <&dpll_gmac_x2_ck>;
692 ti,autoidle-shift = <8>;
694 ti,index-starts-at-one;
695 ti,invert-autoidle-bit;
698 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
700 compatible = "ti,divider-clock";
701 clocks = <&dpll_gmac_x2_ck>;
703 ti,autoidle-shift = <8>;
705 ti,index-starts-at-one;
706 ti,invert-autoidle-bit;
709 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
711 compatible = "ti,divider-clock";
712 clocks = <&dpll_gmac_x2_ck>;
714 ti,autoidle-shift = <8>;
716 ti,index-starts-at-one;
717 ti,invert-autoidle-bit;
720 gmii_m_clk_div: gmii_m_clk_div {
722 compatible = "fixed-factor-clock";
723 clocks = <&dpll_gmac_h11x2_ck>;
728 hdmi_clk2_div: hdmi_clk2_div {
730 compatible = "fixed-factor-clock";
731 clocks = <&hdmi_clkin_ck>;
736 hdmi_div_clk: hdmi_div_clk {
738 compatible = "fixed-factor-clock";
739 clocks = <&hdmi_clkin_ck>;
744 l3_iclk_div: l3_iclk_div@100 {
746 compatible = "ti,divider-clock";
750 clocks = <&dpll_core_h12x2_ck>;
751 ti,index-power-of-two;
754 l4_root_clk_div: l4_root_clk_div {
756 compatible = "fixed-factor-clock";
757 clocks = <&l3_iclk_div>;
762 video1_clk2_div: video1_clk2_div {
764 compatible = "fixed-factor-clock";
765 clocks = <&video1_clkin_ck>;
770 video1_div_clk: video1_div_clk {
772 compatible = "fixed-factor-clock";
773 clocks = <&video1_clkin_ck>;
778 video2_clk2_div: video2_clk2_div {
780 compatible = "fixed-factor-clock";
781 clocks = <&video2_clkin_ck>;
786 video2_div_clk: video2_div_clk {
788 compatible = "fixed-factor-clock";
789 clocks = <&video2_clkin_ck>;
794 ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
796 compatible = "ti,mux-clock";
797 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
800 assigned-clocks = <&ipu1_gfclk_mux>;
801 assigned-clock-parents = <&dpll_core_h22x2_ck>;
804 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
806 compatible = "ti,mux-clock";
807 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
812 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
814 compatible = "ti,mux-clock";
815 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
820 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
822 compatible = "ti,mux-clock";
823 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
828 timer5_gfclk_mux: timer5_gfclk_mux@558 {
830 compatible = "ti,mux-clock";
831 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
836 timer6_gfclk_mux: timer6_gfclk_mux@560 {
838 compatible = "ti,mux-clock";
839 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
844 timer7_gfclk_mux: timer7_gfclk_mux@568 {
846 compatible = "ti,mux-clock";
847 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
852 timer8_gfclk_mux: timer8_gfclk_mux@570 {
854 compatible = "ti,mux-clock";
855 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
860 uart6_gfclk_mux: uart6_gfclk_mux@580 {
862 compatible = "ti,mux-clock";
863 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
870 compatible = "fixed-clock";
871 clock-frequency = <0>;
875 sys_clkin1: sys_clkin1@110 {
877 compatible = "ti,mux-clock";
878 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
880 ti,index-starts-at-one;
883 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
885 compatible = "ti,mux-clock";
886 clocks = <&sys_clkin1>, <&sys_clkin2>;
890 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
892 compatible = "ti,mux-clock";
893 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
897 abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
899 compatible = "ti,mux-clock";
900 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
904 abe_24m_fclk: abe_24m_fclk@11c {
906 compatible = "ti,divider-clock";
907 clocks = <&dpll_abe_m2x2_ck>;
909 ti,dividers = <8>, <16>;
912 aess_fclk: aess_fclk@178 {
914 compatible = "ti,divider-clock";
920 abe_giclk_div: abe_giclk_div@174 {
922 compatible = "ti,divider-clock";
923 clocks = <&aess_fclk>;
928 abe_lp_clk_div: abe_lp_clk_div@1d8 {
930 compatible = "ti,divider-clock";
931 clocks = <&dpll_abe_m2x2_ck>;
933 ti,dividers = <16>, <32>;
936 abe_sys_clk_div: abe_sys_clk_div@120 {
938 compatible = "ti,divider-clock";
939 clocks = <&sys_clkin1>;
944 adc_gfclk_mux: adc_gfclk_mux@1dc {
946 compatible = "ti,mux-clock";
947 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
951 sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
953 compatible = "ti,divider-clock";
954 clocks = <&sys_clkin1>;
957 ti,index-power-of-two;
960 sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
962 compatible = "ti,divider-clock";
963 clocks = <&sys_clkin2>;
966 ti,index-power-of-two;
969 per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
971 compatible = "ti,divider-clock";
972 clocks = <&dpll_abe_m2_ck>;
975 ti,index-power-of-two;
978 dsp_gclk_div: dsp_gclk_div@18c {
980 compatible = "ti,divider-clock";
981 clocks = <&dpll_dsp_m2_ck>;
984 ti,index-power-of-two;
987 gpu_dclk: gpu_dclk@1a0 {
989 compatible = "ti,divider-clock";
990 clocks = <&dpll_gpu_m2_ck>;
993 ti,index-power-of-two;
996 emif_phy_dclk_div: emif_phy_dclk_div@190 {
998 compatible = "ti,divider-clock";
999 clocks = <&dpll_ddr_m2_ck>;
1002 ti,index-power-of-two;
1005 gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
1007 compatible = "ti,divider-clock";
1008 clocks = <&dpll_gmac_m2_ck>;
1011 ti,index-power-of-two;
1014 gmac_main_clk: gmac_main_clk {
1016 compatible = "fixed-factor-clock";
1017 clocks = <&gmac_250m_dclk_div>;
1022 l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
1024 compatible = "ti,divider-clock";
1025 clocks = <&dpll_usb_m2_ck>;
1028 ti,index-power-of-two;
1031 usb_otg_dclk_div: usb_otg_dclk_div@184 {
1033 compatible = "ti,divider-clock";
1034 clocks = <&usb_otg_clkin_ck>;
1037 ti,index-power-of-two;
1040 sata_dclk_div: sata_dclk_div@1c0 {
1042 compatible = "ti,divider-clock";
1043 clocks = <&sys_clkin1>;
1046 ti,index-power-of-two;
1049 pcie2_dclk_div: pcie2_dclk_div@1b8 {
1051 compatible = "ti,divider-clock";
1052 clocks = <&dpll_pcie_ref_m2_ck>;
1055 ti,index-power-of-two;
1058 pcie_dclk_div: pcie_dclk_div@1b4 {
1060 compatible = "ti,divider-clock";
1061 clocks = <&apll_pcie_m2_ck>;
1064 ti,index-power-of-two;
1067 emu_dclk_div: emu_dclk_div@194 {
1069 compatible = "ti,divider-clock";
1070 clocks = <&sys_clkin1>;
1073 ti,index-power-of-two;
1076 secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1078 compatible = "ti,divider-clock";
1079 clocks = <&secure_32k_clk_src_ck>;
1082 ti,index-power-of-two;
1085 clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1087 compatible = "ti,mux-clock";
1088 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1092 clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1094 compatible = "ti,mux-clock";
1095 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1099 clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1101 compatible = "ti,mux-clock";
1102 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1106 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1108 compatible = "fixed-factor-clock";
1109 clocks = <&sys_clkin1>;
1114 eve_clk: eve_clk@180 {
1116 compatible = "ti,mux-clock";
1117 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1121 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1123 compatible = "ti,mux-clock";
1124 clocks = <&sys_clkin1>, <&sys_clkin2>;
1128 mlb_clk: mlb_clk@134 {
1130 compatible = "ti,divider-clock";
1131 clocks = <&mlb_clkin_ck>;
1134 ti,index-power-of-two;
1137 mlbp_clk: mlbp_clk@130 {
1139 compatible = "ti,divider-clock";
1140 clocks = <&mlbp_clkin_ck>;
1143 ti,index-power-of-two;
1146 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1148 compatible = "ti,divider-clock";
1149 clocks = <&dpll_abe_m2_ck>;
1152 ti,index-power-of-two;
1155 timer_sys_clk_div: timer_sys_clk_div@144 {
1157 compatible = "ti,divider-clock";
1158 clocks = <&sys_clkin1>;
1163 video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1165 compatible = "ti,mux-clock";
1166 clocks = <&sys_clkin1>, <&sys_clkin2>;
1170 video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1172 compatible = "ti,mux-clock";
1173 clocks = <&sys_clkin1>, <&sys_clkin2>;
1177 wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1179 compatible = "ti,mux-clock";
1180 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1184 gpio1_dbclk: gpio1_dbclk@1838 {
1186 compatible = "ti,gate-clock";
1187 clocks = <&sys_32k_ck>;
1192 dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
1194 compatible = "ti,mux-clock";
1195 clocks = <&sys_clkin1>, <&sys_clkin2>;
1196 ti,bit-shift = <24>;
1200 timer1_gfclk_mux: timer1_gfclk_mux@1840 {
1202 compatible = "ti,mux-clock";
1203 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1204 ti,bit-shift = <24>;
1208 uart10_gfclk_mux: uart10_gfclk_mux@1880 {
1210 compatible = "ti,mux-clock";
1211 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1212 ti,bit-shift = <24>;
1217 dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1219 compatible = "ti,omap4-dpll-clock";
1220 clocks = <&sys_clkin1>, <&sys_clkin1>;
1221 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1224 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1226 compatible = "ti,divider-clock";
1227 clocks = <&dpll_pcie_ref_ck>;
1229 ti,autoidle-shift = <8>;
1231 ti,index-starts-at-one;
1232 ti,invert-autoidle-bit;
1235 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1236 compatible = "ti,mux-clock";
1237 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1243 apll_pcie_ck: apll_pcie_ck@21c {
1245 compatible = "ti,dra7-apll-clock";
1246 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1247 reg = <0x021c>, <0x0220>;
1250 optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1251 compatible = "ti,gate-clock";
1252 clocks = <&sys_32k_ck>;
1258 optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1259 compatible = "ti,gate-clock";
1260 clocks = <&sys_32k_ck>;
1266 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1267 compatible = "ti,divider-clock";
1268 clocks = <&apll_pcie_ck>;
1271 ti,dividers = <2>, <1>;
1276 optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1277 compatible = "ti,gate-clock";
1278 clocks = <&apll_pcie_ck>;
1284 optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1285 compatible = "ti,gate-clock";
1286 clocks = <&apll_pcie_ck>;
1292 optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1293 compatible = "ti,gate-clock";
1294 clocks = <&optfclk_pciephy_div>;
1297 ti,bit-shift = <10>;
1300 optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1301 compatible = "ti,gate-clock";
1302 clocks = <&optfclk_pciephy_div>;
1305 ti,bit-shift = <10>;
1308 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1310 compatible = "fixed-factor-clock";
1311 clocks = <&apll_pcie_ck>;
1316 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1318 compatible = "fixed-factor-clock";
1319 clocks = <&apll_pcie_ck>;
1324 apll_pcie_m2_ck: apll_pcie_m2_ck {
1326 compatible = "fixed-factor-clock";
1327 clocks = <&apll_pcie_ck>;
1332 dpll_per_byp_mux: dpll_per_byp_mux@14c {
1334 compatible = "ti,mux-clock";
1335 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1336 ti,bit-shift = <23>;
1340 dpll_per_ck: dpll_per_ck@140 {
1342 compatible = "ti,omap4-dpll-clock";
1343 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1344 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1347 dpll_per_m2_ck: dpll_per_m2_ck@150 {
1349 compatible = "ti,divider-clock";
1350 clocks = <&dpll_per_ck>;
1352 ti,autoidle-shift = <8>;
1354 ti,index-starts-at-one;
1355 ti,invert-autoidle-bit;
1358 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1360 compatible = "fixed-factor-clock";
1361 clocks = <&dpll_per_m2_ck>;
1366 dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1368 compatible = "ti,mux-clock";
1369 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1370 ti,bit-shift = <23>;
1374 dpll_usb_ck: dpll_usb_ck@180 {
1376 compatible = "ti,omap4-dpll-j-type-clock";
1377 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1378 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1381 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1383 compatible = "ti,divider-clock";
1384 clocks = <&dpll_usb_ck>;
1386 ti,autoidle-shift = <8>;
1388 ti,index-starts-at-one;
1389 ti,invert-autoidle-bit;
1392 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1394 compatible = "ti,divider-clock";
1395 clocks = <&dpll_pcie_ref_ck>;
1397 ti,autoidle-shift = <8>;
1399 ti,index-starts-at-one;
1400 ti,invert-autoidle-bit;
1403 dpll_per_x2_ck: dpll_per_x2_ck {
1405 compatible = "ti,omap4-dpll-x2-clock";
1406 clocks = <&dpll_per_ck>;
1409 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1411 compatible = "ti,divider-clock";
1412 clocks = <&dpll_per_x2_ck>;
1414 ti,autoidle-shift = <8>;
1416 ti,index-starts-at-one;
1417 ti,invert-autoidle-bit;
1420 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1422 compatible = "ti,divider-clock";
1423 clocks = <&dpll_per_x2_ck>;
1425 ti,autoidle-shift = <8>;
1427 ti,index-starts-at-one;
1428 ti,invert-autoidle-bit;
1431 dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1433 compatible = "ti,divider-clock";
1434 clocks = <&dpll_per_x2_ck>;
1436 ti,autoidle-shift = <8>;
1438 ti,index-starts-at-one;
1439 ti,invert-autoidle-bit;
1442 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1444 compatible = "ti,divider-clock";
1445 clocks = <&dpll_per_x2_ck>;
1447 ti,autoidle-shift = <8>;
1449 ti,index-starts-at-one;
1450 ti,invert-autoidle-bit;
1453 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1455 compatible = "ti,divider-clock";
1456 clocks = <&dpll_per_x2_ck>;
1458 ti,autoidle-shift = <8>;
1460 ti,index-starts-at-one;
1461 ti,invert-autoidle-bit;
1464 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1466 compatible = "fixed-factor-clock";
1467 clocks = <&dpll_usb_ck>;
1472 func_128m_clk: func_128m_clk {
1474 compatible = "fixed-factor-clock";
1475 clocks = <&dpll_per_h11x2_ck>;
1480 func_12m_fclk: func_12m_fclk {
1482 compatible = "fixed-factor-clock";
1483 clocks = <&dpll_per_m2x2_ck>;
1488 func_24m_clk: func_24m_clk {
1490 compatible = "fixed-factor-clock";
1491 clocks = <&dpll_per_m2_ck>;
1496 func_48m_fclk: func_48m_fclk {
1498 compatible = "fixed-factor-clock";
1499 clocks = <&dpll_per_m2x2_ck>;
1504 func_96m_fclk: func_96m_fclk {
1506 compatible = "fixed-factor-clock";
1507 clocks = <&dpll_per_m2x2_ck>;
1512 l3init_60m_fclk: l3init_60m_fclk@104 {
1514 compatible = "ti,divider-clock";
1515 clocks = <&dpll_usb_m2_ck>;
1517 ti,dividers = <1>, <8>;
1520 clkout2_clk: clkout2_clk@6b0 {
1522 compatible = "ti,gate-clock";
1523 clocks = <&clkoutmux2_clk_mux>;
1528 l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1530 compatible = "ti,gate-clock";
1531 clocks = <&dpll_usb_clkdcoldo>;
1536 dss_32khz_clk: dss_32khz_clk@1120 {
1538 compatible = "ti,gate-clock";
1539 clocks = <&sys_32k_ck>;
1540 ti,bit-shift = <11>;
1544 dss_48mhz_clk: dss_48mhz_clk@1120 {
1546 compatible = "ti,gate-clock";
1547 clocks = <&func_48m_fclk>;
1552 dss_dss_clk: dss_dss_clk@1120 {
1554 compatible = "ti,gate-clock";
1555 clocks = <&dpll_per_h12x2_ck>;
1561 dss_hdmi_clk: dss_hdmi_clk@1120 {
1563 compatible = "ti,gate-clock";
1564 clocks = <&hdmi_dpll_clk_mux>;
1565 ti,bit-shift = <10>;
1569 dss_video1_clk: dss_video1_clk@1120 {
1571 compatible = "ti,gate-clock";
1572 clocks = <&video1_dpll_clk_mux>;
1573 ti,bit-shift = <12>;
1577 dss_video2_clk: dss_video2_clk@1120 {
1579 compatible = "ti,gate-clock";
1580 clocks = <&video2_dpll_clk_mux>;
1581 ti,bit-shift = <13>;
1585 gpio2_dbclk: gpio2_dbclk@1760 {
1587 compatible = "ti,gate-clock";
1588 clocks = <&sys_32k_ck>;
1593 gpio3_dbclk: gpio3_dbclk@1768 {
1595 compatible = "ti,gate-clock";
1596 clocks = <&sys_32k_ck>;
1601 gpio4_dbclk: gpio4_dbclk@1770 {
1603 compatible = "ti,gate-clock";
1604 clocks = <&sys_32k_ck>;
1609 gpio5_dbclk: gpio5_dbclk@1778 {
1611 compatible = "ti,gate-clock";
1612 clocks = <&sys_32k_ck>;
1617 gpio6_dbclk: gpio6_dbclk@1780 {
1619 compatible = "ti,gate-clock";
1620 clocks = <&sys_32k_ck>;
1625 gpio7_dbclk: gpio7_dbclk@1810 {
1627 compatible = "ti,gate-clock";
1628 clocks = <&sys_32k_ck>;
1633 gpio8_dbclk: gpio8_dbclk@1818 {
1635 compatible = "ti,gate-clock";
1636 clocks = <&sys_32k_ck>;
1641 mmc1_clk32k: mmc1_clk32k@1328 {
1643 compatible = "ti,gate-clock";
1644 clocks = <&sys_32k_ck>;
1649 mmc2_clk32k: mmc2_clk32k@1330 {
1651 compatible = "ti,gate-clock";
1652 clocks = <&sys_32k_ck>;
1657 mmc3_clk32k: mmc3_clk32k@1820 {
1659 compatible = "ti,gate-clock";
1660 clocks = <&sys_32k_ck>;
1665 mmc4_clk32k: mmc4_clk32k@1828 {
1667 compatible = "ti,gate-clock";
1668 clocks = <&sys_32k_ck>;
1673 sata_ref_clk: sata_ref_clk@1388 {
1675 compatible = "ti,gate-clock";
1676 clocks = <&sys_clkin1>;
1681 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
1683 compatible = "ti,gate-clock";
1684 clocks = <&l3init_960m_gfclk>;
1689 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
1691 compatible = "ti,gate-clock";
1692 clocks = <&l3init_960m_gfclk>;
1697 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1699 compatible = "ti,gate-clock";
1700 clocks = <&sys_32k_ck>;
1705 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1707 compatible = "ti,gate-clock";
1708 clocks = <&sys_32k_ck>;
1713 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1715 compatible = "ti,gate-clock";
1716 clocks = <&sys_32k_ck>;
1721 atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
1723 compatible = "ti,mux-clock";
1724 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1725 ti,bit-shift = <24>;
1729 atl_gfclk_mux: atl_gfclk_mux@c00 {
1731 compatible = "ti,mux-clock";
1732 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1733 ti,bit-shift = <26>;
1737 rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
1739 compatible = "ti,mux-clock";
1740 clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
1741 ti,bit-shift = <24>;
1745 gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
1747 compatible = "ti,mux-clock";
1748 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1749 ti,bit-shift = <25>;
1753 gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1755 compatible = "ti,mux-clock";
1756 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1757 ti,bit-shift = <24>;
1761 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1763 compatible = "ti,mux-clock";
1764 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1765 ti,bit-shift = <26>;
1769 l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1771 compatible = "ti,divider-clock";
1772 clocks = <&wkupaon_iclk_mux>;
1773 ti,bit-shift = <24>;
1775 ti,dividers = <8>, <16>, <32>;
1778 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
1780 compatible = "ti,mux-clock";
1781 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1782 ti,bit-shift = <28>;
1786 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
1788 compatible = "ti,mux-clock";
1789 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1790 ti,bit-shift = <24>;
1794 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
1796 compatible = "ti,mux-clock";
1797 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1798 ti,bit-shift = <22>;
1802 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
1804 compatible = "ti,mux-clock";
1805 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1806 ti,bit-shift = <24>;
1810 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
1812 compatible = "ti,mux-clock";
1813 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1814 ti,bit-shift = <22>;
1818 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
1820 compatible = "ti,mux-clock";
1821 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1822 ti,bit-shift = <24>;
1826 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
1828 compatible = "ti,mux-clock";
1829 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1830 ti,bit-shift = <22>;
1834 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
1836 compatible = "ti,mux-clock";
1837 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1838 ti,bit-shift = <24>;
1842 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
1844 compatible = "ti,mux-clock";
1845 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1846 ti,bit-shift = <22>;
1850 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
1852 compatible = "ti,mux-clock";
1853 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1854 ti,bit-shift = <24>;
1858 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
1860 compatible = "ti,mux-clock";
1861 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1862 ti,bit-shift = <22>;
1866 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
1868 compatible = "ti,mux-clock";
1869 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1870 ti,bit-shift = <24>;
1874 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
1876 compatible = "ti,mux-clock";
1877 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1878 ti,bit-shift = <22>;
1882 mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
1884 compatible = "ti,mux-clock";
1885 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1886 ti,bit-shift = <22>;
1890 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
1892 compatible = "ti,mux-clock";
1893 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1894 ti,bit-shift = <24>;
1898 mmc1_fclk_mux: mmc1_fclk_mux@1328 {
1900 compatible = "ti,mux-clock";
1901 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1902 ti,bit-shift = <24>;
1906 mmc1_fclk_div: mmc1_fclk_div@1328 {
1908 compatible = "ti,divider-clock";
1909 clocks = <&mmc1_fclk_mux>;
1910 ti,bit-shift = <25>;
1913 ti,index-power-of-two;
1916 mmc2_fclk_mux: mmc2_fclk_mux@1330 {
1918 compatible = "ti,mux-clock";
1919 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1920 ti,bit-shift = <24>;
1924 mmc2_fclk_div: mmc2_fclk_div@1330 {
1926 compatible = "ti,divider-clock";
1927 clocks = <&mmc2_fclk_mux>;
1928 ti,bit-shift = <25>;
1931 ti,index-power-of-two;
1934 mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
1936 compatible = "ti,mux-clock";
1937 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1938 ti,bit-shift = <24>;
1942 mmc3_gfclk_div: mmc3_gfclk_div@1820 {
1944 compatible = "ti,divider-clock";
1945 clocks = <&mmc3_gfclk_mux>;
1946 ti,bit-shift = <25>;
1949 ti,index-power-of-two;
1952 mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
1954 compatible = "ti,mux-clock";
1955 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1956 ti,bit-shift = <24>;
1960 mmc4_gfclk_div: mmc4_gfclk_div@1828 {
1962 compatible = "ti,divider-clock";
1963 clocks = <&mmc4_gfclk_mux>;
1964 ti,bit-shift = <25>;
1967 ti,index-power-of-two;
1970 qspi_gfclk_mux: qspi_gfclk_mux@1838 {
1972 compatible = "ti,mux-clock";
1973 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1974 ti,bit-shift = <24>;
1978 qspi_gfclk_div: qspi_gfclk_div@1838 {
1980 compatible = "ti,divider-clock";
1981 clocks = <&qspi_gfclk_mux>;
1982 ti,bit-shift = <25>;
1985 ti,index-power-of-two;
1988 timer10_gfclk_mux: timer10_gfclk_mux@1728 {
1990 compatible = "ti,mux-clock";
1991 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1992 ti,bit-shift = <24>;
1996 timer11_gfclk_mux: timer11_gfclk_mux@1730 {
1998 compatible = "ti,mux-clock";
1999 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2000 ti,bit-shift = <24>;
2004 timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
2006 compatible = "ti,mux-clock";
2007 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2008 ti,bit-shift = <24>;
2012 timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
2014 compatible = "ti,mux-clock";
2015 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2016 ti,bit-shift = <24>;
2020 timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
2022 compatible = "ti,mux-clock";
2023 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2024 ti,bit-shift = <24>;
2028 timer16_gfclk_mux: timer16_gfclk_mux@1830 {
2030 compatible = "ti,mux-clock";
2031 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2032 ti,bit-shift = <24>;
2036 timer2_gfclk_mux: timer2_gfclk_mux@1738 {
2038 compatible = "ti,mux-clock";
2039 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2040 ti,bit-shift = <24>;
2044 timer3_gfclk_mux: timer3_gfclk_mux@1740 {
2046 compatible = "ti,mux-clock";
2047 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2048 ti,bit-shift = <24>;
2052 timer4_gfclk_mux: timer4_gfclk_mux@1748 {
2054 compatible = "ti,mux-clock";
2055 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2056 ti,bit-shift = <24>;
2060 timer9_gfclk_mux: timer9_gfclk_mux@1750 {
2062 compatible = "ti,mux-clock";
2063 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2064 ti,bit-shift = <24>;
2068 uart1_gfclk_mux: uart1_gfclk_mux@1840 {
2070 compatible = "ti,mux-clock";
2071 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2072 ti,bit-shift = <24>;
2076 uart2_gfclk_mux: uart2_gfclk_mux@1848 {
2078 compatible = "ti,mux-clock";
2079 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2080 ti,bit-shift = <24>;
2084 uart3_gfclk_mux: uart3_gfclk_mux@1850 {
2086 compatible = "ti,mux-clock";
2087 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2088 ti,bit-shift = <24>;
2092 uart4_gfclk_mux: uart4_gfclk_mux@1858 {
2094 compatible = "ti,mux-clock";
2095 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2096 ti,bit-shift = <24>;
2100 uart5_gfclk_mux: uart5_gfclk_mux@1870 {
2102 compatible = "ti,mux-clock";
2103 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2104 ti,bit-shift = <24>;
2108 uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
2110 compatible = "ti,mux-clock";
2111 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2112 ti,bit-shift = <24>;
2116 uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
2118 compatible = "ti,mux-clock";
2119 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2120 ti,bit-shift = <24>;
2124 uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
2126 compatible = "ti,mux-clock";
2127 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2128 ti,bit-shift = <24>;
2132 vip1_gclk_mux: vip1_gclk_mux@1020 {
2134 compatible = "ti,mux-clock";
2135 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2136 ti,bit-shift = <24>;
2140 vip2_gclk_mux: vip2_gclk_mux@1028 {
2142 compatible = "ti,mux-clock";
2143 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2144 ti,bit-shift = <24>;
2148 vip3_gclk_mux: vip3_gclk_mux@1030 {
2150 compatible = "ti,mux-clock";
2151 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2152 ti,bit-shift = <24>;
2157 &cm_core_clockdomains {
2158 coreaon_clkdm: coreaon_clkdm {
2159 compatible = "ti,clockdomain";
2160 clocks = <&dpll_usb_ck>;
2165 dss_deshdcp_clk: dss_deshdcp_clk@558 {
2167 compatible = "ti,gate-clock";
2168 clocks = <&l3_iclk_div>;
2173 ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
2175 compatible = "ti,gate-clock";
2176 clocks = <&l4_root_clk_div>;
2177 ti,bit-shift = <20>;
2181 ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
2183 compatible = "ti,gate-clock";
2184 clocks = <&l4_root_clk_div>;
2185 ti,bit-shift = <21>;
2189 ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
2191 compatible = "ti,gate-clock";
2192 clocks = <&l4_root_clk_div>;
2193 ti,bit-shift = <22>;
2197 sys_32k_ck: sys_32k_ck {
2199 compatible = "ti,mux-clock";
2200 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;