2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
53 compatible = "arm,cortex-a15";
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
66 gic: interrupt-controller@48211000 {
67 compatible = "arm,cortex-a15-gic";
69 #interrupt-cells = <3>;
70 reg = <0x48211000 0x1000>,
74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
78 * The soc node represents the soc top level view. It is uses for IPs
79 * that are not memory mapped in the MPU view or for the MPU itself.
82 compatible = "ti,omap-infra";
84 compatible = "ti,omap5-mpu";
90 * XXX: Use a flat representation of the SOC interconnect.
91 * The real OMAP interconnect network is quite complex.
92 * Since that will not bring real advantage to represent that in DT for
93 * the moment, just use a fake OCP bus entry to represent the whole bus
97 compatible = "ti,omap4-l3-noc", "simple-bus";
101 ti,hwmods = "l3_main_1", "l3_main_2";
102 reg = <0x44000000 0x2000>,
104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
108 compatible = "ti,dra7-prm";
109 reg = <0x4ae06000 0x3000>;
112 #address-cells = <1>;
116 prm_clockdomains: clockdomains {
120 cm_core_aon: cm_core_aon@4a005000 {
121 compatible = "ti,dra7-cm-core-aon";
122 reg = <0x4a005000 0x2000>;
124 cm_core_aon_clocks: clocks {
125 #address-cells = <1>;
129 cm_core_aon_clockdomains: clockdomains {
133 cm_core: cm_core@4a008000 {
134 compatible = "ti,dra7-cm-core";
135 reg = <0x4a008000 0x3000>;
137 cm_core_clocks: clocks {
138 #address-cells = <1>;
142 cm_core_clockdomains: clockdomains {
146 counter32k: counter@4ae04000 {
147 compatible = "ti,omap-counter32k";
148 reg = <0x4ae04000 0x40>;
149 ti,hwmods = "counter_32k";
152 dra7_pmx_core: pinmux@4a003400 {
153 compatible = "pinctrl-single";
154 reg = <0x4a003400 0x0464>;
155 #address-cells = <1>;
157 pinctrl-single,register-width = <32>;
158 pinctrl-single,function-mask = <0x3fffffff>;
161 sdma: dma-controller@4a056000 {
162 compatible = "ti,omap4430-sdma";
163 reg = <0x4a056000 0x1000>;
164 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
169 #dma-channels = <32>;
170 #dma-requests = <127>;
173 gpio1: gpio@4ae10000 {
174 compatible = "ti,omap4-gpio";
175 reg = <0x4ae10000 0x200>;
176 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-controller;
181 #interrupt-cells = <1>;
184 gpio2: gpio@48055000 {
185 compatible = "ti,omap4-gpio";
186 reg = <0x48055000 0x200>;
187 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-controller;
192 #interrupt-cells = <1>;
195 gpio3: gpio@48057000 {
196 compatible = "ti,omap4-gpio";
197 reg = <0x48057000 0x200>;
198 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-controller;
203 #interrupt-cells = <1>;
206 gpio4: gpio@48059000 {
207 compatible = "ti,omap4-gpio";
208 reg = <0x48059000 0x200>;
209 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-controller;
214 #interrupt-cells = <1>;
217 gpio5: gpio@4805b000 {
218 compatible = "ti,omap4-gpio";
219 reg = <0x4805b000 0x200>;
220 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-controller;
225 #interrupt-cells = <1>;
228 gpio6: gpio@4805d000 {
229 compatible = "ti,omap4-gpio";
230 reg = <0x4805d000 0x200>;
231 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-controller;
236 #interrupt-cells = <1>;
239 gpio7: gpio@48051000 {
240 compatible = "ti,omap4-gpio";
241 reg = <0x48051000 0x200>;
242 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
246 interrupt-controller;
247 #interrupt-cells = <1>;
250 gpio8: gpio@48053000 {
251 compatible = "ti,omap4-gpio";
252 reg = <0x48053000 0x200>;
253 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
257 interrupt-controller;
258 #interrupt-cells = <1>;
261 uart1: serial@4806a000 {
262 compatible = "ti,omap4-uart";
263 reg = <0x4806a000 0x100>;
264 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
266 clock-frequency = <48000000>;
270 uart2: serial@4806c000 {
271 compatible = "ti,omap4-uart";
272 reg = <0x4806c000 0x100>;
273 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
275 clock-frequency = <48000000>;
279 uart3: serial@48020000 {
280 compatible = "ti,omap4-uart";
281 reg = <0x48020000 0x100>;
282 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
284 clock-frequency = <48000000>;
288 uart4: serial@4806e000 {
289 compatible = "ti,omap4-uart";
290 reg = <0x4806e000 0x100>;
291 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
293 clock-frequency = <48000000>;
297 uart5: serial@48066000 {
298 compatible = "ti,omap4-uart";
299 reg = <0x48066000 0x100>;
300 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
302 clock-frequency = <48000000>;
306 uart6: serial@48068000 {
307 compatible = "ti,omap4-uart";
308 reg = <0x48068000 0x100>;
309 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
311 clock-frequency = <48000000>;
315 uart7: serial@48420000 {
316 compatible = "ti,omap4-uart";
317 reg = <0x48420000 0x100>;
319 clock-frequency = <48000000>;
323 uart8: serial@48422000 {
324 compatible = "ti,omap4-uart";
325 reg = <0x48422000 0x100>;
327 clock-frequency = <48000000>;
331 uart9: serial@48424000 {
332 compatible = "ti,omap4-uart";
333 reg = <0x48424000 0x100>;
335 clock-frequency = <48000000>;
339 uart10: serial@4ae2b000 {
340 compatible = "ti,omap4-uart";
341 reg = <0x4ae2b000 0x100>;
342 ti,hwmods = "uart10";
343 clock-frequency = <48000000>;
347 timer1: timer@4ae18000 {
348 compatible = "ti,omap5430-timer";
349 reg = <0x4ae18000 0x80>;
350 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
351 ti,hwmods = "timer1";
355 timer2: timer@48032000 {
356 compatible = "ti,omap5430-timer";
357 reg = <0x48032000 0x80>;
358 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "timer2";
362 timer3: timer@48034000 {
363 compatible = "ti,omap5430-timer";
364 reg = <0x48034000 0x80>;
365 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
366 ti,hwmods = "timer3";
369 timer4: timer@48036000 {
370 compatible = "ti,omap5430-timer";
371 reg = <0x48036000 0x80>;
372 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
373 ti,hwmods = "timer4";
376 timer5: timer@48820000 {
377 compatible = "ti,omap5430-timer";
378 reg = <0x48820000 0x80>;
379 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
380 ti,hwmods = "timer5";
384 timer6: timer@48822000 {
385 compatible = "ti,omap5430-timer";
386 reg = <0x48822000 0x80>;
387 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
388 ti,hwmods = "timer6";
393 timer7: timer@48824000 {
394 compatible = "ti,omap5430-timer";
395 reg = <0x48824000 0x80>;
396 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
397 ti,hwmods = "timer7";
401 timer8: timer@48826000 {
402 compatible = "ti,omap5430-timer";
403 reg = <0x48826000 0x80>;
404 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
405 ti,hwmods = "timer8";
410 timer9: timer@4803e000 {
411 compatible = "ti,omap5430-timer";
412 reg = <0x4803e000 0x80>;
413 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "timer9";
417 timer10: timer@48086000 {
418 compatible = "ti,omap5430-timer";
419 reg = <0x48086000 0x80>;
420 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
421 ti,hwmods = "timer10";
424 timer11: timer@48088000 {
425 compatible = "ti,omap5430-timer";
426 reg = <0x48088000 0x80>;
427 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
428 ti,hwmods = "timer11";
432 timer13: timer@48828000 {
433 compatible = "ti,omap5430-timer";
434 reg = <0x48828000 0x80>;
435 ti,hwmods = "timer13";
439 timer14: timer@4882a000 {
440 compatible = "ti,omap5430-timer";
441 reg = <0x4882a000 0x80>;
442 ti,hwmods = "timer14";
446 timer15: timer@4882c000 {
447 compatible = "ti,omap5430-timer";
448 reg = <0x4882c000 0x80>;
449 ti,hwmods = "timer15";
453 timer16: timer@4882e000 {
454 compatible = "ti,omap5430-timer";
455 reg = <0x4882e000 0x80>;
456 ti,hwmods = "timer16";
461 compatible = "ti,omap4-wdt";
462 reg = <0x4ae14000 0x80>;
463 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
464 ti,hwmods = "wd_timer2";
468 compatible = "ti,omap4-i2c";
469 reg = <0x48070000 0x100>;
470 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
471 #address-cells = <1>;
478 compatible = "ti,omap4-i2c";
479 reg = <0x48072000 0x100>;
480 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
481 #address-cells = <1>;
488 compatible = "ti,omap4-i2c";
489 reg = <0x48060000 0x100>;
490 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
498 compatible = "ti,omap4-i2c";
499 reg = <0x4807a000 0x100>;
500 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
501 #address-cells = <1>;
508 compatible = "ti,omap4-i2c";
509 reg = <0x4807c000 0x100>;
510 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
511 #address-cells = <1>;
518 compatible = "ti,omap4-hsmmc";
519 reg = <0x4809c000 0x400>;
520 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
523 ti,needs-special-reset;
524 dmas = <&sdma 61>, <&sdma 62>;
525 dma-names = "tx", "rx";
530 compatible = "ti,omap4-hsmmc";
531 reg = <0x480b4000 0x400>;
532 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
534 ti,needs-special-reset;
535 dmas = <&sdma 47>, <&sdma 48>;
536 dma-names = "tx", "rx";
541 compatible = "ti,omap4-hsmmc";
542 reg = <0x480ad000 0x400>;
543 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
545 ti,needs-special-reset;
546 dmas = <&sdma 77>, <&sdma 78>;
547 dma-names = "tx", "rx";
552 compatible = "ti,omap4-hsmmc";
553 reg = <0x480d1000 0x400>;
554 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
556 ti,needs-special-reset;
557 dmas = <&sdma 57>, <&sdma 58>;
558 dma-names = "tx", "rx";
562 mcspi1: spi@48098000 {
563 compatible = "ti,omap4-mcspi";
564 reg = <0x48098000 0x200>;
565 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
568 ti,hwmods = "mcspi1";
578 dma-names = "tx0", "rx0", "tx1", "rx1",
579 "tx2", "rx2", "tx3", "rx3";
583 mcspi2: spi@4809a000 {
584 compatible = "ti,omap4-mcspi";
585 reg = <0x4809a000 0x200>;
586 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
587 #address-cells = <1>;
589 ti,hwmods = "mcspi2";
595 dma-names = "tx0", "rx0", "tx1", "rx1";
599 mcspi3: spi@480b8000 {
600 compatible = "ti,omap4-mcspi";
601 reg = <0x480b8000 0x200>;
602 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
603 #address-cells = <1>;
605 ti,hwmods = "mcspi3";
607 dmas = <&sdma 15>, <&sdma 16>;
608 dma-names = "tx0", "rx0";
612 mcspi4: spi@480ba000 {
613 compatible = "ti,omap4-mcspi";
614 reg = <0x480ba000 0x200>;
615 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
616 #address-cells = <1>;
618 ti,hwmods = "mcspi4";
620 dmas = <&sdma 70>, <&sdma 71>;
621 dma-names = "tx0", "rx0";
627 /include/ "dra7xx-clocks.dtsi"