arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 i2c3 = &i2c4;
  30                 i2c4 = &i2c5;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 serial8 = &uart9;
  40                 serial9 = &uart10;
  41                 ethernet0 = &cpsw_emac0;
  42                 ethernet1 = &cpsw_emac1;
  43                 d_can0 = &dcan1;
  44                 d_can1 = &dcan2;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv7-timer";
  49                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 arm,routable-irqs = <192>;
  60                 reg = <0x48211000 0x1000>,
  61                       <0x48212000 0x1000>,
  62                       <0x48214000 0x2000>,
  63                       <0x48216000 0x2000>;
  64                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  65         };
  66
  67         /*
  68          * The soc node represents the soc top level view. It is used for IPs
  69          * that are not memory mapped in the MPU view or for the MPU itself.
  70          */
  71         soc {
  72                 compatible = "ti,omap-infra";
  73                 mpu {
  74                         compatible = "ti,omap5-mpu";
  75                         ti,hwmods = "mpu";
  76                 };
  77         };
  78
  79         /*
  80          * XXX: Use a flat representation of the SOC interconnect.
  81          * The real OMAP interconnect network is quite complex.
  82          * Since it will not bring real advantage to represent that in DT for
  83          * the moment, just use a fake OCP bus entry to represent the whole bus
  84          * hierarchy.
  85          */
  86         ocp {
  87                 compatible = "ti,dra7-l3-noc", "simple-bus";
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 ranges;
  91                 ti,hwmods = "l3_main_1", "l3_main_2";
  92                 reg = <0x44000000 0x1000000>,
  93                       <0x45000000 0x1000>;
  94                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  95                              <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
  96
  97                 l4_cfg: l4@4a000000 {
  98                         compatible = "ti,dra7-l4-cfg", "simple-bus";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges = <0 0x4a000000 0x22c000>;
 102
 103                         scm: scm@2000 {
 104                                 compatible = "ti,dra7-scm-core", "simple-bus";
 105                                 reg = <0x2000 0x2000>;
 106                                 #address-cells = <1>;
 107                                 #size-cells = <1>;
 108                                 ranges = <0 0x2000 0x2000>;
 109
 110                                 scm_conf: scm_conf@0 {
 111                                         compatible = "syscon";
 112                                         reg = <0x0 0x1400>;
 113                                         #address-cells = <1>;
 114                                         #size-cells = <1>;
 115
 116                                         pbias_regulator: pbias_regulator {
 117                                                 compatible = "ti,pbias-omap";
 118                                                 reg = <0xe00 0x4>;
 119                                                 syscon = <&scm_conf>;
 120                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 121                                                         regulator-name = "pbias_mmc_omap5";
 122                                                         regulator-min-microvolt = <1800000>;
 123                                                         regulator-max-microvolt = <3000000>;
 124                                                 };
 125                                         };
 126                                 };
 127
 128                                 dra7_pmx_core: pinmux@1400 {
 129                                         compatible = "ti,dra7-padconf",
 130                                                      "pinctrl-single";
 131                                         reg = <0x1400 0x0464>;
 132                                         #address-cells = <1>;
 133                                         #size-cells = <0>;
 134                                         #interrupt-cells = <1>;
 135                                         interrupt-controller;
 136                                         pinctrl-single,register-width = <32>;
 137                                         pinctrl-single,function-mask = <0x3fffffff>;
 138                                 };
 139                         };
 140
 141                         cm_core_aon: cm_core_aon@5000 {
 142                                 compatible = "ti,dra7-cm-core-aon";
 143                                 reg = <0x5000 0x2000>;
 144
 145                                 cm_core_aon_clocks: clocks {
 146                                         #address-cells = <1>;
 147                                         #size-cells = <0>;
 148                                 };
 149
 150                                 cm_core_aon_clockdomains: clockdomains {
 151                                 };
 152                         };
 153
 154                         cm_core: cm_core@8000 {
 155                                 compatible = "ti,dra7-cm-core";
 156                                 reg = <0x8000 0x3000>;
 157
 158                                 cm_core_clocks: clocks {
 159                                         #address-cells = <1>;
 160                                         #size-cells = <0>;
 161                                 };
 162
 163                                 cm_core_clockdomains: clockdomains {
 164                                 };
 165                         };
 166                 };
 167
 168                 l4_wkup: l4@4ae00000 {
 169                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172                         ranges = <0 0x4ae00000 0x3f000>;
 173
 174                         counter32k: counter@4000 {
 175                                 compatible = "ti,omap-counter32k";
 176                                 reg = <0x4000 0x40>;
 177                                 ti,hwmods = "counter_32k";
 178                         };
 179
 180                         prm: prm@6000 {
 181                                 compatible = "ti,dra7-prm";
 182                                 reg = <0x6000 0x3000>;
 183                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                                 prm_clocks: clocks {
 186                                         #address-cells = <1>;
 187                                         #size-cells = <0>;
 188                                 };
 189
 190                                 prm_clockdomains: clockdomains {
 191                                 };
 192                         };
 193                 };
 194
 195                 axi@0 {
 196                         compatible = "simple-bus";
 197                         #size-cells = <1>;
 198                         #address-cells = <1>;
 199                         ranges = <0x51000000 0x51000000 0x3000
 200                                   0x0        0x20000000 0x10000000>;
 201                         pcie@51000000 {
 202                                 compatible = "ti,dra7-pcie";
 203                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 204                                 reg-names = "rc_dbics", "ti_conf", "config";
 205                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 206                                 #address-cells = <3>;
 207                                 #size-cells = <2>;
 208                                 device_type = "pci";
 209                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 210                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 211                                 #interrupt-cells = <1>;
 212                                 num-lanes = <1>;
 213                                 ti,hwmods = "pcie1";
 214                                 phys = <&pcie1_phy>;
 215                                 phy-names = "pcie-phy0";
 216                                 interrupt-map-mask = <0 0 0 7>;
 217                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 218                                                 <0 0 0 2 &pcie1_intc 2>,
 219                                                 <0 0 0 3 &pcie1_intc 3>,
 220                                                 <0 0 0 4 &pcie1_intc 4>;
 221                                 pcie1_intc: interrupt-controller {
 222                                         interrupt-controller;
 223                                         #address-cells = <0>;
 224                                         #interrupt-cells = <1>;
 225                                 };
 226                         };
 227                 };
 228
 229                 axi@1 {
 230                         compatible = "simple-bus";
 231                         #size-cells = <1>;
 232                         #address-cells = <1>;
 233                         ranges = <0x51800000 0x51800000 0x3000
 234                                   0x0        0x30000000 0x10000000>;
 235                         status = "disabled";
 236                         pcie@51000000 {
 237                                 compatible = "ti,dra7-pcie";
 238                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 239                                 reg-names = "rc_dbics", "ti_conf", "config";
 240                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 241                                 #address-cells = <3>;
 242                                 #size-cells = <2>;
 243                                 device_type = "pci";
 244                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 245                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 246                                 #interrupt-cells = <1>;
 247                                 num-lanes = <1>;
 248                                 ti,hwmods = "pcie2";
 249                                 phys = <&pcie2_phy>;
 250                                 phy-names = "pcie-phy0";
 251                                 interrupt-map-mask = <0 0 0 7>;
 252                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 253                                                 <0 0 0 2 &pcie2_intc 2>,
 254                                                 <0 0 0 3 &pcie2_intc 3>,
 255                                                 <0 0 0 4 &pcie2_intc 4>;
 256                                 pcie2_intc: interrupt-controller {
 257                                         interrupt-controller;
 258                                         #address-cells = <0>;
 259                                         #interrupt-cells = <1>;
 260                                 };
 261                         };
 262                 };
 263
 264                 bandgap: bandgap@4a0021e0 {
 265                         reg = <0x4a0021e0 0xc
 266                                 0x4a00232c 0xc
 267                                 0x4a002380 0x2c
 268                                 0x4a0023C0 0x3c
 269                                 0x4a002564 0x8
 270                                 0x4a002574 0x50>;
 271                                 compatible = "ti,dra752-bandgap";
 272                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 273                                 #thermal-sensor-cells = <1>;
 274                 };
 275
 276                 dra7_ctrl_core: ctrl_core@4a002000 {
 277                         compatible = "syscon";
 278                         reg = <0x4a002000 0x6d0>;
 279                 };
 280
 281                 dra7_ctrl_general: tisyscon@4a002e00 {
 282                         compatible = "syscon";
 283                         reg = <0x4a002e00 0x7c>;
 284                 };
 285
 286                 sdma: dma-controller@4a056000 {
 287                         compatible = "ti,omap4430-sdma";
 288                         reg = <0x4a056000 0x1000>;
 289                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 293                         #dma-cells = <1>;
 294                         dma-channels = <32>;
 295                         dma-requests = <127>;
 296                 };
 297
 298                 gpio1: gpio@4ae10000 {
 299                         compatible = "ti,omap4-gpio";
 300                         reg = <0x4ae10000 0x200>;
 301                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 302                         ti,hwmods = "gpio1";
 303                         gpio-controller;
 304                         #gpio-cells = <2>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                 };
 308
 309                 gpio2: gpio@48055000 {
 310                         compatible = "ti,omap4-gpio";
 311                         reg = <0x48055000 0x200>;
 312                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 313                         ti,hwmods = "gpio2";
 314                         gpio-controller;
 315                         #gpio-cells = <2>;
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                 };
 319
 320                 gpio3: gpio@48057000 {
 321                         compatible = "ti,omap4-gpio";
 322                         reg = <0x48057000 0x200>;
 323                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 324                         ti,hwmods = "gpio3";
 325                         gpio-controller;
 326                         #gpio-cells = <2>;
 327                         interrupt-controller;
 328                         #interrupt-cells = <2>;
 329                 };
 330
 331                 gpio4: gpio@48059000 {
 332                         compatible = "ti,omap4-gpio";
 333                         reg = <0x48059000 0x200>;
 334                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 335                         ti,hwmods = "gpio4";
 336                         gpio-controller;
 337                         #gpio-cells = <2>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                 };
 341
 342                 gpio5: gpio@4805b000 {
 343                         compatible = "ti,omap4-gpio";
 344                         reg = <0x4805b000 0x200>;
 345                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 346                         ti,hwmods = "gpio5";
 347                         gpio-controller;
 348                         #gpio-cells = <2>;
 349                         interrupt-controller;
 350                         #interrupt-cells = <2>;
 351                 };
 352
 353                 gpio6: gpio@4805d000 {
 354                         compatible = "ti,omap4-gpio";
 355                         reg = <0x4805d000 0x200>;
 356                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 357                         ti,hwmods = "gpio6";
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360                         interrupt-controller;
 361                         #interrupt-cells = <2>;
 362                 };
 363
 364                 gpio7: gpio@48051000 {
 365                         compatible = "ti,omap4-gpio";
 366                         reg = <0x48051000 0x200>;
 367                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 368                         ti,hwmods = "gpio7";
 369                         gpio-controller;
 370                         #gpio-cells = <2>;
 371                         interrupt-controller;
 372                         #interrupt-cells = <2>;
 373                 };
 374
 375                 gpio8: gpio@48053000 {
 376                         compatible = "ti,omap4-gpio";
 377                         reg = <0x48053000 0x200>;
 378                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 379                         ti,hwmods = "gpio8";
 380                         gpio-controller;
 381                         #gpio-cells = <2>;
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                 };
 385
 386                 uart1: serial@4806a000 {
 387                         compatible = "ti,omap4-uart";
 388                         reg = <0x4806a000 0x100>;
 389                         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 390                         ti,hwmods = "uart1";
 391                         clock-frequency = <48000000>;
 392                         status = "disabled";
 393                         dmas = <&sdma 49>, <&sdma 50>;
 394                         dma-names = "tx", "rx";
 395                 };
 396
 397                 uart2: serial@4806c000 {
 398                         compatible = "ti,omap4-uart";
 399                         reg = <0x4806c000 0x100>;
 400                         interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 401                         ti,hwmods = "uart2";
 402                         clock-frequency = <48000000>;
 403                         status = "disabled";
 404                         dmas = <&sdma 51>, <&sdma 52>;
 405                         dma-names = "tx", "rx";
 406                 };
 407
 408                 uart3: serial@48020000 {
 409                         compatible = "ti,omap4-uart";
 410                         reg = <0x48020000 0x100>;
 411                         interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 412                         ti,hwmods = "uart3";
 413                         clock-frequency = <48000000>;
 414                         status = "disabled";
 415                         dmas = <&sdma 53>, <&sdma 54>;
 416                         dma-names = "tx", "rx";
 417                 };
 418
 419                 uart4: serial@4806e000 {
 420                         compatible = "ti,omap4-uart";
 421                         reg = <0x4806e000 0x100>;
 422                         interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 423                         ti,hwmods = "uart4";
 424                         clock-frequency = <48000000>;
 425                         status = "disabled";
 426                         dmas = <&sdma 55>, <&sdma 56>;
 427                         dma-names = "tx", "rx";
 428                 };
 429
 430                 uart5: serial@48066000 {
 431                         compatible = "ti,omap4-uart";
 432                         reg = <0x48066000 0x100>;
 433                         interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 434                         ti,hwmods = "uart5";
 435                         clock-frequency = <48000000>;
 436                         status = "disabled";
 437                         dmas = <&sdma 63>, <&sdma 64>;
 438                         dma-names = "tx", "rx";
 439                 };
 440
 441                 uart6: serial@48068000 {
 442                         compatible = "ti,omap4-uart";
 443                         reg = <0x48068000 0x100>;
 444                         interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 445                         ti,hwmods = "uart6";
 446                         clock-frequency = <48000000>;
 447                         status = "disabled";
 448                         dmas = <&sdma 79>, <&sdma 80>;
 449                         dma-names = "tx", "rx";
 450                 };
 451
 452                 uart7: serial@48420000 {
 453                         compatible = "ti,omap4-uart";
 454                         reg = <0x48420000 0x100>;
 455                         interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 456                         ti,hwmods = "uart7";
 457                         clock-frequency = <48000000>;
 458                         status = "disabled";
 459                 };
 460
 461                 uart8: serial@48422000 {
 462                         compatible = "ti,omap4-uart";
 463                         reg = <0x48422000 0x100>;
 464                         interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 465                         ti,hwmods = "uart8";
 466                         clock-frequency = <48000000>;
 467                         status = "disabled";
 468                 };
 469
 470                 uart9: serial@48424000 {
 471                         compatible = "ti,omap4-uart";
 472                         reg = <0x48424000 0x100>;
 473                         interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 474                         ti,hwmods = "uart9";
 475                         clock-frequency = <48000000>;
 476                         status = "disabled";
 477                 };
 478
 479                 uart10: serial@4ae2b000 {
 480                         compatible = "ti,omap4-uart";
 481                         reg = <0x4ae2b000 0x100>;
 482                         interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 483                         ti,hwmods = "uart10";
 484                         clock-frequency = <48000000>;
 485                         status = "disabled";
 486                 };
 487
 488                 mailbox1: mailbox@4a0f4000 {
 489                         compatible = "ti,omap4-mailbox";
 490                         reg = <0x4a0f4000 0x200>;
 491                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 492                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 493                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 494                         ti,hwmods = "mailbox1";
 495                         #mbox-cells = <1>;
 496                         ti,mbox-num-users = <3>;
 497                         ti,mbox-num-fifos = <8>;
 498                         status = "disabled";
 499                 };
 500
 501                 mailbox2: mailbox@4883a000 {
 502                         compatible = "ti,omap4-mailbox";
 503                         reg = <0x4883a000 0x200>;
 504                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 506                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 507                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 508                         ti,hwmods = "mailbox2";
 509                         #mbox-cells = <1>;
 510                         ti,mbox-num-users = <4>;
 511                         ti,mbox-num-fifos = <12>;
 512                         status = "disabled";
 513                 };
 514
 515                 mailbox3: mailbox@4883c000 {
 516                         compatible = "ti,omap4-mailbox";
 517                         reg = <0x4883c000 0x200>;
 518                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 520                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 521                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 522                         ti,hwmods = "mailbox3";
 523                         #mbox-cells = <1>;
 524                         ti,mbox-num-users = <4>;
 525                         ti,mbox-num-fifos = <12>;
 526                         status = "disabled";
 527                 };
 528
 529                 mailbox4: mailbox@4883e000 {
 530                         compatible = "ti,omap4-mailbox";
 531                         reg = <0x4883e000 0x200>;
 532                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 536                         ti,hwmods = "mailbox4";
 537                         #mbox-cells = <1>;
 538                         ti,mbox-num-users = <4>;
 539                         ti,mbox-num-fifos = <12>;
 540                         status = "disabled";
 541                 };
 542
 543                 mailbox5: mailbox@48840000 {
 544                         compatible = "ti,omap4-mailbox";
 545                         reg = <0x48840000 0x200>;
 546                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 548                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 550                         ti,hwmods = "mailbox5";
 551                         #mbox-cells = <1>;
 552                         ti,mbox-num-users = <4>;
 553                         ti,mbox-num-fifos = <12>;
 554                         status = "disabled";
 555                 };
 556
 557                 mailbox6: mailbox@48842000 {
 558                         compatible = "ti,omap4-mailbox";
 559                         reg = <0x48842000 0x200>;
 560                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 562                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 563                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 564                         ti,hwmods = "mailbox6";
 565                         #mbox-cells = <1>;
 566                         ti,mbox-num-users = <4>;
 567                         ti,mbox-num-fifos = <12>;
 568                         status = "disabled";
 569                 };
 570
 571                 mailbox7: mailbox@48844000 {
 572                         compatible = "ti,omap4-mailbox";
 573                         reg = <0x48844000 0x200>;
 574                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 575                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 576                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 577                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 578                         ti,hwmods = "mailbox7";
 579                         #mbox-cells = <1>;
 580                         ti,mbox-num-users = <4>;
 581                         ti,mbox-num-fifos = <12>;
 582                         status = "disabled";
 583                 };
 584
 585                 mailbox8: mailbox@48846000 {
 586                         compatible = "ti,omap4-mailbox";
 587                         reg = <0x48846000 0x200>;
 588                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 592                         ti,hwmods = "mailbox8";
 593                         #mbox-cells = <1>;
 594                         ti,mbox-num-users = <4>;
 595                         ti,mbox-num-fifos = <12>;
 596                         status = "disabled";
 597                 };
 598
 599                 mailbox9: mailbox@4885e000 {
 600                         compatible = "ti,omap4-mailbox";
 601                         reg = <0x4885e000 0x200>;
 602                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 604                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 605                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 606                         ti,hwmods = "mailbox9";
 607                         #mbox-cells = <1>;
 608                         ti,mbox-num-users = <4>;
 609                         ti,mbox-num-fifos = <12>;
 610                         status = "disabled";
 611                 };
 612
 613                 mailbox10: mailbox@48860000 {
 614                         compatible = "ti,omap4-mailbox";
 615                         reg = <0x48860000 0x200>;
 616                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 618                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 619                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 620                         ti,hwmods = "mailbox10";
 621                         #mbox-cells = <1>;
 622                         ti,mbox-num-users = <4>;
 623                         ti,mbox-num-fifos = <12>;
 624                         status = "disabled";
 625                 };
 626
 627                 mailbox11: mailbox@48862000 {
 628                         compatible = "ti,omap4-mailbox";
 629                         reg = <0x48862000 0x200>;
 630                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 632                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 633                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 634                         ti,hwmods = "mailbox11";
 635                         #mbox-cells = <1>;
 636                         ti,mbox-num-users = <4>;
 637                         ti,mbox-num-fifos = <12>;
 638                         status = "disabled";
 639                 };
 640
 641                 mailbox12: mailbox@48864000 {
 642                         compatible = "ti,omap4-mailbox";
 643                         reg = <0x48864000 0x200>;
 644                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 646                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 648                         ti,hwmods = "mailbox12";
 649                         #mbox-cells = <1>;
 650                         ti,mbox-num-users = <4>;
 651                         ti,mbox-num-fifos = <12>;
 652                         status = "disabled";
 653                 };
 654
 655                 mailbox13: mailbox@48802000 {
 656                         compatible = "ti,omap4-mailbox";
 657                         reg = <0x48802000 0x200>;
 658                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 662                         ti,hwmods = "mailbox13";
 663                         #mbox-cells = <1>;
 664                         ti,mbox-num-users = <4>;
 665                         ti,mbox-num-fifos = <12>;
 666                         status = "disabled";
 667                 };
 668
 669                 timer1: timer@4ae18000 {
 670                         compatible = "ti,omap5430-timer";
 671                         reg = <0x4ae18000 0x80>;
 672                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 673                         ti,hwmods = "timer1";
 674                         ti,timer-alwon;
 675                 };
 676
 677                 timer2: timer@48032000 {
 678                         compatible = "ti,omap5430-timer";
 679                         reg = <0x48032000 0x80>;
 680                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 681                         ti,hwmods = "timer2";
 682                 };
 683
 684                 timer3: timer@48034000 {
 685                         compatible = "ti,omap5430-timer";
 686                         reg = <0x48034000 0x80>;
 687                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 688                         ti,hwmods = "timer3";
 689                 };
 690
 691                 timer4: timer@48036000 {
 692                         compatible = "ti,omap5430-timer";
 693                         reg = <0x48036000 0x80>;
 694                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 695                         ti,hwmods = "timer4";
 696                 };
 697
 698                 timer5: timer@48820000 {
 699                         compatible = "ti,omap5430-timer";
 700                         reg = <0x48820000 0x80>;
 701                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 702                         ti,hwmods = "timer5";
 703                         ti,timer-dsp;
 704                 };
 705
 706                 timer6: timer@48822000 {
 707                         compatible = "ti,omap5430-timer";
 708                         reg = <0x48822000 0x80>;
 709                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 710                         ti,hwmods = "timer6";
 711                         ti,timer-dsp;
 712                         ti,timer-pwm;
 713                 };
 714
 715                 timer7: timer@48824000 {
 716                         compatible = "ti,omap5430-timer";
 717                         reg = <0x48824000 0x80>;
 718                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 719                         ti,hwmods = "timer7";
 720                         ti,timer-dsp;
 721                 };
 722
 723                 timer8: timer@48826000 {
 724                         compatible = "ti,omap5430-timer";
 725                         reg = <0x48826000 0x80>;
 726                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 727                         ti,hwmods = "timer8";
 728                         ti,timer-dsp;
 729                         ti,timer-pwm;
 730                 };
 731
 732                 timer9: timer@4803e000 {
 733                         compatible = "ti,omap5430-timer";
 734                         reg = <0x4803e000 0x80>;
 735                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 736                         ti,hwmods = "timer9";
 737                 };
 738
 739                 timer10: timer@48086000 {
 740                         compatible = "ti,omap5430-timer";
 741                         reg = <0x48086000 0x80>;
 742                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 743                         ti,hwmods = "timer10";
 744                 };
 745
 746                 timer11: timer@48088000 {
 747                         compatible = "ti,omap5430-timer";
 748                         reg = <0x48088000 0x80>;
 749                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 750                         ti,hwmods = "timer11";
 751                         ti,timer-pwm;
 752                 };
 753
 754                 timer13: timer@48828000 {
 755                         compatible = "ti,omap5430-timer";
 756                         reg = <0x48828000 0x80>;
 757                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 758                         ti,hwmods = "timer13";
 759                         status = "disabled";
 760                 };
 761
 762                 timer14: timer@4882a000 {
 763                         compatible = "ti,omap5430-timer";
 764                         reg = <0x4882a000 0x80>;
 765                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 766                         ti,hwmods = "timer14";
 767                         status = "disabled";
 768                 };
 769
 770                 timer15: timer@4882c000 {
 771                         compatible = "ti,omap5430-timer";
 772                         reg = <0x4882c000 0x80>;
 773                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 774                         ti,hwmods = "timer15";
 775                         status = "disabled";
 776                 };
 777
 778                 timer16: timer@4882e000 {
 779                         compatible = "ti,omap5430-timer";
 780                         reg = <0x4882e000 0x80>;
 781                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 782                         ti,hwmods = "timer16";
 783                         status = "disabled";
 784                 };
 785
 786                 wdt2: wdt@4ae14000 {
 787                         compatible = "ti,omap3-wdt";
 788                         reg = <0x4ae14000 0x80>;
 789                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 790                         ti,hwmods = "wd_timer2";
 791                 };
 792
 793                 hwspinlock: spinlock@4a0f6000 {
 794                         compatible = "ti,omap4-hwspinlock";
 795                         reg = <0x4a0f6000 0x1000>;
 796                         ti,hwmods = "spinlock";
 797                         #hwlock-cells = <1>;
 798                 };
 799
 800                 dmm@4e000000 {
 801                         compatible = "ti,omap5-dmm";
 802                         reg = <0x4e000000 0x800>;
 803                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 804                         ti,hwmods = "dmm";
 805                 };
 806
 807                 i2c1: i2c@48070000 {
 808                         compatible = "ti,omap4-i2c";
 809                         reg = <0x48070000 0x100>;
 810                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 811                         #address-cells = <1>;
 812                         #size-cells = <0>;
 813                         ti,hwmods = "i2c1";
 814                         status = "disabled";
 815                 };
 816
 817                 i2c2: i2c@48072000 {
 818                         compatible = "ti,omap4-i2c";
 819                         reg = <0x48072000 0x100>;
 820                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                         ti,hwmods = "i2c2";
 824                         status = "disabled";
 825                 };
 826
 827                 i2c3: i2c@48060000 {
 828                         compatible = "ti,omap4-i2c";
 829                         reg = <0x48060000 0x100>;
 830                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 831                         #address-cells = <1>;
 832                         #size-cells = <0>;
 833                         ti,hwmods = "i2c3";
 834                         status = "disabled";
 835                 };
 836
 837                 i2c4: i2c@4807a000 {
 838                         compatible = "ti,omap4-i2c";
 839                         reg = <0x4807a000 0x100>;
 840                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 841                         #address-cells = <1>;
 842                         #size-cells = <0>;
 843                         ti,hwmods = "i2c4";
 844                         status = "disabled";
 845                 };
 846
 847                 i2c5: i2c@4807c000 {
 848                         compatible = "ti,omap4-i2c";
 849                         reg = <0x4807c000 0x100>;
 850                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 851                         #address-cells = <1>;
 852                         #size-cells = <0>;
 853                         ti,hwmods = "i2c5";
 854                         status = "disabled";
 855                 };
 856
 857                 mmc1: mmc@4809c000 {
 858                         compatible = "ti,omap4-hsmmc";
 859                         reg = <0x4809c000 0x400>;
 860                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 861                         ti,hwmods = "mmc1";
 862                         ti,dual-volt;
 863                         ti,needs-special-reset;
 864                         dmas = <&sdma 61>, <&sdma 62>;
 865                         dma-names = "tx", "rx";
 866                         status = "disabled";
 867                         pbias-supply = <&pbias_mmc_reg>;
 868                 };
 869
 870                 mmc2: mmc@480b4000 {
 871                         compatible = "ti,omap4-hsmmc";
 872                         reg = <0x480b4000 0x400>;
 873                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 874                         ti,hwmods = "mmc2";
 875                         ti,needs-special-reset;
 876                         dmas = <&sdma 47>, <&sdma 48>;
 877                         dma-names = "tx", "rx";
 878                         status = "disabled";
 879                 };
 880
 881                 mmc3: mmc@480ad000 {
 882                         compatible = "ti,omap4-hsmmc";
 883                         reg = <0x480ad000 0x400>;
 884                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 885                         ti,hwmods = "mmc3";
 886                         ti,needs-special-reset;
 887                         dmas = <&sdma 77>, <&sdma 78>;
 888                         dma-names = "tx", "rx";
 889                         status = "disabled";
 890                 };
 891
 892                 mmc4: mmc@480d1000 {
 893                         compatible = "ti,omap4-hsmmc";
 894                         reg = <0x480d1000 0x400>;
 895                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 896                         ti,hwmods = "mmc4";
 897                         ti,needs-special-reset;
 898                         dmas = <&sdma 57>, <&sdma 58>;
 899                         dma-names = "tx", "rx";
 900                         status = "disabled";
 901                 };
 902
 903                 abb_mpu: regulator-abb-mpu {
 904                         compatible = "ti,abb-v3";
 905                         regulator-name = "abb_mpu";
 906                         #address-cells = <0>;
 907                         #size-cells = <0>;
 908                         clocks = <&sys_clkin1>;
 909                         ti,settling-time = <50>;
 910                         ti,clock-cycles = <16>;
 911
 912                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 913                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 914                               <0x4ae0c158 0x4>;
 915                         reg-names = "setup-address", "control-address",
 916                                     "int-address", "efuse-address",
 917                                     "ldo-address";
 918                         ti,tranxdone-status-mask = <0x80>;
 919                         /* LDOVBBMPU_FBB_MUX_CTRL */
 920                         ti,ldovbb-override-mask = <0x400>;
 921                         /* LDOVBBMPU_FBB_VSET_OUT */
 922                         ti,ldovbb-vset-mask = <0x1F>;
 923
 924                         /*
 925                          * NOTE: only FBB mode used but actual vset will
 926                          * determine final biasing
 927                          */
 928                         ti,abb_info = <
 929                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 930                         1060000         0       0x0     0 0x02000000 0x01F00000
 931                         1160000         0       0x4     0 0x02000000 0x01F00000
 932                         1210000         0       0x8     0 0x02000000 0x01F00000
 933                         >;
 934                 };
 935
 936                 abb_ivahd: regulator-abb-ivahd {
 937                         compatible = "ti,abb-v3";
 938                         regulator-name = "abb_ivahd";
 939                         #address-cells = <0>;
 940                         #size-cells = <0>;
 941                         clocks = <&sys_clkin1>;
 942                         ti,settling-time = <50>;
 943                         ti,clock-cycles = <16>;
 944
 945                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 946                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 947                               <0x4a002470 0x4>;
 948                         reg-names = "setup-address", "control-address",
 949                                     "int-address", "efuse-address",
 950                                     "ldo-address";
 951                         ti,tranxdone-status-mask = <0x40000000>;
 952                         /* LDOVBBIVA_FBB_MUX_CTRL */
 953                         ti,ldovbb-override-mask = <0x400>;
 954                         /* LDOVBBIVA_FBB_VSET_OUT */
 955                         ti,ldovbb-vset-mask = <0x1F>;
 956
 957                         /*
 958                          * NOTE: only FBB mode used but actual vset will
 959                          * determine final biasing
 960                          */
 961                         ti,abb_info = <
 962                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 963                         1055000         0       0x0     0 0x02000000 0x01F00000
 964                         1150000         0       0x4     0 0x02000000 0x01F00000
 965                         1250000         0       0x8     0 0x02000000 0x01F00000
 966                         >;
 967                 };
 968
 969                 abb_dspeve: regulator-abb-dspeve {
 970                         compatible = "ti,abb-v3";
 971                         regulator-name = "abb_dspeve";
 972                         #address-cells = <0>;
 973                         #size-cells = <0>;
 974                         clocks = <&sys_clkin1>;
 975                         ti,settling-time = <50>;
 976                         ti,clock-cycles = <16>;
 977
 978                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 979                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 980                               <0x4a00246c 0x4>;
 981                         reg-names = "setup-address", "control-address",
 982                                     "int-address", "efuse-address",
 983                                     "ldo-address";
 984                         ti,tranxdone-status-mask = <0x20000000>;
 985                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 986                         ti,ldovbb-override-mask = <0x400>;
 987                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 988                         ti,ldovbb-vset-mask = <0x1F>;
 989
 990                         /*
 991                          * NOTE: only FBB mode used but actual vset will
 992                          * determine final biasing
 993                          */
 994                         ti,abb_info = <
 995                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 996                         1055000         0       0x0     0 0x02000000 0x01F00000
 997                         1150000         0       0x4     0 0x02000000 0x01F00000
 998                         1250000         0       0x8     0 0x02000000 0x01F00000
 999                         >;
1000                 };
1001
1002                 abb_gpu: regulator-abb-gpu {
1003                         compatible = "ti,abb-v3";
1004                         regulator-name = "abb_gpu";
1005                         #address-cells = <0>;
1006                         #size-cells = <0>;
1007                         clocks = <&sys_clkin1>;
1008                         ti,settling-time = <50>;
1009                         ti,clock-cycles = <16>;
1010
1011                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1012                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
1013                               <0x4ae0c154 0x4>;
1014                         reg-names = "setup-address", "control-address",
1015                                     "int-address", "efuse-address",
1016                                     "ldo-address";
1017                         ti,tranxdone-status-mask = <0x10000000>;
1018                         /* LDOVBBGPU_FBB_MUX_CTRL */
1019                         ti,ldovbb-override-mask = <0x400>;
1020                         /* LDOVBBGPU_FBB_VSET_OUT */
1021                         ti,ldovbb-vset-mask = <0x1F>;
1022
1023                         /*
1024                          * NOTE: only FBB mode used but actual vset will
1025                          * determine final biasing
1026                          */
1027                         ti,abb_info = <
1028                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1029                         1090000         0       0x0     0 0x02000000 0x01F00000
1030                         1210000         0       0x4     0 0x02000000 0x01F00000
1031                         1280000         0       0x8     0 0x02000000 0x01F00000
1032                         >;
1033                 };
1034
1035                 mcspi1: spi@48098000 {
1036                         compatible = "ti,omap4-mcspi";
1037                         reg = <0x48098000 0x200>;
1038                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041                         ti,hwmods = "mcspi1";
1042                         ti,spi-num-cs = <4>;
1043                         dmas = <&sdma 35>,
1044                                <&sdma 36>,
1045                                <&sdma 37>,
1046                                <&sdma 38>,
1047                                <&sdma 39>,
1048                                <&sdma 40>,
1049                                <&sdma 41>,
1050                                <&sdma 42>;
1051                         dma-names = "tx0", "rx0", "tx1", "rx1",
1052                                     "tx2", "rx2", "tx3", "rx3";
1053                         status = "disabled";
1054                 };
1055
1056                 mcspi2: spi@4809a000 {
1057                         compatible = "ti,omap4-mcspi";
1058                         reg = <0x4809a000 0x200>;
1059                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1060                         #address-cells = <1>;
1061                         #size-cells = <0>;
1062                         ti,hwmods = "mcspi2";
1063                         ti,spi-num-cs = <2>;
1064                         dmas = <&sdma 43>,
1065                                <&sdma 44>,
1066                                <&sdma 45>,
1067                                <&sdma 46>;
1068                         dma-names = "tx0", "rx0", "tx1", "rx1";
1069                         status = "disabled";
1070                 };
1071
1072                 mcspi3: spi@480b8000 {
1073                         compatible = "ti,omap4-mcspi";
1074                         reg = <0x480b8000 0x200>;
1075                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1076                         #address-cells = <1>;
1077                         #size-cells = <0>;
1078                         ti,hwmods = "mcspi3";
1079                         ti,spi-num-cs = <2>;
1080                         dmas = <&sdma 15>, <&sdma 16>;
1081                         dma-names = "tx0", "rx0";
1082                         status = "disabled";
1083                 };
1084
1085                 mcspi4: spi@480ba000 {
1086                         compatible = "ti,omap4-mcspi";
1087                         reg = <0x480ba000 0x200>;
1088                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1089                         #address-cells = <1>;
1090                         #size-cells = <0>;
1091                         ti,hwmods = "mcspi4";
1092                         ti,spi-num-cs = <1>;
1093                         dmas = <&sdma 70>, <&sdma 71>;
1094                         dma-names = "tx0", "rx0";
1095                         status = "disabled";
1096                 };
1097
1098                 qspi: qspi@4b300000 {
1099                         compatible = "ti,dra7xxx-qspi";
1100                         reg = <0x4b300000 0x100>;
1101                         reg-names = "qspi_base";
1102                         #address-cells = <1>;
1103                         #size-cells = <0>;
1104                         ti,hwmods = "qspi";
1105                         clocks = <&qspi_gfclk_div>;
1106                         clock-names = "fck";
1107                         num-cs = <4>;
1108                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1109                         status = "disabled";
1110                 };
1111
1112                 omap_control_sata: control-phy@4a002374 {
1113                         compatible = "ti,control-phy-pipe3";
1114                         reg = <0x4a002374 0x4>;
1115                         reg-names = "power";
1116                         clocks = <&sys_clkin1>;
1117                         clock-names = "sysclk";
1118                 };
1119
1120                 /* OCP2SCP3 */
1121                 ocp2scp@4a090000 {
1122                         compatible = "ti,omap-ocp2scp";
1123                         #address-cells = <1>;
1124                         #size-cells = <1>;
1125                         ranges;
1126                         reg = <0x4a090000 0x20>;
1127                         ti,hwmods = "ocp2scp3";
1128                         sata_phy: phy@4A096000 {
1129                                 compatible = "ti,phy-pipe3-sata";
1130                                 reg = <0x4A096000 0x80>, /* phy_rx */
1131                                       <0x4A096400 0x64>, /* phy_tx */
1132                                       <0x4A096800 0x40>; /* pll_ctrl */
1133                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1134                                 ctrl-module = <&omap_control_sata>;
1135                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1136                                 clock-names = "sysclk", "refclk";
1137                                 #phy-cells = <0>;
1138                         };
1139
1140                         pcie1_phy: pciephy@4a094000 {
1141                                 compatible = "ti,phy-pipe3-pcie";
1142                                 reg = <0x4a094000 0x80>, /* phy_rx */
1143                                       <0x4a094400 0x64>; /* phy_tx */
1144                                 reg-names = "phy_rx", "phy_tx";
1145                                 ctrl-module = <&omap_control_pcie1phy>;
1146                                 clocks = <&dpll_pcie_ref_ck>,
1147                                          <&dpll_pcie_ref_m2ldo_ck>,
1148                                          <&optfclk_pciephy1_32khz>,
1149                                          <&optfclk_pciephy1_clk>,
1150                                          <&optfclk_pciephy1_div_clk>,
1151                                          <&optfclk_pciephy_div>;
1152                                 clock-names = "dpll_ref", "dpll_ref_m2",
1153                                               "wkupclk", "refclk",
1154                                               "div-clk", "phy-div";
1155                                 #phy-cells = <0>;
1156                                 ti,hwmods = "pcie1-phy";
1157                         };
1158
1159                         pcie2_phy: pciephy@4a095000 {
1160                                 compatible = "ti,phy-pipe3-pcie";
1161                                 reg = <0x4a095000 0x80>, /* phy_rx */
1162                                       <0x4a095400 0x64>; /* phy_tx */
1163                                 reg-names = "phy_rx", "phy_tx";
1164                                 ctrl-module = <&omap_control_pcie2phy>;
1165                                 clocks = <&dpll_pcie_ref_ck>,
1166                                          <&dpll_pcie_ref_m2ldo_ck>,
1167                                          <&optfclk_pciephy2_32khz>,
1168                                          <&optfclk_pciephy2_clk>,
1169                                          <&optfclk_pciephy2_div_clk>,
1170                                          <&optfclk_pciephy_div>;
1171                                 clock-names = "dpll_ref", "dpll_ref_m2",
1172                                               "wkupclk", "refclk",
1173                                               "div-clk", "phy-div";
1174                                 #phy-cells = <0>;
1175                                 ti,hwmods = "pcie2-phy";
1176                                 status = "disabled";
1177                         };
1178                 };
1179
1180                 sata: sata@4a141100 {
1181                         compatible = "snps,dwc-ahci";
1182                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1183                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1184                         phys = <&sata_phy>;
1185                         phy-names = "sata-phy";
1186                         clocks = <&sata_ref_clk>;
1187                         ti,hwmods = "sata";
1188                 };
1189
1190                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1191                         compatible = "ti,control-phy-pcie";
1192                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1193                         reg-names = "power", "control_sma", "pcie_pcs";
1194                         clocks = <&sys_clkin1>;
1195                         clock-names = "sysclk";
1196                 };
1197
1198                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1199                         compatible = "ti,control-phy-pcie";
1200                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1201                         reg-names = "power", "control_sma", "pcie_pcs";
1202                         clocks = <&sys_clkin1>;
1203                         clock-names = "sysclk";
1204                         status = "disabled";
1205                 };
1206
1207                 rtc@48838000 {
1208                         compatible = "ti,am3352-rtc";
1209                         reg = <0x48838000 0x100>;
1210                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1212                         ti,hwmods = "rtcss";
1213                         clocks = <&sys_32k_ck>;
1214                 };
1215
1216                 omap_control_usb2phy1: control-phy@4a002300 {
1217                         compatible = "ti,control-phy-usb2";
1218                         reg = <0x4a002300 0x4>;
1219                         reg-names = "power";
1220                 };
1221
1222                 omap_control_usb3phy1: control-phy@4a002370 {
1223                         compatible = "ti,control-phy-pipe3";
1224                         reg = <0x4a002370 0x4>;
1225                         reg-names = "power";
1226                 };
1227
1228                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1229                         compatible = "ti,control-phy-usb2-dra7";
1230                         reg = <0x4a002e74 0x4>;
1231                         reg-names = "power";
1232                 };
1233
1234                 /* OCP2SCP1 */
1235                 ocp2scp@4a080000 {
1236                         compatible = "ti,omap-ocp2scp";
1237                         #address-cells = <1>;
1238                         #size-cells = <1>;
1239                         ranges;
1240                         reg = <0x4a080000 0x20>;
1241                         ti,hwmods = "ocp2scp1";
1242
1243                         usb2_phy1: phy@4a084000 {
1244                                 compatible = "ti,omap-usb2";
1245                                 reg = <0x4a084000 0x400>;
1246                                 ctrl-module = <&omap_control_usb2phy1>;
1247                                 clocks = <&usb_phy1_always_on_clk32k>,
1248                                          <&usb_otg_ss1_refclk960m>;
1249                                 clock-names =   "wkupclk",
1250                                                 "refclk";
1251                                 #phy-cells = <0>;
1252                         };
1253
1254                         usb2_phy2: phy@4a085000 {
1255                                 compatible = "ti,omap-usb2";
1256                                 reg = <0x4a085000 0x400>;
1257                                 ctrl-module = <&omap_control_usb2phy2>;
1258                                 clocks = <&usb_phy2_always_on_clk32k>,
1259                                          <&usb_otg_ss2_refclk960m>;
1260                                 clock-names =   "wkupclk",
1261                                                 "refclk";
1262                                 #phy-cells = <0>;
1263                         };
1264
1265                         usb3_phy1: phy@4a084400 {
1266                                 compatible = "ti,omap-usb3";
1267                                 reg = <0x4a084400 0x80>,
1268                                       <0x4a084800 0x64>,
1269                                       <0x4a084c00 0x40>;
1270                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1271                                 ctrl-module = <&omap_control_usb3phy1>;
1272                                 clocks = <&usb_phy3_always_on_clk32k>,
1273                                          <&sys_clkin1>,
1274                                          <&usb_otg_ss1_refclk960m>;
1275                                 clock-names =   "wkupclk",
1276                                                 "sysclk",
1277                                                 "refclk";
1278                                 #phy-cells = <0>;
1279                         };
1280                 };
1281
1282                 omap_dwc3_1: omap_dwc3_1@48880000 {
1283                         compatible = "ti,dwc3";
1284                         ti,hwmods = "usb_otg_ss1";
1285                         reg = <0x48880000 0x10000>;
1286                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1287                         #address-cells = <1>;
1288                         #size-cells = <1>;
1289                         utmi-mode = <2>;
1290                         ranges;
1291                         usb1: usb@48890000 {
1292                                 compatible = "snps,dwc3";
1293                                 reg = <0x48890000 0x17000>;
1294                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1295                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1296                                 phy-names = "usb2-phy", "usb3-phy";
1297                                 tx-fifo-resize;
1298                                 maximum-speed = "super-speed";
1299                                 dr_mode = "otg";
1300                                 snps,dis_u3_susphy_quirk;
1301                                 snps,dis_u2_susphy_quirk;
1302                         };
1303                 };
1304
1305                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1306                         compatible = "ti,dwc3";
1307                         ti,hwmods = "usb_otg_ss2";
1308                         reg = <0x488c0000 0x10000>;
1309                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1310                         #address-cells = <1>;
1311                         #size-cells = <1>;
1312                         utmi-mode = <2>;
1313                         ranges;
1314                         usb2: usb@488d0000 {
1315                                 compatible = "snps,dwc3";
1316                                 reg = <0x488d0000 0x17000>;
1317                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1318                                 phys = <&usb2_phy2>;
1319                                 phy-names = "usb2-phy";
1320                                 tx-fifo-resize;
1321                                 maximum-speed = "high-speed";
1322                                 dr_mode = "otg";
1323                                 snps,dis_u3_susphy_quirk;
1324                                 snps,dis_u2_susphy_quirk;
1325                         };
1326                 };
1327
1328                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1329                 omap_dwc3_3: omap_dwc3_3@48900000 {
1330                         compatible = "ti,dwc3";
1331                         ti,hwmods = "usb_otg_ss3";
1332                         reg = <0x48900000 0x10000>;
1333                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1334                         #address-cells = <1>;
1335                         #size-cells = <1>;
1336                         utmi-mode = <2>;
1337                         ranges;
1338                         status = "disabled";
1339                         usb3: usb@48910000 {
1340                                 compatible = "snps,dwc3";
1341                                 reg = <0x48910000 0x17000>;
1342                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1343                                 tx-fifo-resize;
1344                                 maximum-speed = "high-speed";
1345                                 dr_mode = "otg";
1346                                 snps,dis_u3_susphy_quirk;
1347                                 snps,dis_u2_susphy_quirk;
1348                         };
1349                 };
1350
1351                 elm: elm@48078000 {
1352                         compatible = "ti,am3352-elm";
1353                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1354                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1355                         ti,hwmods = "elm";
1356                         status = "disabled";
1357                 };
1358
1359                 gpmc: gpmc@50000000 {
1360                         compatible = "ti,am3352-gpmc";
1361                         ti,hwmods = "gpmc";
1362                         reg = <0x50000000 0x37c>;      /* device IO registers */
1363                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1364                         gpmc,num-cs = <8>;
1365                         gpmc,num-waitpins = <2>;
1366                         #address-cells = <2>;
1367                         #size-cells = <1>;
1368                         status = "disabled";
1369                 };
1370
1371                 atl: atl@4843c000 {
1372                         compatible = "ti,dra7-atl";
1373                         reg = <0x4843c000 0x3ff>;
1374                         ti,hwmods = "atl";
1375                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1376                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1377                         clocks = <&atl_gfclk_mux>;
1378                         clock-names = "fck";
1379                         status = "disabled";
1380                 };
1381
1382                 crossbar_mpu: crossbar@4a020000 {
1383                         compatible = "ti,irq-crossbar";
1384                         reg = <0x4a002a48 0x130>;
1385                         ti,max-irqs = <160>;
1386                         ti,max-crossbar-sources = <MAX_SOURCES>;
1387                         ti,reg-size = <2>;
1388                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1389                         ti,irqs-skip = <10 133 139 140>;
1390                         ti,irqs-safe-map = <0>;
1391                 };
1392
1393                 mac: ethernet@4a100000 {
1394                         compatible = "ti,cpsw";
1395                         ti,hwmods = "gmac";
1396                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1397                         clock-names = "fck", "cpts";
1398                         cpdma_channels = <8>;
1399                         ale_entries = <1024>;
1400                         bd_ram_size = <0x2000>;
1401                         no_bd_ram = <0>;
1402                         rx_descs = <64>;
1403                         mac_control = <0x20>;
1404                         slaves = <2>;
1405                         active_slave = <0>;
1406                         cpts_clock_mult = <0x80000000>;
1407                         cpts_clock_shift = <29>;
1408                         reg = <0x48484000 0x1000
1409                                0x48485200 0x2E00>;
1410                         #address-cells = <1>;
1411                         #size-cells = <1>;
1412                         /*
1413                          * rx_thresh_pend
1414                          * rx_pend
1415                          * tx_pend
1416                          * misc_pend
1417                          */
1418                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1419                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1420                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1421                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1422                         ranges;
1423                         status = "disabled";
1424
1425                         davinci_mdio: mdio@48485000 {
1426                                 compatible = "ti,davinci_mdio";
1427                                 #address-cells = <1>;
1428                                 #size-cells = <0>;
1429                                 ti,hwmods = "davinci_mdio";
1430                                 bus_freq = <1000000>;
1431                                 reg = <0x48485000 0x100>;
1432                         };
1433
1434                         cpsw_emac0: slave@48480200 {
1435                                 /* Filled in by U-Boot */
1436                                 mac-address = [ 00 00 00 00 00 00 ];
1437                         };
1438
1439                         cpsw_emac1: slave@48480300 {
1440                                 /* Filled in by U-Boot */
1441                                 mac-address = [ 00 00 00 00 00 00 ];
1442                         };
1443
1444                         phy_sel: cpsw-phy-sel@4a002554 {
1445                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1446                                 reg= <0x4a002554 0x4>;
1447                                 reg-names = "gmii-sel";
1448                         };
1449                 };
1450
1451                 dcan1: can@481cc000 {
1452                         compatible = "ti,dra7-d_can";
1453                         ti,hwmods = "dcan1";
1454                         reg = <0x4ae3c000 0x2000>;
1455                         syscon-raminit = <&scm_conf 0x558 0>;
1456                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1457                         clocks = <&dcan1_sys_clk_mux>;
1458                         status = "disabled";
1459                 };
1460
1461                 dcan2: can@481d0000 {
1462                         compatible = "ti,dra7-d_can";
1463                         ti,hwmods = "dcan2";
1464                         reg = <0x48480000 0x2000>;
1465                         syscon-raminit = <&scm_conf 0x558 1>;
1466                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1467                         clocks = <&sys_clkin1>;
1468                         status = "disabled";
1469                 };
1470         };
1471
1472         thermal_zones: thermal-zones {
1473                 #include "omap4-cpu-thermal.dtsi"
1474                 #include "omap5-gpu-thermal.dtsi"
1475                 #include "omap5-core-thermal.dtsi"
1476         };
1477
1478 };
1479
1480 &cpu_thermal {
1481         polling-delay = <500>; /* milliseconds */
1482 };
1483
1484 /include/ "dra7xx-clocks.dtsi"