arch/arm/boot/dts/dra7-l4.dtsi

   1 &l4_cfg {                                               /* 0x4a000000 */
   2         compatible = "ti,dra7-l4-cfg", "simple-bus";
   3         reg = <0x4a000000 0x800>,
   4               <0x4a000800 0x800>,
   5               <0x4a001000 0x1000>;
   6         reg-names = "ap", "la", "ia0";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         ranges = <0x00000000 0x4a000000 0x100000>,      /* segment 0 */
  10                  <0x00100000 0x4a100000 0x100000>,      /* segment 1 */
  11                  <0x00200000 0x4a200000 0x100000>;      /* segment 2 */
  12
  13         segment@0 {                                     /* 0x4a000000 */
  14                 compatible = "simple-bus";
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
  18                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
  19                          <0x00001000 0x00001000 0x001000>,      /* ap 2 */
  20                          <0x00002000 0x00002000 0x002000>,      /* ap 3 */
  21                          <0x00004000 0x00004000 0x001000>,      /* ap 4 */
  22                          <0x00005000 0x00005000 0x001000>,      /* ap 5 */
  23                          <0x00006000 0x00006000 0x001000>,      /* ap 6 */
  24                          <0x00008000 0x00008000 0x002000>,      /* ap 7 */
  25                          <0x0000a000 0x0000a000 0x001000>,      /* ap 8 */
  26                          <0x00056000 0x00056000 0x001000>,      /* ap 9 */
  27                          <0x00057000 0x00057000 0x001000>,      /* ap 10 */
  28                          <0x0005e000 0x0005e000 0x002000>,      /* ap 11 */
  29                          <0x00060000 0x00060000 0x001000>,      /* ap 12 */
  30                          <0x00080000 0x00080000 0x008000>,      /* ap 13 */
  31                          <0x00088000 0x00088000 0x001000>,      /* ap 14 */
  32                          <0x000a0000 0x000a0000 0x008000>,      /* ap 15 */
  33                          <0x000a8000 0x000a8000 0x001000>,      /* ap 16 */
  34                          <0x000d9000 0x000d9000 0x001000>,      /* ap 17 */
  35                          <0x000da000 0x000da000 0x001000>,      /* ap 18 */
  36                          <0x000dd000 0x000dd000 0x001000>,      /* ap 19 */
  37                          <0x000de000 0x000de000 0x001000>,      /* ap 20 */
  38                          <0x000e0000 0x000e0000 0x001000>,      /* ap 21 */
  39                          <0x000e1000 0x000e1000 0x001000>,      /* ap 22 */
  40                          <0x000f4000 0x000f4000 0x001000>,      /* ap 23 */
  41                          <0x000f5000 0x000f5000 0x001000>,      /* ap 24 */
  42                          <0x000f6000 0x000f6000 0x001000>,      /* ap 25 */
  43                          <0x000f7000 0x000f7000 0x001000>,      /* ap 26 */
  44                          <0x00090000 0x00090000 0x008000>,      /* ap 59 */
  45                          <0x00098000 0x00098000 0x001000>;      /* ap 60 */
  46
  47                 target-module@2000 {                    /* 0x4a002000, ap 3 08.0 */
  48                         compatible = "ti,sysc-omap4", "ti,sysc";
  49                         reg = <0x2000 0x4>;
  50                         reg-names = "rev";
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53                         ranges = <0x0 0x2000 0x2000>;
  54
  55                         scm: scm@0 {
  56                                 compatible = "ti,dra7-scm-core", "simple-bus";
  57                                 reg = <0 0x2000>;
  58                                 #address-cells = <1>;
  59                                 #size-cells = <1>;
  60                                 ranges = <0 0 0x2000>;
  61
  62                                 scm_conf: scm_conf@0 {
  63                                         compatible = "syscon", "simple-bus";
  64                                         reg = <0x0 0x1400>;
  65                                         #address-cells = <1>;
  66                                         #size-cells = <1>;
  67                                         ranges = <0 0x0 0x1400>;
  68
  69                                         pbias_regulator: pbias_regulator@e00 {
  70                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
  71                                                 reg = <0xe00 0x4>;
  72                                                 syscon = <&scm_conf>;
  73                                                 pbias_mmc_reg: pbias_mmc_omap5 {
  74                                                         regulator-name = "pbias_mmc_omap5";
  75                                                         regulator-min-microvolt = <1800000>;
  76                                                         regulator-max-microvolt = <3300000>;
  77                                                 };
  78                                         };
  79
  80                                         phy_gmii_sel: phy-gmii-sel {
  81                                                 compatible = "ti,dra7xx-phy-gmii-sel";
  82                                                 reg = <0x554 0x4>;
  83                                                 #phy-cells = <1>;
  84                                         };
  85
  86                                         scm_conf_clocks: clocks {
  87                                                 #address-cells = <1>;
  88                                                 #size-cells = <0>;
  89                                         };
  90                                 };
  91
  92                                 dra7_pmx_core: pinmux@1400 {
  93                                         compatible = "ti,dra7-padconf",
  94                                                      "pinctrl-single";
  95                                         reg = <0x1400 0x0468>;
  96                                         #address-cells = <1>;
  97                                         #size-cells = <0>;
  98                                         #pinctrl-cells = <1>;
  99                                         #interrupt-cells = <1>;
 100                                         interrupt-controller;
 101                                         pinctrl-single,register-width = <32>;
 102                                         pinctrl-single,function-mask = <0x3fffffff>;
 103                                 };
 104
 105                                 scm_conf1: scm_conf@1c04 {
 106                                         compatible = "syscon";
 107                                         reg = <0x1c04 0x0020>;
 108                                         #syscon-cells = <2>;
 109                                 };
 110
 111                                 scm_conf_pcie: scm_conf@1c24 {
 112                                         compatible = "syscon";
 113                                         reg = <0x1c24 0x0024>;
 114                                 };
 115
 116                                 sdma_xbar: dma-router@b78 {
 117                                         compatible = "ti,dra7-dma-crossbar";
 118                                         reg = <0xb78 0xfc>;
 119                                         #dma-cells = <1>;
 120                                         dma-requests = <205>;
 121                                         ti,dma-safe-map = <0>;
 122                                         dma-masters = <&sdma>;
 123                                 };
 124
 125                                 edma_xbar: dma-router@c78 {
 126                                         compatible = "ti,dra7-dma-crossbar";
 127                                         reg = <0xc78 0x7c>;
 128                                         #dma-cells = <2>;
 129                                         dma-requests = <204>;
 130                                         ti,dma-safe-map = <0>;
 131                                         dma-masters = <&edma>;
 132                                 };
 133                         };
 134                 };
 135
 136                 target-module@5000 {                    /* 0x4a005000, ap 5 10.0 */
 137                         compatible = "ti,sysc-omap4", "ti,sysc";
 138                         reg = <0x5000 0x4>;
 139                         reg-names = "rev";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         ranges = <0x0 0x5000 0x1000>;
 143
 144                         cm_core_aon: cm_core_aon@0 {
 145                                 compatible = "ti,dra7-cm-core-aon",
 146                                               "simple-bus";
 147                                 #address-cells = <1>;
 148                                 #size-cells = <1>;
 149                                 reg = <0 0x2000>;
 150                                 ranges = <0 0 0x2000>;
 151
 152                                 cm_core_aon_clocks: clocks {
 153                                         #address-cells = <1>;
 154                                         #size-cells = <0>;
 155                                 };
 156
 157                                 cm_core_aon_clockdomains: clockdomains {
 158                                 };
 159                         };
 160                 };
 161
 162                 target-module@8000 {                    /* 0x4a008000, ap 7 0e.0 */
 163                         compatible = "ti,sysc-omap4", "ti,sysc";
 164                         reg = <0x8000 0x4>;
 165                         reg-names = "rev";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x0 0x8000 0x2000>;
 169
 170                         cm_core: cm_core@0 {
 171                                 compatible = "ti,dra7-cm-core", "simple-bus";
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 reg = <0 0x3000>;
 175                                 ranges = <0 0 0x3000>;
 176
 177                                 cm_core_clocks: clocks {
 178                                         #address-cells = <1>;
 179                                         #size-cells = <0>;
 180                                 };
 181
 182                                 cm_core_clockdomains: clockdomains {
 183                                 };
 184                         };
 185                 };
 186
 187                 target-module@56000 {                   /* 0x4a056000, ap 9 02.0 */
 188                         compatible = "ti,sysc-omap2", "ti,sysc";
 189                         reg = <0x56000 0x4>,
 190                               <0x5602c 0x4>,
 191                               <0x56028 0x4>;
 192                         reg-names = "rev", "sysc", "syss";
 193                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 194                                          SYSC_OMAP2_EMUFREE |
 195                                          SYSC_OMAP2_SOFTRESET |
 196                                          SYSC_OMAP2_AUTOIDLE)>;
 197                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 198                                         <SYSC_IDLE_NO>,
 199                                         <SYSC_IDLE_SMART>,
 200                                         <SYSC_IDLE_SMART_WKUP>;
 201                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 202                                         <SYSC_IDLE_NO>,
 203                                         <SYSC_IDLE_SMART>,
 204                                         <SYSC_IDLE_SMART_WKUP>;
 205                         ti,syss-mask = <1>;
 206                         /* Domains (P, C): core_pwrdm, dma_clkdm */
 207                         clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
 208                         clock-names = "fck";
 209                         #address-cells = <1>;
 210                         #size-cells = <1>;
 211                         ranges = <0x0 0x56000 0x1000>;
 212
 213                         sdma: dma-controller@0 {
 214                                 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
 215                                 reg = <0x0 0x1000>;
 216                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 217                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 218                                              <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 219                                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 220                                 #dma-cells = <1>;
 221                                 dma-channels = <32>;
 222                                 dma-requests = <127>;
 223                         };
 224                 };
 225
 226                 target-module@5e000 {                   /* 0x4a05e000, ap 11 1a.0 */
 227                         compatible = "ti,sysc";
 228                         status = "disabled";
 229                         #address-cells = <1>;
 230                         #size-cells = <1>;
 231                         ranges = <0x0 0x5e000 0x2000>;
 232                 };
 233
 234                 target-module@80000 {                   /* 0x4a080000, ap 13 20.0 */
 235                         compatible = "ti,sysc-omap2", "ti,sysc";
 236                         reg = <0x80000 0x4>,
 237                               <0x80010 0x4>,
 238                               <0x80014 0x4>;
 239                         reg-names = "rev", "sysc", "syss";
 240                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 241                                          SYSC_OMAP2_AUTOIDLE)>;
 242                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 243                                         <SYSC_IDLE_NO>,
 244                                         <SYSC_IDLE_SMART>;
 245                         ti,syss-mask = <1>;
 246                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 247                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
 248                         clock-names = "fck";
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         ranges = <0x0 0x80000 0x8000>;
 252
 253                         ocp2scp@0 {
 254                                 compatible = "ti,omap-ocp2scp";
 255                                 #address-cells = <1>;
 256                                 #size-cells = <1>;
 257                                 ranges = <0 0 0x8000>;
 258                                 reg = <0x0 0x20>;
 259
 260                                 usb2_phy1: phy@4000 {
 261                                         compatible = "ti,dra7x-usb2", "ti,omap-usb2";
 262                                         reg = <0x4000 0x400>;
 263                                         syscon-phy-power = <&scm_conf 0x300>;
 264                                         clocks = <&usb_phy1_always_on_clk32k>,
 265                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 266                                         clock-names =   "wkupclk",
 267                                                         "refclk";
 268                                         #phy-cells = <0>;
 269                                 };
 270
 271                                 usb2_phy2: phy@5000 {
 272                                         compatible = "ti,dra7x-usb2-phy2",
 273                                                      "ti,omap-usb2";
 274                                         reg = <0x5000 0x400>;
 275                                         syscon-phy-power = <&scm_conf 0xe74>;
 276                                         clocks = <&usb_phy2_always_on_clk32k>,
 277                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
 278                                         clock-names =   "wkupclk",
 279                                                         "refclk";
 280                                         #phy-cells = <0>;
 281                                 };
 282
 283                                 usb3_phy1: phy@4400 {
 284                                         compatible = "ti,omap-usb3";
 285                                         reg = <0x4400 0x80>,
 286                                               <0x4800 0x64>,
 287                                               <0x4c00 0x40>;
 288                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 289                                         syscon-phy-power = <&scm_conf 0x370>;
 290                                         clocks = <&usb_phy3_always_on_clk32k>,
 291                                                  <&sys_clkin1>,
 292                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 293                                         clock-names =   "wkupclk",
 294                                                         "sysclk",
 295                                                         "refclk";
 296                                         #phy-cells = <0>;
 297                                 };
 298                         };
 299                 };
 300
 301                 target-module@90000 {                   /* 0x4a090000, ap 59 42.0 */
 302                         compatible = "ti,sysc-omap2", "ti,sysc";
 303                         reg = <0x90000 0x4>,
 304                               <0x90010 0x4>,
 305                               <0x90014 0x4>;
 306                         reg-names = "rev", "sysc", "syss";
 307                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 308                                          SYSC_OMAP2_AUTOIDLE)>;
 309                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 310                                         <SYSC_IDLE_NO>,
 311                                         <SYSC_IDLE_SMART>;
 312                         ti,syss-mask = <1>;
 313                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 314                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
 315                         clock-names = "fck";
 316                         #address-cells = <1>;
 317                         #size-cells = <1>;
 318                         ranges = <0x0 0x90000 0x8000>;
 319
 320                         ocp2scp@0 {
 321                                 compatible = "ti,omap-ocp2scp";
 322                                 #address-cells = <1>;
 323                                 #size-cells = <1>;
 324                                 ranges = <0 0 0x8000>;
 325                                 reg = <0x0 0x20>;
 326
 327                                 pcie1_phy: pciephy@4000 {
 328                                         compatible = "ti,phy-pipe3-pcie";
 329                                         reg = <0x4000 0x80>, /* phy_rx */
 330                                               <0x4400 0x64>; /* phy_tx */
 331                                         reg-names = "phy_rx", "phy_tx";
 332                                         syscon-phy-power = <&scm_conf_pcie 0x1c>;
 333                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 334                                         clocks = <&dpll_pcie_ref_ck>,
 335                                                  <&dpll_pcie_ref_m2ldo_ck>,
 336                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
 337                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
 338                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
 339                                                  <&optfclk_pciephy_div>,
 340                                                  <&sys_clkin1>;
 341                                         clock-names = "dpll_ref", "dpll_ref_m2",
 342                                                       "wkupclk", "refclk",
 343                                                       "div-clk", "phy-div", "sysclk";
 344                                         #phy-cells = <0>;
 345                                 };
 346
 347                                 pcie2_phy: pciephy@5000 {
 348                                         compatible = "ti,phy-pipe3-pcie";
 349                                         reg = <0x5000 0x80>, /* phy_rx */
 350                                               <0x5400 0x64>; /* phy_tx */
 351                                         reg-names = "phy_rx", "phy_tx";
 352                                         syscon-phy-power = <&scm_conf_pcie 0x20>;
 353                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 354                                         clocks = <&dpll_pcie_ref_ck>,
 355                                                  <&dpll_pcie_ref_m2ldo_ck>,
 356                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
 357                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
 358                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
 359                                                  <&optfclk_pciephy_div>,
 360                                                  <&sys_clkin1>;
 361                                         clock-names = "dpll_ref", "dpll_ref_m2",
 362                                                       "wkupclk", "refclk",
 363                                                       "div-clk", "phy-div", "sysclk";
 364                                         #phy-cells = <0>;
 365                                         status = "disabled";
 366                                 };
 367
 368                                 sata_phy: phy@6000 {
 369                                         compatible = "ti,phy-pipe3-sata";
 370                                         reg = <0x6000 0x80>, /* phy_rx */
 371                                               <0x6400 0x64>, /* phy_tx */
 372                                               <0x6800 0x40>; /* pll_ctrl */
 373                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 374                                         syscon-phy-power = <&scm_conf 0x374>;
 375                                         clocks = <&sys_clkin1>,
 376                                                  <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
 377                                         clock-names = "sysclk", "refclk";
 378                                         syscon-pllreset = <&scm_conf 0x3fc>;
 379                                         #phy-cells = <0>;
 380                                 };
 381                         };
 382                 };
 383
 384                 target-module@a0000 {                   /* 0x4a0a0000, ap 15 40.0 */
 385                         compatible = "ti,sysc";
 386                         status = "disabled";
 387                         #address-cells = <1>;
 388                         #size-cells = <1>;
 389                         ranges = <0x0 0xa0000 0x8000>;
 390                 };
 391
 392                 target-module@d9000 {                   /* 0x4a0d9000, ap 17 72.0 */
 393                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 394                         reg = <0xd9038 0x4>;
 395                         reg-names = "sysc";
 396                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 397                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 398                                         <SYSC_IDLE_NO>,
 399                                         <SYSC_IDLE_SMART>,
 400                                         <SYSC_IDLE_SMART_WKUP>;
 401                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 402                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
 403                         clock-names = "fck";
 404                         #address-cells = <1>;
 405                         #size-cells = <1>;
 406                         ranges = <0x0 0xd9000 0x1000>;
 407
 408                         /* SmartReflex child device marked reserved in TRM */
 409                 };
 410
 411                 target-module@dd000 {                   /* 0x4a0dd000, ap 19 18.0 */
 412                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 413                         reg = <0xdd038 0x4>;
 414                         reg-names = "sysc";
 415                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 416                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 417                                         <SYSC_IDLE_NO>,
 418                                         <SYSC_IDLE_SMART>,
 419                                         <SYSC_IDLE_SMART_WKUP>;
 420                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 421                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
 422                         clock-names = "fck";
 423                         #address-cells = <1>;
 424                         #size-cells = <1>;
 425                         ranges = <0x0 0xdd000 0x1000>;
 426
 427                         /* SmartReflex child device marked reserved in TRM */
 428                 };
 429
 430                 target-module@e0000 {                   /* 0x4a0e0000, ap 21 28.0 */
 431                         compatible = "ti,sysc";
 432                         status = "disabled";
 433                         #address-cells = <1>;
 434                         #size-cells = <1>;
 435                         ranges = <0x0 0xe0000 0x1000>;
 436                 };
 437
 438                 target-module@f4000 {                   /* 0x4a0f4000, ap 23 04.0 */
 439                         compatible = "ti,sysc-omap4", "ti,sysc";
 440                         reg = <0xf4000 0x4>,
 441                               <0xf4010 0x4>;
 442                         reg-names = "rev", "sysc";
 443                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 444                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 445                                         <SYSC_IDLE_NO>,
 446                                         <SYSC_IDLE_SMART>;
 447                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 448                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
 449                         clock-names = "fck";
 450                         #address-cells = <1>;
 451                         #size-cells = <1>;
 452                         ranges = <0x0 0xf4000 0x1000>;
 453
 454                         mailbox1: mailbox@0 {
 455                                 compatible = "ti,omap4-mailbox";
 456                                 reg = <0x0 0x200>;
 457                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 458                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 459                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 460                                 #mbox-cells = <1>;
 461                                 ti,mbox-num-users = <3>;
 462                                 ti,mbox-num-fifos = <8>;
 463                                 status = "disabled";
 464                         };
 465                 };
 466
 467                 target-module@f6000 {                   /* 0x4a0f6000, ap 25 78.0 */
 468                         compatible = "ti,sysc-omap2", "ti,sysc";
 469                         reg = <0xf6000 0x4>,
 470                               <0xf6010 0x4>,
 471                               <0xf6014 0x4>;
 472                         reg-names = "rev", "sysc", "syss";
 473                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 474                                          SYSC_OMAP2_SOFTRESET |
 475                                          SYSC_OMAP2_AUTOIDLE)>;
 476                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 477                                         <SYSC_IDLE_NO>,
 478                                         <SYSC_IDLE_SMART>;
 479                         ti,syss-mask = <1>;
 480                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 481                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
 482                         clock-names = "fck";
 483                         #address-cells = <1>;
 484                         #size-cells = <1>;
 485                         ranges = <0x0 0xf6000 0x1000>;
 486
 487                         hwspinlock: spinlock@0 {
 488                                 compatible = "ti,omap4-hwspinlock";
 489                                 reg = <0x0 0x1000>;
 490                                 #hwlock-cells = <1>;
 491                         };
 492                 };
 493         };
 494
 495         segment@100000 {                                        /* 0x4a100000 */
 496                 compatible = "simple-bus";
 497                 #address-cells = <1>;
 498                 #size-cells = <1>;
 499                 ranges = <0x00002000 0x00102000 0x001000>,      /* ap 27 */
 500                          <0x00003000 0x00103000 0x001000>,      /* ap 28 */
 501                          <0x00008000 0x00108000 0x001000>,      /* ap 29 */
 502                          <0x00009000 0x00109000 0x001000>,      /* ap 30 */
 503                          <0x00040000 0x00140000 0x010000>,      /* ap 31 */
 504                          <0x00050000 0x00150000 0x001000>,      /* ap 32 */
 505                          <0x00051000 0x00151000 0x001000>,      /* ap 33 */
 506                          <0x00052000 0x00152000 0x001000>,      /* ap 34 */
 507                          <0x00053000 0x00153000 0x001000>,      /* ap 35 */
 508                          <0x00054000 0x00154000 0x001000>,      /* ap 36 */
 509                          <0x00055000 0x00155000 0x001000>,      /* ap 37 */
 510                          <0x00056000 0x00156000 0x001000>,      /* ap 38 */
 511                          <0x00057000 0x00157000 0x001000>,      /* ap 39 */
 512                          <0x00058000 0x00158000 0x001000>,      /* ap 40 */
 513                          <0x0005b000 0x0015b000 0x001000>,      /* ap 41 */
 514                          <0x0005c000 0x0015c000 0x001000>,      /* ap 42 */
 515                          <0x0005d000 0x0015d000 0x001000>,      /* ap 45 */
 516                          <0x0005e000 0x0015e000 0x001000>,      /* ap 46 */
 517                          <0x0005f000 0x0015f000 0x001000>,      /* ap 47 */
 518                          <0x00060000 0x00160000 0x001000>,      /* ap 48 */
 519                          <0x00061000 0x00161000 0x001000>,      /* ap 49 */
 520                          <0x00062000 0x00162000 0x001000>,      /* ap 50 */
 521                          <0x00063000 0x00163000 0x001000>,      /* ap 51 */
 522                          <0x00064000 0x00164000 0x001000>,      /* ap 52 */
 523                          <0x00065000 0x00165000 0x001000>,      /* ap 53 */
 524                          <0x00066000 0x00166000 0x001000>,      /* ap 54 */
 525                          <0x00067000 0x00167000 0x001000>,      /* ap 55 */
 526                          <0x00068000 0x00168000 0x001000>,      /* ap 56 */
 527                          <0x0006d000 0x0016d000 0x001000>,      /* ap 57 */
 528                          <0x0006e000 0x0016e000 0x001000>,      /* ap 58 */
 529                          <0x00071000 0x00171000 0x001000>,      /* ap 61 */
 530                          <0x00072000 0x00172000 0x001000>,      /* ap 62 */
 531                          <0x00073000 0x00173000 0x001000>,      /* ap 63 */
 532                          <0x00074000 0x00174000 0x001000>,      /* ap 64 */
 533                          <0x00075000 0x00175000 0x001000>,      /* ap 65 */
 534                          <0x00076000 0x00176000 0x001000>,      /* ap 66 */
 535                          <0x00077000 0x00177000 0x001000>,      /* ap 67 */
 536                          <0x00078000 0x00178000 0x001000>,      /* ap 68 */
 537                          <0x00081000 0x00181000 0x001000>,      /* ap 69 */
 538                          <0x00082000 0x00182000 0x001000>,      /* ap 70 */
 539                          <0x00083000 0x00183000 0x001000>,      /* ap 71 */
 540                          <0x00084000 0x00184000 0x001000>,      /* ap 72 */
 541                          <0x00085000 0x00185000 0x001000>,      /* ap 73 */
 542                          <0x00086000 0x00186000 0x001000>,      /* ap 74 */
 543                          <0x00087000 0x00187000 0x001000>,      /* ap 75 */
 544                          <0x00088000 0x00188000 0x001000>,      /* ap 76 */
 545                          <0x00069000 0x00169000 0x001000>,      /* ap 103 */
 546                          <0x0006a000 0x0016a000 0x001000>,      /* ap 104 */
 547                          <0x00079000 0x00179000 0x001000>,      /* ap 105 */
 548                          <0x0007a000 0x0017a000 0x001000>,      /* ap 106 */
 549                          <0x0006b000 0x0016b000 0x001000>,      /* ap 107 */
 550                          <0x0006c000 0x0016c000 0x001000>,      /* ap 108 */
 551                          <0x0007b000 0x0017b000 0x001000>,      /* ap 121 */
 552                          <0x0007c000 0x0017c000 0x001000>,      /* ap 122 */
 553                          <0x0007d000 0x0017d000 0x001000>,      /* ap 123 */
 554                          <0x0007e000 0x0017e000 0x001000>,      /* ap 124 */
 555                          <0x00059000 0x00159000 0x001000>,      /* ap 125 */
 556                          <0x0005a000 0x0015a000 0x001000>;      /* ap 126 */
 557
 558                 target-module@2000 {                    /* 0x4a102000, ap 27 3c.0 */
 559                         compatible = "ti,sysc";
 560                         status = "disabled";
 561                         #address-cells = <1>;
 562                         #size-cells = <1>;
 563                         ranges = <0x0 0x2000 0x1000>;
 564                 };
 565
 566                 target-module@8000 {                    /* 0x4a108000, ap 29 1e.0 */
 567                         compatible = "ti,sysc";
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <1>;
 571                         ranges = <0x0 0x8000 0x1000>;
 572                 };
 573
 574                 target-module@40000 {                   /* 0x4a140000, ap 31 06.0 */
 575                         compatible = "ti,sysc";
 576                         status = "disabled";
 577                         #address-cells = <1>;
 578                         #size-cells = <1>;
 579                         ranges = <0x0 0x40000 0x10000>;
 580                 };
 581
 582                 target-module@51000 {                   /* 0x4a151000, ap 33 50.0 */
 583                         compatible = "ti,sysc";
 584                         status = "disabled";
 585                         #address-cells = <1>;
 586                         #size-cells = <1>;
 587                         ranges = <0x0 0x51000 0x1000>;
 588                 };
 589
 590                 target-module@53000 {                   /* 0x4a153000, ap 35 54.0 */
 591                         compatible = "ti,sysc";
 592                         status = "disabled";
 593                         #address-cells = <1>;
 594                         #size-cells = <1>;
 595                         ranges = <0x0 0x53000 0x1000>;
 596                 };
 597
 598                 target-module@55000 {                   /* 0x4a155000, ap 37 46.0 */
 599                         compatible = "ti,sysc";
 600                         status = "disabled";
 601                         #address-cells = <1>;
 602                         #size-cells = <1>;
 603                         ranges = <0x0 0x55000 0x1000>;
 604                 };
 605
 606                 target-module@57000 {                   /* 0x4a157000, ap 39 58.0 */
 607                         compatible = "ti,sysc";
 608                         status = "disabled";
 609                         #address-cells = <1>;
 610                         #size-cells = <1>;
 611                         ranges = <0x0 0x57000 0x1000>;
 612                 };
 613
 614                 target-module@59000 {                   /* 0x4a159000, ap 125 6a.0 */
 615                         compatible = "ti,sysc";
 616                         status = "disabled";
 617                         #address-cells = <1>;
 618                         #size-cells = <1>;
 619                         ranges = <0x0 0x59000 0x1000>;
 620                 };
 621
 622                 target-module@5b000 {                   /* 0x4a15b000, ap 41 60.0 */
 623                         compatible = "ti,sysc";
 624                         status = "disabled";
 625                         #address-cells = <1>;
 626                         #size-cells = <1>;
 627                         ranges = <0x0 0x5b000 0x1000>;
 628                 };
 629
 630                 target-module@5d000 {                   /* 0x4a15d000, ap 45 3a.0 */
 631                         compatible = "ti,sysc";
 632                         status = "disabled";
 633                         #address-cells = <1>;
 634                         #size-cells = <1>;
 635                         ranges = <0x0 0x5d000 0x1000>;
 636                 };
 637
 638                 target-module@5f000 {                   /* 0x4a15f000, ap 47 56.0 */
 639                         compatible = "ti,sysc";
 640                         status = "disabled";
 641                         #address-cells = <1>;
 642                         #size-cells = <1>;
 643                         ranges = <0x0 0x5f000 0x1000>;
 644                 };
 645
 646                 target-module@61000 {                   /* 0x4a161000, ap 49 32.0 */
 647                         compatible = "ti,sysc";
 648                         status = "disabled";
 649                         #address-cells = <1>;
 650                         #size-cells = <1>;
 651                         ranges = <0x0 0x61000 0x1000>;
 652                 };
 653
 654                 target-module@63000 {                   /* 0x4a163000, ap 51 5c.0 */
 655                         compatible = "ti,sysc";
 656                         status = "disabled";
 657                         #address-cells = <1>;
 658                         #size-cells = <1>;
 659                         ranges = <0x0 0x63000 0x1000>;
 660                 };
 661
 662                 target-module@65000 {                   /* 0x4a165000, ap 53 4e.0 */
 663                         compatible = "ti,sysc";
 664                         status = "disabled";
 665                         #address-cells = <1>;
 666                         #size-cells = <1>;
 667                         ranges = <0x0 0x65000 0x1000>;
 668                 };
 669
 670                 target-module@67000 {                   /* 0x4a167000, ap 55 5e.0 */
 671                         compatible = "ti,sysc";
 672                         status = "disabled";
 673                         #address-cells = <1>;
 674                         #size-cells = <1>;
 675                         ranges = <0x0 0x67000 0x1000>;
 676                 };
 677
 678                 target-module@69000 {                   /* 0x4a169000, ap 103 4a.0 */
 679                         compatible = "ti,sysc";
 680                         status = "disabled";
 681                         #address-cells = <1>;
 682                         #size-cells = <1>;
 683                         ranges = <0x0 0x69000 0x1000>;
 684                 };
 685
 686                 target-module@6b000 {                   /* 0x4a16b000, ap 107 52.0 */
 687                         compatible = "ti,sysc";
 688                         status = "disabled";
 689                         #address-cells = <1>;
 690                         #size-cells = <1>;
 691                         ranges = <0x0 0x6b000 0x1000>;
 692                 };
 693
 694                 target-module@6d000 {                   /* 0x4a16d000, ap 57 68.0 */
 695                         compatible = "ti,sysc";
 696                         status = "disabled";
 697                         #address-cells = <1>;
 698                         #size-cells = <1>;
 699                         ranges = <0x0 0x6d000 0x1000>;
 700                 };
 701
 702                 target-module@71000 {                   /* 0x4a171000, ap 61 48.0 */
 703                         compatible = "ti,sysc";
 704                         status = "disabled";
 705                         #address-cells = <1>;
 706                         #size-cells = <1>;
 707                         ranges = <0x0 0x71000 0x1000>;
 708                 };
 709
 710                 target-module@73000 {                   /* 0x4a173000, ap 63 2a.0 */
 711                         compatible = "ti,sysc";
 712                         status = "disabled";
 713                         #address-cells = <1>;
 714                         #size-cells = <1>;
 715                         ranges = <0x0 0x73000 0x1000>;
 716                 };
 717
 718                 target-module@75000 {                   /* 0x4a175000, ap 65 64.0 */
 719                         compatible = "ti,sysc";
 720                         status = "disabled";
 721                         #address-cells = <1>;
 722                         #size-cells = <1>;
 723                         ranges = <0x0 0x75000 0x1000>;
 724                 };
 725
 726                 target-module@77000 {                   /* 0x4a177000, ap 67 66.0 */
 727                         compatible = "ti,sysc";
 728                         status = "disabled";
 729                         #address-cells = <1>;
 730                         #size-cells = <1>;
 731                         ranges = <0x0 0x77000 0x1000>;
 732                 };
 733
 734                 target-module@79000 {                   /* 0x4a179000, ap 105 34.0 */
 735                         compatible = "ti,sysc";
 736                         status = "disabled";
 737                         #address-cells = <1>;
 738                         #size-cells = <1>;
 739                         ranges = <0x0 0x79000 0x1000>;
 740                 };
 741
 742                 target-module@7b000 {                   /* 0x4a17b000, ap 121 7c.0 */
 743                         compatible = "ti,sysc";
 744                         status = "disabled";
 745                         #address-cells = <1>;
 746                         #size-cells = <1>;
 747                         ranges = <0x0 0x7b000 0x1000>;
 748                 };
 749
 750                 target-module@7d000 {                   /* 0x4a17d000, ap 123 7e.0 */
 751                         compatible = "ti,sysc";
 752                         status = "disabled";
 753                         #address-cells = <1>;
 754                         #size-cells = <1>;
 755                         ranges = <0x0 0x7d000 0x1000>;
 756                 };
 757
 758                 target-module@81000 {                   /* 0x4a181000, ap 69 26.0 */
 759                         compatible = "ti,sysc";
 760                         status = "disabled";
 761                         #address-cells = <1>;
 762                         #size-cells = <1>;
 763                         ranges = <0x0 0x81000 0x1000>;
 764                 };
 765
 766                 target-module@83000 {                   /* 0x4a183000, ap 71 2e.0 */
 767                         compatible = "ti,sysc";
 768                         status = "disabled";
 769                         #address-cells = <1>;
 770                         #size-cells = <1>;
 771                         ranges = <0x0 0x83000 0x1000>;
 772                 };
 773
 774                 target-module@85000 {                   /* 0x4a185000, ap 73 36.0 */
 775                         compatible = "ti,sysc";
 776                         status = "disabled";
 777                         #address-cells = <1>;
 778                         #size-cells = <1>;
 779                         ranges = <0x0 0x85000 0x1000>;
 780                 };
 781
 782                 target-module@87000 {                   /* 0x4a187000, ap 75 74.0 */
 783                         compatible = "ti,sysc";
 784                         status = "disabled";
 785                         #address-cells = <1>;
 786                         #size-cells = <1>;
 787                         ranges = <0x0 0x87000 0x1000>;
 788                 };
 789         };
 790
 791         segment@200000 {                                        /* 0x4a200000 */
 792                 compatible = "simple-bus";
 793                 #address-cells = <1>;
 794                 #size-cells = <1>;
 795                 ranges = <0x00018000 0x00218000 0x001000>,      /* ap 43 */
 796                          <0x00019000 0x00219000 0x001000>,      /* ap 44 */
 797                          <0x00000000 0x00200000 0x001000>,      /* ap 77 */
 798                          <0x00001000 0x00201000 0x001000>,      /* ap 78 */
 799                          <0x0000a000 0x0020a000 0x001000>,      /* ap 79 */
 800                          <0x0000b000 0x0020b000 0x001000>,      /* ap 80 */
 801                          <0x0000c000 0x0020c000 0x001000>,      /* ap 81 */
 802                          <0x0000d000 0x0020d000 0x001000>,      /* ap 82 */
 803                          <0x0000e000 0x0020e000 0x001000>,      /* ap 83 */
 804                          <0x0000f000 0x0020f000 0x001000>,      /* ap 84 */
 805                          <0x00010000 0x00210000 0x001000>,      /* ap 85 */
 806                          <0x00011000 0x00211000 0x001000>,      /* ap 86 */
 807                          <0x00012000 0x00212000 0x001000>,      /* ap 87 */
 808                          <0x00013000 0x00213000 0x001000>,      /* ap 88 */
 809                          <0x00014000 0x00214000 0x001000>,      /* ap 89 */
 810                          <0x00015000 0x00215000 0x001000>,      /* ap 90 */
 811                          <0x0002a000 0x0022a000 0x001000>,      /* ap 91 */
 812                          <0x0002b000 0x0022b000 0x001000>,      /* ap 92 */
 813                          <0x0001c000 0x0021c000 0x001000>,      /* ap 93 */
 814                          <0x0001d000 0x0021d000 0x001000>,      /* ap 94 */
 815                          <0x0001e000 0x0021e000 0x001000>,      /* ap 95 */
 816                          <0x0001f000 0x0021f000 0x001000>,      /* ap 96 */
 817                          <0x00020000 0x00220000 0x001000>,      /* ap 97 */
 818                          <0x00021000 0x00221000 0x001000>,      /* ap 98 */
 819                          <0x00024000 0x00224000 0x001000>,      /* ap 99 */
 820                          <0x00025000 0x00225000 0x001000>,      /* ap 100 */
 821                          <0x00026000 0x00226000 0x001000>,      /* ap 101 */
 822                          <0x00027000 0x00227000 0x001000>,      /* ap 102 */
 823                          <0x0002c000 0x0022c000 0x001000>,      /* ap 109 */
 824                          <0x0002d000 0x0022d000 0x001000>,      /* ap 110 */
 825                          <0x0002e000 0x0022e000 0x001000>,      /* ap 111 */
 826                          <0x0002f000 0x0022f000 0x001000>,      /* ap 112 */
 827                          <0x00030000 0x00230000 0x001000>,      /* ap 113 */
 828                          <0x00031000 0x00231000 0x001000>,      /* ap 114 */
 829                          <0x00032000 0x00232000 0x001000>,      /* ap 115 */
 830                          <0x00033000 0x00233000 0x001000>,      /* ap 116 */
 831                          <0x00034000 0x00234000 0x001000>,      /* ap 117 */
 832                          <0x00035000 0x00235000 0x001000>,      /* ap 118 */
 833                          <0x00036000 0x00236000 0x001000>,      /* ap 119 */
 834                          <0x00037000 0x00237000 0x001000>,      /* ap 120 */
 835                          <0x0001a000 0x0021a000 0x001000>,      /* ap 127 */
 836                          <0x0001b000 0x0021b000 0x001000>;      /* ap 128 */
 837
 838                 target-module@0 {                       /* 0x4a200000, ap 77 3e.0 */
 839                         compatible = "ti,sysc";
 840                         status = "disabled";
 841                         #address-cells = <1>;
 842                         #size-cells = <1>;
 843                         ranges = <0x0 0x0 0x1000>;
 844                 };
 845
 846                 target-module@a000 {                    /* 0x4a20a000, ap 79 30.0 */
 847                         compatible = "ti,sysc";
 848                         status = "disabled";
 849                         #address-cells = <1>;
 850                         #size-cells = <1>;
 851                         ranges = <0x0 0xa000 0x1000>;
 852                 };
 853
 854                 target-module@c000 {                    /* 0x4a20c000, ap 81 0c.0 */
 855                         compatible = "ti,sysc";
 856                         status = "disabled";
 857                         #address-cells = <1>;
 858                         #size-cells = <1>;
 859                         ranges = <0x0 0xc000 0x1000>;
 860                 };
 861
 862                 target-module@e000 {                    /* 0x4a20e000, ap 83 22.0 */
 863                         compatible = "ti,sysc";
 864                         status = "disabled";
 865                         #address-cells = <1>;
 866                         #size-cells = <1>;
 867                         ranges = <0x0 0xe000 0x1000>;
 868                 };
 869
 870                 target-module@10000 {                   /* 0x4a210000, ap 85 14.0 */
 871                         compatible = "ti,sysc";
 872                         status = "disabled";
 873                         #address-cells = <1>;
 874                         #size-cells = <1>;
 875                         ranges = <0x0 0x10000 0x1000>;
 876                 };
 877
 878                 target-module@12000 {                   /* 0x4a212000, ap 87 16.0 */
 879                         compatible = "ti,sysc";
 880                         status = "disabled";
 881                         #address-cells = <1>;
 882                         #size-cells = <1>;
 883                         ranges = <0x0 0x12000 0x1000>;
 884                 };
 885
 886                 target-module@14000 {                   /* 0x4a214000, ap 89 1c.0 */
 887                         compatible = "ti,sysc";
 888                         status = "disabled";
 889                         #address-cells = <1>;
 890                         #size-cells = <1>;
 891                         ranges = <0x0 0x14000 0x1000>;
 892                 };
 893
 894                 target-module@18000 {                   /* 0x4a218000, ap 43 12.0 */
 895                         compatible = "ti,sysc";
 896                         status = "disabled";
 897                         #address-cells = <1>;
 898                         #size-cells = <1>;
 899                         ranges = <0x0 0x18000 0x1000>;
 900                 };
 901
 902                 target-module@1a000 {                   /* 0x4a21a000, ap 127 7a.0 */
 903                         compatible = "ti,sysc";
 904                         status = "disabled";
 905                         #address-cells = <1>;
 906                         #size-cells = <1>;
 907                         ranges = <0x0 0x1a000 0x1000>;
 908                 };
 909
 910                 target-module@1c000 {                   /* 0x4a21c000, ap 93 38.0 */
 911                         compatible = "ti,sysc";
 912                         status = "disabled";
 913                         #address-cells = <1>;
 914                         #size-cells = <1>;
 915                         ranges = <0x0 0x1c000 0x1000>;
 916                 };
 917
 918                 target-module@1e000 {                   /* 0x4a21e000, ap 95 0a.0 */
 919                         compatible = "ti,sysc";
 920                         status = "disabled";
 921                         #address-cells = <1>;
 922                         #size-cells = <1>;
 923                         ranges = <0x0 0x1e000 0x1000>;
 924                 };
 925
 926                 target-module@20000 {                   /* 0x4a220000, ap 97 24.0 */
 927                         compatible = "ti,sysc";
 928                         status = "disabled";
 929                         #address-cells = <1>;
 930                         #size-cells = <1>;
 931                         ranges = <0x0 0x20000 0x1000>;
 932                 };
 933
 934                 target-module@24000 {                   /* 0x4a224000, ap 99 44.0 */
 935                         compatible = "ti,sysc";
 936                         status = "disabled";
 937                         #address-cells = <1>;
 938                         #size-cells = <1>;
 939                         ranges = <0x0 0x24000 0x1000>;
 940                 };
 941
 942                 target-module@26000 {                   /* 0x4a226000, ap 101 2c.0 */
 943                         compatible = "ti,sysc";
 944                         status = "disabled";
 945                         #address-cells = <1>;
 946                         #size-cells = <1>;
 947                         ranges = <0x0 0x26000 0x1000>;
 948                 };
 949
 950                 target-module@2a000 {                   /* 0x4a22a000, ap 91 4c.0 */
 951                         compatible = "ti,sysc";
 952                         status = "disabled";
 953                         #address-cells = <1>;
 954                         #size-cells = <1>;
 955                         ranges = <0x0 0x2a000 0x1000>;
 956                 };
 957
 958                 target-module@2c000 {                   /* 0x4a22c000, ap 109 6c.0 */
 959                         compatible = "ti,sysc";
 960                         status = "disabled";
 961                         #address-cells = <1>;
 962                         #size-cells = <1>;
 963                         ranges = <0x0 0x2c000 0x1000>;
 964                 };
 965
 966                 target-module@2e000 {                   /* 0x4a22e000, ap 111 6e.0 */
 967                         compatible = "ti,sysc";
 968                         status = "disabled";
 969                         #address-cells = <1>;
 970                         #size-cells = <1>;
 971                         ranges = <0x0 0x2e000 0x1000>;
 972                 };
 973
 974                 target-module@30000 {                   /* 0x4a230000, ap 113 70.0 */
 975                         compatible = "ti,sysc";
 976                         status = "disabled";
 977                         #address-cells = <1>;
 978                         #size-cells = <1>;
 979                         ranges = <0x0 0x30000 0x1000>;
 980                 };
 981
 982                 target-module@32000 {                   /* 0x4a232000, ap 115 5a.0 */
 983                         compatible = "ti,sysc";
 984                         status = "disabled";
 985                         #address-cells = <1>;
 986                         #size-cells = <1>;
 987                         ranges = <0x0 0x32000 0x1000>;
 988                 };
 989
 990                 target-module@34000 {                   /* 0x4a234000, ap 117 76.1 */
 991                         compatible = "ti,sysc";
 992                         status = "disabled";
 993                         #address-cells = <1>;
 994                         #size-cells = <1>;
 995                         ranges = <0x0 0x34000 0x1000>;
 996                 };
 997
 998                 target-module@36000 {                   /* 0x4a236000, ap 119 62.0 */
 999                         compatible = "ti,sysc";
1000                         status = "disabled";
1001                         #address-cells = <1>;
1002                         #size-cells = <1>;
1003                         ranges = <0x0 0x36000 0x1000>;
1004                 };
1005         };
1006 };
1007
1008 &l4_per1 {                                              /* 0x48000000 */
1009         compatible = "ti,dra7-l4-per1", "simple-bus";
1010         reg = <0x48000000 0x800>,
1011               <0x48000800 0x800>,
1012               <0x48001000 0x400>,
1013               <0x48001400 0x400>,
1014               <0x48001800 0x400>,
1015               <0x48001c00 0x400>;
1016         reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1017         #address-cells = <1>;
1018         #size-cells = <1>;
1019         ranges = <0x00000000 0x48000000 0x200000>,      /* segment 0 */
1020                  <0x00200000 0x48200000 0x200000>;      /* segment 1 */
1021
1022         segment@0 {                                     /* 0x48000000 */
1023                 compatible = "simple-bus";
1024                 #address-cells = <1>;
1025                 #size-cells = <1>;
1026                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
1027                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
1028                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
1029                          <0x00020000 0x00020000 0x001000>,      /* ap 3 */
1030                          <0x00021000 0x00021000 0x001000>,      /* ap 4 */
1031                          <0x00032000 0x00032000 0x001000>,      /* ap 5 */
1032                          <0x00033000 0x00033000 0x001000>,      /* ap 6 */
1033                          <0x00034000 0x00034000 0x001000>,      /* ap 7 */
1034                          <0x00035000 0x00035000 0x001000>,      /* ap 8 */
1035                          <0x00036000 0x00036000 0x001000>,      /* ap 9 */
1036                          <0x00037000 0x00037000 0x001000>,      /* ap 10 */
1037                          <0x0003e000 0x0003e000 0x001000>,      /* ap 11 */
1038                          <0x0003f000 0x0003f000 0x001000>,      /* ap 12 */
1039                          <0x00055000 0x00055000 0x001000>,      /* ap 13 */
1040                          <0x00056000 0x00056000 0x001000>,      /* ap 14 */
1041                          <0x00057000 0x00057000 0x001000>,      /* ap 15 */
1042                          <0x00058000 0x00058000 0x001000>,      /* ap 16 */
1043                          <0x00059000 0x00059000 0x001000>,      /* ap 17 */
1044                          <0x0005a000 0x0005a000 0x001000>,      /* ap 18 */
1045                          <0x0005b000 0x0005b000 0x001000>,      /* ap 19 */
1046                          <0x0005c000 0x0005c000 0x001000>,      /* ap 20 */
1047                          <0x0005d000 0x0005d000 0x001000>,      /* ap 21 */
1048                          <0x0005e000 0x0005e000 0x001000>,      /* ap 22 */
1049                          <0x00060000 0x00060000 0x001000>,      /* ap 23 */
1050                          <0x0006a000 0x0006a000 0x001000>,      /* ap 24 */
1051                          <0x0006b000 0x0006b000 0x001000>,      /* ap 25 */
1052                          <0x0006c000 0x0006c000 0x001000>,      /* ap 26 */
1053                          <0x0006d000 0x0006d000 0x001000>,      /* ap 27 */
1054                          <0x0006e000 0x0006e000 0x001000>,      /* ap 28 */
1055                          <0x0006f000 0x0006f000 0x001000>,      /* ap 29 */
1056                          <0x00070000 0x00070000 0x001000>,      /* ap 30 */
1057                          <0x00071000 0x00071000 0x001000>,      /* ap 31 */
1058                          <0x00072000 0x00072000 0x001000>,      /* ap 32 */
1059                          <0x00073000 0x00073000 0x001000>,      /* ap 33 */
1060                          <0x00061000 0x00061000 0x001000>,      /* ap 34 */
1061                          <0x00053000 0x00053000 0x001000>,      /* ap 35 */
1062                          <0x00054000 0x00054000 0x001000>,      /* ap 36 */
1063                          <0x000b2000 0x000b2000 0x001000>,      /* ap 37 */
1064                          <0x000b3000 0x000b3000 0x001000>,      /* ap 38 */
1065                          <0x00078000 0x00078000 0x001000>,      /* ap 39 */
1066                          <0x00079000 0x00079000 0x001000>,      /* ap 40 */
1067                          <0x00086000 0x00086000 0x001000>,      /* ap 41 */
1068                          <0x00087000 0x00087000 0x001000>,      /* ap 42 */
1069                          <0x00088000 0x00088000 0x001000>,      /* ap 43 */
1070                          <0x00089000 0x00089000 0x001000>,      /* ap 44 */
1071                          <0x00051000 0x00051000 0x001000>,      /* ap 45 */
1072                          <0x00052000 0x00052000 0x001000>,      /* ap 46 */
1073                          <0x00098000 0x00098000 0x001000>,      /* ap 47 */
1074                          <0x00099000 0x00099000 0x001000>,      /* ap 48 */
1075                          <0x0009a000 0x0009a000 0x001000>,      /* ap 49 */
1076                          <0x0009b000 0x0009b000 0x001000>,      /* ap 50 */
1077                          <0x0009c000 0x0009c000 0x001000>,      /* ap 51 */
1078                          <0x0009d000 0x0009d000 0x001000>,      /* ap 52 */
1079                          <0x00068000 0x00068000 0x001000>,      /* ap 53 */
1080                          <0x00069000 0x00069000 0x001000>,      /* ap 54 */
1081                          <0x00090000 0x00090000 0x002000>,      /* ap 55 */
1082                          <0x00092000 0x00092000 0x001000>,      /* ap 56 */
1083                          <0x000a4000 0x000a4000 0x001000>,      /* ap 57 */
1084                          <0x000a6000 0x000a6000 0x001000>,      /* ap 58 */
1085                          <0x000a8000 0x000a8000 0x004000>,      /* ap 59 */
1086                          <0x000ac000 0x000ac000 0x001000>,      /* ap 60 */
1087                          <0x000ad000 0x000ad000 0x001000>,      /* ap 61 */
1088                          <0x000ae000 0x000ae000 0x001000>,      /* ap 62 */
1089                          <0x00066000 0x00066000 0x001000>,      /* ap 63 */
1090                          <0x00067000 0x00067000 0x001000>,      /* ap 64 */
1091                          <0x000b4000 0x000b4000 0x001000>,      /* ap 65 */
1092                          <0x000b5000 0x000b5000 0x001000>,      /* ap 66 */
1093                          <0x000b8000 0x000b8000 0x001000>,      /* ap 67 */
1094                          <0x000b9000 0x000b9000 0x001000>,      /* ap 68 */
1095                          <0x000ba000 0x000ba000 0x001000>,      /* ap 69 */
1096                          <0x000bb000 0x000bb000 0x001000>,      /* ap 70 */
1097                          <0x000d1000 0x000d1000 0x001000>,      /* ap 71 */
1098                          <0x000d2000 0x000d2000 0x001000>,      /* ap 72 */
1099                          <0x000d5000 0x000d5000 0x001000>,      /* ap 73 */
1100                          <0x000d6000 0x000d6000 0x001000>,      /* ap 74 */
1101                          <0x000a2000 0x000a2000 0x001000>,      /* ap 75 */
1102                          <0x000a3000 0x000a3000 0x001000>,      /* ap 76 */
1103                          <0x00001400 0x00001400 0x000400>,      /* ap 77 */
1104                          <0x00001800 0x00001800 0x000400>,      /* ap 78 */
1105                          <0x00001c00 0x00001c00 0x000400>,      /* ap 79 */
1106                          <0x000a5000 0x000a5000 0x001000>,      /* ap 80 */
1107                          <0x0007a000 0x0007a000 0x001000>,      /* ap 81 */
1108                          <0x0007b000 0x0007b000 0x001000>,      /* ap 82 */
1109                          <0x0007c000 0x0007c000 0x001000>,      /* ap 83 */
1110                          <0x0007d000 0x0007d000 0x001000>;      /* ap 84 */
1111
1112                 target-module@20000 {                   /* 0x48020000, ap 3 04.0 */
1113                         compatible = "ti,sysc-omap2", "ti,sysc";
1114                         reg = <0x20050 0x4>,
1115                               <0x20054 0x4>,
1116                               <0x20058 0x4>;
1117                         reg-names = "rev", "sysc", "syss";
1118                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1119                                          SYSC_OMAP2_SOFTRESET |
1120                                          SYSC_OMAP2_AUTOIDLE)>;
1121                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1122                                         <SYSC_IDLE_NO>,
1123                                         <SYSC_IDLE_SMART>,
1124                                         <SYSC_IDLE_SMART_WKUP>;
1125                         ti,syss-mask = <1>;
1126                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1127                         clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1128                         clock-names = "fck";
1129                         #address-cells = <1>;
1130                         #size-cells = <1>;
1131                         ranges = <0x0 0x20000 0x1000>;
1132
1133                         uart3: serial@0 {
1134                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1135                                 reg = <0x0 0x100>;
1136                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1137                                 clock-frequency = <48000000>;
1138                                 status = "disabled";
1139                                 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1140                                 dma-names = "tx", "rx";
1141                         };
1142                 };
1143
1144                 target-module@32000 {                   /* 0x48032000, ap 5 3e.0 */
1145                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1146                         reg = <0x32000 0x4>,
1147                               <0x32010 0x4>;
1148                         reg-names = "rev", "sysc";
1149                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1150                                          SYSC_OMAP4_SOFTRESET)>;
1151                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1152                                         <SYSC_IDLE_NO>,
1153                                         <SYSC_IDLE_SMART>,
1154                                         <SYSC_IDLE_SMART_WKUP>;
1155                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1156                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1157                         clock-names = "fck";
1158                         #address-cells = <1>;
1159                         #size-cells = <1>;
1160                         ranges = <0x0 0x32000 0x1000>;
1161
1162                         timer2: timer@0 {
1163                                 compatible = "ti,omap5430-timer";
1164                                 reg = <0x0 0x80>;
1165                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
1166                                 clock-names = "fck", "timer_sys_ck";
1167                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1168                         };
1169                 };
1170
1171                 target-module@34000 {                   /* 0x48034000, ap 7 46.0 */
1172                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1173                         reg = <0x34000 0x4>,
1174                               <0x34010 0x4>;
1175                         reg-names = "rev", "sysc";
1176                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1177                                          SYSC_OMAP4_SOFTRESET)>;
1178                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1179                                         <SYSC_IDLE_NO>,
1180                                         <SYSC_IDLE_SMART>,
1181                                         <SYSC_IDLE_SMART_WKUP>;
1182                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1183                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1184                         clock-names = "fck";
1185                         #address-cells = <1>;
1186                         #size-cells = <1>;
1187                         ranges = <0x0 0x34000 0x1000>;
1188
1189                         timer3: timer@0 {
1190                                 compatible = "ti,omap5430-timer";
1191                                 reg = <0x0 0x80>;
1192                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
1193                                 clock-names = "fck", "timer_sys_ck";
1194                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1195                         };
1196                 };
1197
1198                 target-module@36000 {                   /* 0x48036000, ap 9 4e.0 */
1199                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1200                         reg = <0x36000 0x4>,
1201                               <0x36010 0x4>;
1202                         reg-names = "rev", "sysc";
1203                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1204                                          SYSC_OMAP4_SOFTRESET)>;
1205                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1206                                         <SYSC_IDLE_NO>,
1207                                         <SYSC_IDLE_SMART>,
1208                                         <SYSC_IDLE_SMART_WKUP>;
1209                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1210                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>,
1211                                  <&timer_sys_clk_div>;
1212                         clock-names = "fck", "timer_sys_ck";
1213                         #address-cells = <1>;
1214                         #size-cells = <1>;
1215                         ranges = <0x0 0x36000 0x1000>;
1216
1217                         timer4: timer@0 {
1218                                 compatible = "ti,omap5430-timer";
1219                                 reg = <0x0 0x80>;
1220                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
1221                                 clock-names = "fck", "timer_sys_ck";
1222                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1223                         };
1224                 };
1225
1226                 target-module@3e000 {                   /* 0x4803e000, ap 11 56.0 */
1227                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1228                         reg = <0x3e000 0x4>,
1229                               <0x3e010 0x4>;
1230                         reg-names = "rev", "sysc";
1231                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1232                                          SYSC_OMAP4_SOFTRESET)>;
1233                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1234                                         <SYSC_IDLE_NO>,
1235                                         <SYSC_IDLE_SMART>,
1236                                         <SYSC_IDLE_SMART_WKUP>;
1237                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1238                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1239                         clock-names = "fck";
1240                         #address-cells = <1>;
1241                         #size-cells = <1>;
1242                         ranges = <0x0 0x3e000 0x1000>;
1243
1244                         timer9: timer@0 {
1245                                 compatible = "ti,omap5430-timer";
1246                                 reg = <0x0 0x80>;
1247                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
1248                                 clock-names = "fck", "timer_sys_ck";
1249                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1250                         };
1251                 };
1252
1253                 gpio7_target: target-module@51000 {             /* 0x48051000, ap 45 2e.0 */
1254                         compatible = "ti,sysc-omap2", "ti,sysc";
1255                         reg = <0x51000 0x4>,
1256                               <0x51010 0x4>,
1257                               <0x51114 0x4>;
1258                         reg-names = "rev", "sysc", "syss";
1259                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1260                                          SYSC_OMAP2_SOFTRESET |
1261                                          SYSC_OMAP2_AUTOIDLE)>;
1262                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1263                                         <SYSC_IDLE_NO>,
1264                                         <SYSC_IDLE_SMART>,
1265                                         <SYSC_IDLE_SMART_WKUP>;
1266                         ti,syss-mask = <1>;
1267                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1268                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1269                                  <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1270                         clock-names = "fck", "dbclk";
1271                         #address-cells = <1>;
1272                         #size-cells = <1>;
1273                         ranges = <0x0 0x51000 0x1000>;
1274
1275                         gpio7: gpio@0 {
1276                                 compatible = "ti,omap4-gpio";
1277                                 reg = <0x0 0x200>;
1278                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1279                                 gpio-controller;
1280                                 #gpio-cells = <2>;
1281                                 interrupt-controller;
1282                                 #interrupt-cells = <2>;
1283                         };
1284                 };
1285
1286                 target-module@53000 {                   /* 0x48053000, ap 35 36.0 */
1287                         compatible = "ti,sysc-omap2", "ti,sysc";
1288                         reg = <0x53000 0x4>,
1289                               <0x53010 0x4>,
1290                               <0x53114 0x4>;
1291                         reg-names = "rev", "sysc", "syss";
1292                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1293                                          SYSC_OMAP2_SOFTRESET |
1294                                          SYSC_OMAP2_AUTOIDLE)>;
1295                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1296                                         <SYSC_IDLE_NO>,
1297                                         <SYSC_IDLE_SMART>,
1298                                         <SYSC_IDLE_SMART_WKUP>;
1299                         ti,syss-mask = <1>;
1300                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1301                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1302                                  <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1303                         clock-names = "fck", "dbclk";
1304                         #address-cells = <1>;
1305                         #size-cells = <1>;
1306                         ranges = <0x0 0x53000 0x1000>;
1307
1308                         gpio8: gpio@0 {
1309                                 compatible = "ti,omap4-gpio";
1310                                 reg = <0x0 0x200>;
1311                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1312                                 gpio-controller;
1313                                 #gpio-cells = <2>;
1314                                 interrupt-controller;
1315                                 #interrupt-cells = <2>;
1316                         };
1317                 };
1318
1319                 target-module@55000 {                   /* 0x48055000, ap 13 0e.0 */
1320                         compatible = "ti,sysc-omap2", "ti,sysc";
1321                         reg = <0x55000 0x4>,
1322                               <0x55010 0x4>,
1323                               <0x55114 0x4>;
1324                         reg-names = "rev", "sysc", "syss";
1325                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1326                                          SYSC_OMAP2_SOFTRESET |
1327                                          SYSC_OMAP2_AUTOIDLE)>;
1328                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1329                                         <SYSC_IDLE_NO>,
1330                                         <SYSC_IDLE_SMART>,
1331                                         <SYSC_IDLE_SMART_WKUP>;
1332                         ti,syss-mask = <1>;
1333                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1334                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1335                                  <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1336                         clock-names = "fck", "dbclk";
1337                         #address-cells = <1>;
1338                         #size-cells = <1>;
1339                         ranges = <0x0 0x55000 0x1000>;
1340
1341                         gpio2: gpio@0 {
1342                                 compatible = "ti,omap4-gpio";
1343                                 reg = <0x0 0x200>;
1344                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1345                                 gpio-controller;
1346                                 #gpio-cells = <2>;
1347                                 interrupt-controller;
1348                                 #interrupt-cells = <2>;
1349                         };
1350                 };
1351
1352                 target-module@57000 {                   /* 0x48057000, ap 15 06.0 */
1353                         compatible = "ti,sysc-omap2", "ti,sysc";
1354                         reg = <0x57000 0x4>,
1355                               <0x57010 0x4>,
1356                               <0x57114 0x4>;
1357                         reg-names = "rev", "sysc", "syss";
1358                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1359                                          SYSC_OMAP2_SOFTRESET |
1360                                          SYSC_OMAP2_AUTOIDLE)>;
1361                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1362                                         <SYSC_IDLE_NO>,
1363                                         <SYSC_IDLE_SMART>,
1364                                         <SYSC_IDLE_SMART_WKUP>;
1365                         ti,syss-mask = <1>;
1366                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1367                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1368                                  <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1369                         clock-names = "fck", "dbclk";
1370                         #address-cells = <1>;
1371                         #size-cells = <1>;
1372                         ranges = <0x0 0x57000 0x1000>;
1373
1374                         gpio3: gpio@0 {
1375                                 compatible = "ti,omap4-gpio";
1376                                 reg = <0x0 0x200>;
1377                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1378                                 gpio-controller;
1379                                 #gpio-cells = <2>;
1380                                 interrupt-controller;
1381                                 #interrupt-cells = <2>;
1382                         };
1383                 };
1384
1385                 target-module@59000 {                   /* 0x48059000, ap 17 16.0 */
1386                         compatible = "ti,sysc-omap2", "ti,sysc";
1387                         reg = <0x59000 0x4>,
1388                               <0x59010 0x4>,
1389                               <0x59114 0x4>;
1390                         reg-names = "rev", "sysc", "syss";
1391                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1392                                          SYSC_OMAP2_SOFTRESET |
1393                                          SYSC_OMAP2_AUTOIDLE)>;
1394                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1395                                         <SYSC_IDLE_NO>,
1396                                         <SYSC_IDLE_SMART>,
1397                                         <SYSC_IDLE_SMART_WKUP>;
1398                         ti,syss-mask = <1>;
1399                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1400                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1401                                  <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1402                         clock-names = "fck", "dbclk";
1403                         #address-cells = <1>;
1404                         #size-cells = <1>;
1405                         ranges = <0x0 0x59000 0x1000>;
1406
1407                         gpio4: gpio@0 {
1408                                 compatible = "ti,omap4-gpio";
1409                                 reg = <0x0 0x200>;
1410                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1411                                 gpio-controller;
1412                                 #gpio-cells = <2>;
1413                                 interrupt-controller;
1414                                 #interrupt-cells = <2>;
1415                         };
1416                 };
1417
1418                 target-module@5b000 {                   /* 0x4805b000, ap 19 1e.0 */
1419                         compatible = "ti,sysc-omap2", "ti,sysc";
1420                         reg = <0x5b000 0x4>,
1421                               <0x5b010 0x4>,
1422                               <0x5b114 0x4>;
1423                         reg-names = "rev", "sysc", "syss";
1424                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1425                                          SYSC_OMAP2_SOFTRESET |
1426                                          SYSC_OMAP2_AUTOIDLE)>;
1427                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1428                                         <SYSC_IDLE_NO>,
1429                                         <SYSC_IDLE_SMART>,
1430                                         <SYSC_IDLE_SMART_WKUP>;
1431                         ti,syss-mask = <1>;
1432                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1433                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1434                                  <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1435                         clock-names = "fck", "dbclk";
1436                         #address-cells = <1>;
1437                         #size-cells = <1>;
1438                         ranges = <0x0 0x5b000 0x1000>;
1439
1440                         gpio5: gpio@0 {
1441                                 compatible = "ti,omap4-gpio";
1442                                 reg = <0x0 0x200>;
1443                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1444                                 gpio-controller;
1445                                 #gpio-cells = <2>;
1446                                 interrupt-controller;
1447                                 #interrupt-cells = <2>;
1448                         };
1449                 };
1450
1451                 target-module@5d000 {                   /* 0x4805d000, ap 21 26.0 */
1452                         compatible = "ti,sysc-omap2", "ti,sysc";
1453                         reg = <0x5d000 0x4>,
1454                               <0x5d010 0x4>,
1455                               <0x5d114 0x4>;
1456                         reg-names = "rev", "sysc", "syss";
1457                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1458                                          SYSC_OMAP2_SOFTRESET |
1459                                          SYSC_OMAP2_AUTOIDLE)>;
1460                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1461                                         <SYSC_IDLE_NO>,
1462                                         <SYSC_IDLE_SMART>,
1463                                         <SYSC_IDLE_SMART_WKUP>;
1464                         ti,syss-mask = <1>;
1465                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1466                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1467                                  <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1468                         clock-names = "fck", "dbclk";
1469                         #address-cells = <1>;
1470                         #size-cells = <1>;
1471                         ranges = <0x0 0x5d000 0x1000>;
1472
1473                         gpio6: gpio@0 {
1474                                 compatible = "ti,omap4-gpio";
1475                                 reg = <0x0 0x200>;
1476                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1477                                 gpio-controller;
1478                                 #gpio-cells = <2>;
1479                                 interrupt-controller;
1480                                 #interrupt-cells = <2>;
1481                         };
1482                 };
1483
1484                 target-module@60000 {                   /* 0x48060000, ap 23 32.0 */
1485                         compatible = "ti,sysc-omap2", "ti,sysc";
1486                         reg = <0x60000 0x8>,
1487                               <0x60010 0x8>,
1488                               <0x60090 0x8>;
1489                         reg-names = "rev", "sysc", "syss";
1490                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1491                                          SYSC_OMAP2_ENAWAKEUP |
1492                                          SYSC_OMAP2_SOFTRESET |
1493                                          SYSC_OMAP2_AUTOIDLE)>;
1494                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1495                                         <SYSC_IDLE_NO>,
1496                                         <SYSC_IDLE_SMART>,
1497                                         <SYSC_IDLE_SMART_WKUP>;
1498                         ti,syss-mask = <1>;
1499                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1500                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1501                         clock-names = "fck";
1502                         #address-cells = <1>;
1503                         #size-cells = <1>;
1504                         ranges = <0x0 0x60000 0x1000>;
1505
1506                         i2c3: i2c@0 {
1507                                 compatible = "ti,omap4-i2c";
1508                                 reg = <0x0 0x100>;
1509                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1510                                 #address-cells = <1>;
1511                                 #size-cells = <0>;
1512                                 status = "disabled";
1513                         };
1514                 };
1515
1516                 target-module@66000 {                   /* 0x48066000, ap 63 14.0 */
1517                         compatible = "ti,sysc-omap2", "ti,sysc";
1518                         reg = <0x66050 0x4>,
1519                               <0x66054 0x4>,
1520                               <0x66058 0x4>;
1521                         reg-names = "rev", "sysc", "syss";
1522                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1523                                          SYSC_OMAP2_SOFTRESET |
1524                                          SYSC_OMAP2_AUTOIDLE)>;
1525                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1526                                         <SYSC_IDLE_NO>,
1527                                         <SYSC_IDLE_SMART>,
1528                                         <SYSC_IDLE_SMART_WKUP>;
1529                         ti,syss-mask = <1>;
1530                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1531                         clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1532                         clock-names = "fck";
1533                         #address-cells = <1>;
1534                         #size-cells = <1>;
1535                         ranges = <0x0 0x66000 0x1000>;
1536
1537                         uart5: serial@0 {
1538                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1539                                 reg = <0x0 0x100>;
1540                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1541                                 clock-frequency = <48000000>;
1542                                 status = "disabled";
1543                                 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1544                                 dma-names = "tx", "rx";
1545                         };
1546                 };
1547
1548                 target-module@68000 {                   /* 0x48068000, ap 53 1c.0 */
1549                         compatible = "ti,sysc-omap2", "ti,sysc";
1550                         reg = <0x68050 0x4>,
1551                               <0x68054 0x4>,
1552                               <0x68058 0x4>;
1553                         reg-names = "rev", "sysc", "syss";
1554                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1555                                          SYSC_OMAP2_SOFTRESET |
1556                                          SYSC_OMAP2_AUTOIDLE)>;
1557                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1558                                         <SYSC_IDLE_NO>,
1559                                         <SYSC_IDLE_SMART>,
1560                                         <SYSC_IDLE_SMART_WKUP>;
1561                         ti,syss-mask = <1>;
1562                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1563                         clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1564                         clock-names = "fck";
1565                         #address-cells = <1>;
1566                         #size-cells = <1>;
1567                         ranges = <0x0 0x68000 0x1000>;
1568
1569                         uart6: serial@0 {
1570                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1571                                 reg = <0x0 0x100>;
1572                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1573                                 clock-frequency = <48000000>;
1574                                 status = "disabled";
1575                                 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1576                                 dma-names = "tx", "rx";
1577                         };
1578                 };
1579
1580                 target-module@6a000 {                   /* 0x4806a000, ap 24 24.0 */
1581                         compatible = "ti,sysc-omap2", "ti,sysc";
1582                         reg = <0x6a050 0x4>,
1583                               <0x6a054 0x4>,
1584                               <0x6a058 0x4>;
1585                         reg-names = "rev", "sysc", "syss";
1586                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1587                                          SYSC_OMAP2_SOFTRESET |
1588                                          SYSC_OMAP2_AUTOIDLE)>;
1589                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1590                                         <SYSC_IDLE_NO>,
1591                                         <SYSC_IDLE_SMART>,
1592                                         <SYSC_IDLE_SMART_WKUP>;
1593                         ti,syss-mask = <1>;
1594                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1595                         clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1596                         clock-names = "fck";
1597                         #address-cells = <1>;
1598                         #size-cells = <1>;
1599                         ranges = <0x0 0x6a000 0x1000>;
1600
1601                         uart1: serial@0 {
1602                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1603                                 reg = <0x0 0x100>;
1604                                 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1605                                 clock-frequency = <48000000>;
1606                                 status = "disabled";
1607                                 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1608                                 dma-names = "tx", "rx";
1609                         };
1610                 };
1611
1612                 target-module@6c000 {                   /* 0x4806c000, ap 26 2c.0 */
1613                         compatible = "ti,sysc-omap2", "ti,sysc";
1614                         reg = <0x6c050 0x4>,
1615                               <0x6c054 0x4>,
1616                               <0x6c058 0x4>;
1617                         reg-names = "rev", "sysc", "syss";
1618                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1619                                          SYSC_OMAP2_SOFTRESET |
1620                                          SYSC_OMAP2_AUTOIDLE)>;
1621                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1622                                         <SYSC_IDLE_NO>,
1623                                         <SYSC_IDLE_SMART>,
1624                                         <SYSC_IDLE_SMART_WKUP>;
1625                         ti,syss-mask = <1>;
1626                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1627                         clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1628                         clock-names = "fck";
1629                         #address-cells = <1>;
1630                         #size-cells = <1>;
1631                         ranges = <0x0 0x6c000 0x1000>;
1632
1633                         uart2: serial@0 {
1634                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1635                                 reg = <0x0 0x100>;
1636                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1637                                 clock-frequency = <48000000>;
1638                                 status = "disabled";
1639                                 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1640                                 dma-names = "tx", "rx";
1641                         };
1642                 };
1643
1644                 target-module@6e000 {                   /* 0x4806e000, ap 28 0c.1 */
1645                         compatible = "ti,sysc-omap2", "ti,sysc";
1646                         reg = <0x6e050 0x4>,
1647                               <0x6e054 0x4>,
1648                               <0x6e058 0x4>;
1649                         reg-names = "rev", "sysc", "syss";
1650                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1651                                          SYSC_OMAP2_SOFTRESET |
1652                                          SYSC_OMAP2_AUTOIDLE)>;
1653                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1654                                         <SYSC_IDLE_NO>,
1655                                         <SYSC_IDLE_SMART>,
1656                                         <SYSC_IDLE_SMART_WKUP>;
1657                         ti,syss-mask = <1>;
1658                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1659                         clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1660                         clock-names = "fck";
1661                         #address-cells = <1>;
1662                         #size-cells = <1>;
1663                         ranges = <0x0 0x6e000 0x1000>;
1664
1665                         uart4: serial@0 {
1666                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1667                                 reg = <0x0 0x100>;
1668                                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1669                                 clock-frequency = <48000000>;
1670                                                 status = "disabled";
1671                                 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1672                                 dma-names = "tx", "rx";
1673                         };
1674                 };
1675
1676                 target-module@70000 {                   /* 0x48070000, ap 30 22.0 */
1677                         compatible = "ti,sysc-omap2", "ti,sysc";
1678                         reg = <0x70000 0x8>,
1679                               <0x70010 0x8>,
1680                               <0x70090 0x8>;
1681                         reg-names = "rev", "sysc", "syss";
1682                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1683                                          SYSC_OMAP2_ENAWAKEUP |
1684                                          SYSC_OMAP2_SOFTRESET |
1685                                          SYSC_OMAP2_AUTOIDLE)>;
1686                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1687                                         <SYSC_IDLE_NO>,
1688                                         <SYSC_IDLE_SMART>,
1689                                         <SYSC_IDLE_SMART_WKUP>;
1690                         ti,syss-mask = <1>;
1691                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1692                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1693                         clock-names = "fck";
1694                         #address-cells = <1>;
1695                         #size-cells = <1>;
1696                         ranges = <0x0 0x70000 0x1000>;
1697
1698                         i2c1: i2c@0 {
1699                                 compatible = "ti,omap4-i2c";
1700                                 reg = <0x0 0x100>;
1701                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1702                                 #address-cells = <1>;
1703                                 #size-cells = <0>;
1704                                 status = "disabled";
1705                         };
1706                 };
1707
1708                 target-module@72000 {                   /* 0x48072000, ap 32 2a.0 */
1709                         compatible = "ti,sysc-omap2", "ti,sysc";
1710                         reg = <0x72000 0x8>,
1711                               <0x72010 0x8>,
1712                               <0x72090 0x8>;
1713                         reg-names = "rev", "sysc", "syss";
1714                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1715                                          SYSC_OMAP2_ENAWAKEUP |
1716                                          SYSC_OMAP2_SOFTRESET |
1717                                          SYSC_OMAP2_AUTOIDLE)>;
1718                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1719                                         <SYSC_IDLE_NO>,
1720                                         <SYSC_IDLE_SMART>,
1721                                         <SYSC_IDLE_SMART_WKUP>;
1722                         ti,syss-mask = <1>;
1723                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1724                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1725                         clock-names = "fck";
1726                         #address-cells = <1>;
1727                         #size-cells = <1>;
1728                         ranges = <0x0 0x72000 0x1000>;
1729
1730                         i2c2: i2c@0 {
1731                                 compatible = "ti,omap4-i2c";
1732                                 reg = <0x0 0x100>;
1733                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1734                                 #address-cells = <1>;
1735                                 #size-cells = <0>;
1736                                 status = "disabled";
1737                         };
1738                 };
1739
1740                 target-module@78000 {                   /* 0x48078000, ap 39 0a.0 */
1741                         compatible = "ti,sysc-omap2", "ti,sysc";
1742                         reg = <0x78000 0x4>,
1743                               <0x78010 0x4>,
1744                               <0x78014 0x4>;
1745                         reg-names = "rev", "sysc", "syss";
1746                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1747                                          SYSC_OMAP2_SOFTRESET |
1748                                          SYSC_OMAP2_AUTOIDLE)>;
1749                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1750                                         <SYSC_IDLE_NO>,
1751                                         <SYSC_IDLE_SMART>,
1752                                         <SYSC_IDLE_SMART_WKUP>;
1753                         ti,syss-mask = <1>;
1754                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1755                         clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1756                         clock-names = "fck";
1757                         #address-cells = <1>;
1758                         #size-cells = <1>;
1759                         ranges = <0x0 0x78000 0x1000>;
1760
1761                         elm: elm@0 {
1762                                 compatible = "ti,am3352-elm";
1763                                 reg = <0x0 0xfc0>;      /* device IO registers */
1764                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1765                                 status = "disabled";
1766                         };
1767                 };
1768
1769                 target-module@7a000 {                   /* 0x4807a000, ap 81 3a.0 */
1770                         compatible = "ti,sysc-omap2", "ti,sysc";
1771                         reg = <0x7a000 0x8>,
1772                               <0x7a010 0x8>,
1773                               <0x7a090 0x8>;
1774                         reg-names = "rev", "sysc", "syss";
1775                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1776                                          SYSC_OMAP2_ENAWAKEUP |
1777                                          SYSC_OMAP2_SOFTRESET |
1778                                          SYSC_OMAP2_AUTOIDLE)>;
1779                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1780                                         <SYSC_IDLE_NO>,
1781                                         <SYSC_IDLE_SMART>,
1782                                         <SYSC_IDLE_SMART_WKUP>;
1783                         ti,syss-mask = <1>;
1784                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1785                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1786                         clock-names = "fck";
1787                         #address-cells = <1>;
1788                         #size-cells = <1>;
1789                         ranges = <0x0 0x7a000 0x1000>;
1790
1791                         i2c4: i2c@0 {
1792                                 compatible = "ti,omap4-i2c";
1793                                 reg = <0x0 0x100>;
1794                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1795                                 #address-cells = <1>;
1796                                 #size-cells = <0>;
1797                                 status = "disabled";
1798                         };
1799                 };
1800
1801                 target-module@7c000 {                   /* 0x4807c000, ap 83 4a.0 */
1802                         compatible = "ti,sysc-omap2", "ti,sysc";
1803                         reg = <0x7c000 0x8>,
1804                               <0x7c010 0x8>,
1805                               <0x7c090 0x8>;
1806                         reg-names = "rev", "sysc", "syss";
1807                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1808                                          SYSC_OMAP2_ENAWAKEUP |
1809                                          SYSC_OMAP2_SOFTRESET |
1810                                          SYSC_OMAP2_AUTOIDLE)>;
1811                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1812                                         <SYSC_IDLE_NO>,
1813                                         <SYSC_IDLE_SMART>,
1814                                         <SYSC_IDLE_SMART_WKUP>;
1815                         ti,syss-mask = <1>;
1816                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1817                         clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1818                         clock-names = "fck";
1819                         #address-cells = <1>;
1820                         #size-cells = <1>;
1821                         ranges = <0x0 0x7c000 0x1000>;
1822
1823                         i2c5: i2c@0 {
1824                                 compatible = "ti,omap4-i2c";
1825                                 reg = <0x0 0x100>;
1826                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1827                                 #address-cells = <1>;
1828                                 #size-cells = <0>;
1829                                 status = "disabled";
1830                         };
1831                 };
1832
1833                 target-module@86000 {                   /* 0x48086000, ap 41 5e.0 */
1834                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1835                         reg = <0x86000 0x4>,
1836                               <0x86010 0x4>;
1837                         reg-names = "rev", "sysc";
1838                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1839                                          SYSC_OMAP4_SOFTRESET)>;
1840                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1841                                         <SYSC_IDLE_NO>,
1842                                         <SYSC_IDLE_SMART>,
1843                                         <SYSC_IDLE_SMART_WKUP>;
1844                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1845                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1846                         clock-names = "fck";
1847                         #address-cells = <1>;
1848                         #size-cells = <1>;
1849                         ranges = <0x0 0x86000 0x1000>;
1850
1851                         timer10: timer@0 {
1852                                 compatible = "ti,omap5430-timer";
1853                                 reg = <0x0 0x80>;
1854                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
1855                                 clock-names = "fck", "timer_sys_ck";
1856                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1857                         };
1858                 };
1859
1860                 target-module@88000 {                   /* 0x48088000, ap 43 66.0 */
1861                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1862                         reg = <0x88000 0x4>,
1863                               <0x88010 0x4>;
1864                         reg-names = "rev", "sysc";
1865                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1866                                          SYSC_OMAP4_SOFTRESET)>;
1867                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1868                                         <SYSC_IDLE_NO>,
1869                                         <SYSC_IDLE_SMART>,
1870                                         <SYSC_IDLE_SMART_WKUP>;
1871                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1872                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1873                         clock-names = "fck";
1874                         #address-cells = <1>;
1875                         #size-cells = <1>;
1876                         ranges = <0x0 0x88000 0x1000>;
1877
1878                         timer11: timer@0 {
1879                                 compatible = "ti,omap5430-timer";
1880                                 reg = <0x0 0x80>;
1881                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
1882                                 clock-names = "fck", "timer_sys_ck";
1883                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1884                         };
1885                 };
1886
1887                 target-module@90000 {                   /* 0x48090000, ap 55 12.0 */
1888                         compatible = "ti,sysc-omap2", "ti,sysc";
1889                         reg = <0x91fe0 0x4>,
1890                               <0x91fe4 0x4>;
1891                         reg-names = "rev", "sysc";
1892                         ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1893                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1894                                         <SYSC_IDLE_NO>;
1895                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1896                         clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1897                         clock-names = "fck";
1898                         #address-cells = <1>;
1899                         #size-cells = <1>;
1900                         ranges = <0x0 0x90000 0x2000>;
1901
1902                         rng: rng@0 {
1903                                 compatible = "ti,omap4-rng";
1904                                 reg = <0x0 0x2000>;
1905                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1906                                 clocks = <&l3_iclk_div>;
1907                                 clock-names = "fck";
1908                         };
1909                 };
1910
1911                 target-module@98000 {                   /* 0x48098000, ap 47 08.0 */
1912                         compatible = "ti,sysc-omap4", "ti,sysc";
1913                         reg = <0x98000 0x4>,
1914                               <0x98010 0x4>;
1915                         reg-names = "rev", "sysc";
1916                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1917                                          SYSC_OMAP4_SOFTRESET)>;
1918                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1919                                         <SYSC_IDLE_NO>,
1920                                         <SYSC_IDLE_SMART>,
1921                                         <SYSC_IDLE_SMART_WKUP>;
1922                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1923                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1924                         clock-names = "fck";
1925                         #address-cells = <1>;
1926                         #size-cells = <1>;
1927                         ranges = <0x0 0x98000 0x1000>;
1928
1929                         mcspi1: spi@0 {
1930                                 compatible = "ti,omap4-mcspi";
1931                                 reg = <0x0 0x200>;
1932                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1933                                 #address-cells = <1>;
1934                                 #size-cells = <0>;
1935                                 ti,spi-num-cs = <4>;
1936                                 dmas = <&sdma_xbar 35>,
1937                                        <&sdma_xbar 36>,
1938                                        <&sdma_xbar 37>,
1939                                        <&sdma_xbar 38>,
1940                                        <&sdma_xbar 39>,
1941                                        <&sdma_xbar 40>,
1942                                        <&sdma_xbar 41>,
1943                                        <&sdma_xbar 42>;
1944                                 dma-names = "tx0", "rx0", "tx1", "rx1",
1945                                             "tx2", "rx2", "tx3", "rx3";
1946                                 status = "disabled";
1947                         };
1948                 };
1949
1950                 target-module@9a000 {                   /* 0x4809a000, ap 49 10.0 */
1951                         compatible = "ti,sysc-omap4", "ti,sysc";
1952                         reg = <0x9a000 0x4>,
1953                               <0x9a010 0x4>;
1954                         reg-names = "rev", "sysc";
1955                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1956                                          SYSC_OMAP4_SOFTRESET)>;
1957                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1958                                         <SYSC_IDLE_NO>,
1959                                         <SYSC_IDLE_SMART>,
1960                                         <SYSC_IDLE_SMART_WKUP>;
1961                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1962                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1963                         clock-names = "fck";
1964                         #address-cells = <1>;
1965                         #size-cells = <1>;
1966                         ranges = <0x0 0x9a000 0x1000>;
1967
1968                         mcspi2: spi@0 {
1969                                 compatible = "ti,omap4-mcspi";
1970                                 reg = <0x0 0x200>;
1971                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1972                                 #address-cells = <1>;
1973                                 #size-cells = <0>;
1974                                 ti,spi-num-cs = <2>;
1975                                 dmas = <&sdma_xbar 43>,
1976                                        <&sdma_xbar 44>,
1977                                        <&sdma_xbar 45>,
1978                                        <&sdma_xbar 46>;
1979                                 dma-names = "tx0", "rx0", "tx1", "rx1";
1980                                 status = "disabled";
1981                         };
1982                 };
1983
1984                 target-module@9c000 {                   /* 0x4809c000, ap 51 38.0 */
1985                         compatible = "ti,sysc-omap4", "ti,sysc";
1986                         reg = <0x9c000 0x4>,
1987                               <0x9c010 0x4>;
1988                         reg-names = "rev", "sysc";
1989                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1990                                          SYSC_OMAP4_SOFTRESET)>;
1991                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
1992                                         <SYSC_IDLE_NO>,
1993                                         <SYSC_IDLE_SMART>,
1994                                         <SYSC_IDLE_SMART_WKUP>;
1995                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1996                                         <SYSC_IDLE_NO>,
1997                                         <SYSC_IDLE_SMART>,
1998                                         <SYSC_IDLE_SMART_WKUP>;
1999                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2000                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2001                         clock-names = "fck";
2002                         #address-cells = <1>;
2003                         #size-cells = <1>;
2004                         ranges = <0x0 0x9c000 0x1000>;
2005
2006                         mmc1: mmc@0 {
2007                                 compatible = "ti,dra7-sdhci";
2008                                 reg = <0x0 0x400>;
2009                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2010                                 status = "disabled";
2011                                 pbias-supply = <&pbias_mmc_reg>;
2012                                 max-frequency = <192000000>;
2013                                 mmc-ddr-1_8v;
2014                                 mmc-ddr-3_3v;
2015                         };
2016                 };
2017
2018                 target-module@a2000 {                   /* 0x480a2000, ap 75 02.0 */
2019                         compatible = "ti,sysc";
2020                         status = "disabled";
2021                         #address-cells = <1>;
2022                         #size-cells = <1>;
2023                         ranges = <0x0 0xa2000 0x1000>;
2024                 };
2025
2026                 target-module@a4000 {                   /* 0x480a4000, ap 57 42.0 */
2027                         compatible = "ti,sysc";
2028                         status = "disabled";
2029                         #address-cells = <1>;
2030                         #size-cells = <1>;
2031                         ranges = <0x00000000 0x000a4000 0x00001000>,
2032                                  <0x00001000 0x000a5000 0x00001000>;
2033                 };
2034
2035                 des_target: target-module@a5000 {       /* 0x480a5000 */
2036                         compatible = "ti,sysc-omap2", "ti,sysc";
2037                         reg = <0xa5030 0x4>,
2038                               <0xa5034 0x4>,
2039                               <0xa5038 0x4>;
2040                         reg-names = "rev", "sysc", "syss";
2041                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2042                                          SYSC_OMAP2_AUTOIDLE)>;
2043                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2044                                         <SYSC_IDLE_NO>,
2045                                         <SYSC_IDLE_SMART>,
2046                                         <SYSC_IDLE_SMART_WKUP>;
2047                         ti,syss-mask = <1>;
2048                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
2049                         clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2050                         clock-names = "fck";
2051                         #address-cells = <1>;
2052                         #size-cells = <1>;
2053                         ranges = <0 0xa5000 0x00001000>;
2054
2055                         des: des@0 {
2056                                 compatible = "ti,omap4-des";
2057                                 reg = <0 0xa0>;
2058                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2059                                 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2060                                 dma-names = "tx", "rx";
2061                                 clocks = <&l3_iclk_div>;
2062                                 clock-names = "fck";
2063                         };
2064                 };
2065
2066                 target-module@a8000 {                   /* 0x480a8000, ap 59 1a.0 */
2067                         compatible = "ti,sysc";
2068                         status = "disabled";
2069                         #address-cells = <1>;
2070                         #size-cells = <1>;
2071                         ranges = <0x0 0xa8000 0x4000>;
2072                 };
2073
2074                 target-module@ad000 {                   /* 0x480ad000, ap 61 20.0 */
2075                         compatible = "ti,sysc-omap4", "ti,sysc";
2076                         reg = <0xad000 0x4>,
2077                               <0xad010 0x4>;
2078                         reg-names = "rev", "sysc";
2079                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2080                                          SYSC_OMAP4_SOFTRESET)>;
2081                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2082                                         <SYSC_IDLE_NO>,
2083                                         <SYSC_IDLE_SMART>,
2084                                         <SYSC_IDLE_SMART_WKUP>;
2085                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2086                                         <SYSC_IDLE_NO>,
2087                                         <SYSC_IDLE_SMART>,
2088                                         <SYSC_IDLE_SMART_WKUP>;
2089                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2090                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2091                         clock-names = "fck";
2092                         #address-cells = <1>;
2093                         #size-cells = <1>;
2094                         ranges = <0x0 0xad000 0x1000>;
2095
2096                         mmc3: mmc@0 {
2097                                 compatible = "ti,dra7-sdhci";
2098                                 reg = <0x0 0x400>;
2099                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2100                                 status = "disabled";
2101                                 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2102                                 max-frequency = <64000000>;
2103                                 /* SDMA is not supported */
2104                                 sdhci-caps-mask = <0x0 0x400000>;
2105                         };
2106                 };
2107
2108                 target-module@b2000 {                   /* 0x480b2000, ap 37 52.0 */
2109                         compatible = "ti,sysc-omap2", "ti,sysc";
2110                         reg = <0xb2000 0x4>,
2111                               <0xb2014 0x4>,
2112                               <0xb2018 0x4>;
2113                         reg-names = "rev", "sysc", "syss";
2114                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2115                                          SYSC_OMAP2_AUTOIDLE)>;
2116                         ti,syss-mask = <1>;
2117                         ti,no-reset-on-init;
2118                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2119                         clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2120                         clock-names = "fck";
2121                         #address-cells = <1>;
2122                         #size-cells = <1>;
2123                         ranges = <0x0 0xb2000 0x1000>;
2124
2125                         hdqw1w: 1w@0 {
2126                                 compatible = "ti,omap3-1w";
2127                                 reg = <0x0 0x1000>;
2128                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2129                         };
2130                 };
2131
2132                 target-module@b4000 {                   /* 0x480b4000, ap 65 40.0 */
2133                         compatible = "ti,sysc-omap4", "ti,sysc";
2134                         reg = <0xb4000 0x4>,
2135                               <0xb4010 0x4>;
2136                         reg-names = "rev", "sysc";
2137                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2138                                          SYSC_OMAP4_SOFTRESET)>;
2139                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2140                                         <SYSC_IDLE_NO>,
2141                                         <SYSC_IDLE_SMART>,
2142                                         <SYSC_IDLE_SMART_WKUP>;
2143                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2144                                         <SYSC_IDLE_NO>,
2145                                         <SYSC_IDLE_SMART>,
2146                                         <SYSC_IDLE_SMART_WKUP>;
2147                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2148                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2149                         clock-names = "fck";
2150                         #address-cells = <1>;
2151                         #size-cells = <1>;
2152                         ranges = <0x0 0xb4000 0x1000>;
2153
2154                         mmc2: mmc@0 {
2155                                 compatible = "ti,dra7-sdhci";
2156                                 reg = <0x0 0x400>;
2157                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2158                                 status = "disabled";
2159                                 max-frequency = <192000000>;
2160                                 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2161                                 sdhci-caps-mask = <0x7 0x0>;
2162                                 mmc-hs200-1_8v;
2163                                 mmc-ddr-1_8v;
2164                                 mmc-ddr-3_3v;
2165                         };
2166                 };
2167
2168                 target-module@b8000 {                   /* 0x480b8000, ap 67 48.0 */
2169                         compatible = "ti,sysc-omap4", "ti,sysc";
2170                         reg = <0xb8000 0x4>,
2171                               <0xb8010 0x4>;
2172                         reg-names = "rev", "sysc";
2173                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2174                                          SYSC_OMAP4_SOFTRESET)>;
2175                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2176                                         <SYSC_IDLE_NO>,
2177                                         <SYSC_IDLE_SMART>,
2178                                         <SYSC_IDLE_SMART_WKUP>;
2179                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2180                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2181                         clock-names = "fck";
2182                         #address-cells = <1>;
2183                         #size-cells = <1>;
2184                         ranges = <0x0 0xb8000 0x1000>;
2185
2186                         mcspi3: spi@0 {
2187                                 compatible = "ti,omap4-mcspi";
2188                                 reg = <0x0 0x200>;
2189                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2190                                 #address-cells = <1>;
2191                                 #size-cells = <0>;
2192                                 ti,spi-num-cs = <2>;
2193                                 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2194                                 dma-names = "tx0", "rx0";
2195                                 status = "disabled";
2196                         };
2197                 };
2198
2199                 target-module@ba000 {                   /* 0x480ba000, ap 69 18.0 */
2200                         compatible = "ti,sysc-omap4", "ti,sysc";
2201                         reg = <0xba000 0x4>,
2202                               <0xba010 0x4>;
2203                         reg-names = "rev", "sysc";
2204                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2205                                          SYSC_OMAP4_SOFTRESET)>;
2206                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2207                                         <SYSC_IDLE_NO>,
2208                                         <SYSC_IDLE_SMART>,
2209                                         <SYSC_IDLE_SMART_WKUP>;
2210                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2211                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2212                         clock-names = "fck";
2213                         #address-cells = <1>;
2214                         #size-cells = <1>;
2215                         ranges = <0x0 0xba000 0x1000>;
2216
2217                         mcspi4: spi@0 {
2218                                 compatible = "ti,omap4-mcspi";
2219                                 reg = <0x0 0x200>;
2220                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2221                                 #address-cells = <1>;
2222                                 #size-cells = <0>;
2223                                 ti,spi-num-cs = <1>;
2224                                 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2225                                 dma-names = "tx0", "rx0";
2226                                 status = "disabled";
2227                         };
2228                 };
2229
2230                 target-module@d1000 {                   /* 0x480d1000, ap 71 28.0 */
2231                         compatible = "ti,sysc-omap4", "ti,sysc";
2232                         reg = <0xd1000 0x4>,
2233                               <0xd1010 0x4>;
2234                         reg-names = "rev", "sysc";
2235                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2236                                          SYSC_OMAP4_SOFTRESET)>;
2237                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2238                                         <SYSC_IDLE_NO>,
2239                                         <SYSC_IDLE_SMART>,
2240                                         <SYSC_IDLE_SMART_WKUP>;
2241                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2242                                         <SYSC_IDLE_NO>,
2243                                         <SYSC_IDLE_SMART>,
2244                                         <SYSC_IDLE_SMART_WKUP>;
2245                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2246                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2247                         clock-names = "fck";
2248                         #address-cells = <1>;
2249                         #size-cells = <1>;
2250                         ranges = <0x0 0xd1000 0x1000>;
2251
2252                         mmc4: mmc@0 {
2253                                 compatible = "ti,dra7-sdhci";
2254                                 reg = <0x0 0x400>;
2255                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2256                                 status = "disabled";
2257                                 max-frequency = <192000000>;
2258                                 /* SDMA is not supported */
2259                                 sdhci-caps-mask = <0x0 0x400000>;
2260                         };
2261                 };
2262
2263                 target-module@d5000 {                   /* 0x480d5000, ap 73 30.0 */
2264                         compatible = "ti,sysc";
2265                         status = "disabled";
2266                         #address-cells = <1>;
2267                         #size-cells = <1>;
2268                         ranges = <0x0 0xd5000 0x1000>;
2269                 };
2270         };
2271
2272         segment@200000 {                                        /* 0x48200000 */
2273                 compatible = "simple-bus";
2274                 #address-cells = <1>;
2275                 #size-cells = <1>;
2276         };
2277 };
2278
2279 &l4_per2 {                                              /* 0x48400000 */
2280         compatible = "ti,dra7-l4-per2", "simple-bus";
2281         reg = <0x48400000 0x800>,
2282               <0x48400800 0x800>,
2283               <0x48401000 0x400>,
2284               <0x48401400 0x400>,
2285               <0x48401800 0x400>;
2286         reg-names = "ap", "la", "ia0", "ia1", "ia2";
2287         #address-cells = <1>;
2288         #size-cells = <1>;
2289         ranges = <0x00000000 0x48400000 0x400000>,      /* segment 0 */
2290                  <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2291                  <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2292                  <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2293                  <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2294                  <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2295                  <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2296                  <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2297                  <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2298
2299         segment@0 {                                     /* 0x48400000 */
2300                 compatible = "simple-bus";
2301                 #address-cells = <1>;
2302                 #size-cells = <1>;
2303                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
2304                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
2305                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
2306                          <0x00084000 0x00084000 0x004000>,      /* ap 3 */
2307                          <0x00001400 0x00001400 0x000400>,      /* ap 4 */
2308                          <0x00001800 0x00001800 0x000400>,      /* ap 5 */
2309                          <0x00088000 0x00088000 0x001000>,      /* ap 6 */
2310                          <0x0002c000 0x0002c000 0x001000>,      /* ap 7 */
2311                          <0x0002d000 0x0002d000 0x001000>,      /* ap 8 */
2312                          <0x00060000 0x00060000 0x002000>,      /* ap 9 */
2313                          <0x00062000 0x00062000 0x001000>,      /* ap 10 */
2314                          <0x00064000 0x00064000 0x002000>,      /* ap 11 */
2315                          <0x00066000 0x00066000 0x001000>,      /* ap 12 */
2316                          <0x00068000 0x00068000 0x002000>,      /* ap 13 */
2317                          <0x0006a000 0x0006a000 0x001000>,      /* ap 14 */
2318                          <0x0006c000 0x0006c000 0x002000>,      /* ap 15 */
2319                          <0x0006e000 0x0006e000 0x001000>,      /* ap 16 */
2320                          <0x00036000 0x00036000 0x001000>,      /* ap 17 */
2321                          <0x00037000 0x00037000 0x001000>,      /* ap 18 */
2322                          <0x00070000 0x00070000 0x002000>,      /* ap 19 */
2323                          <0x00072000 0x00072000 0x001000>,      /* ap 20 */
2324                          <0x0003a000 0x0003a000 0x001000>,      /* ap 21 */
2325                          <0x0003b000 0x0003b000 0x001000>,      /* ap 22 */
2326                          <0x0003c000 0x0003c000 0x001000>,      /* ap 23 */
2327                          <0x0003d000 0x0003d000 0x001000>,      /* ap 24 */
2328                          <0x0003e000 0x0003e000 0x001000>,      /* ap 25 */
2329                          <0x0003f000 0x0003f000 0x001000>,      /* ap 26 */
2330                          <0x00040000 0x00040000 0x001000>,      /* ap 27 */
2331                          <0x00041000 0x00041000 0x001000>,      /* ap 28 */
2332                          <0x00042000 0x00042000 0x001000>,      /* ap 29 */
2333                          <0x00043000 0x00043000 0x001000>,      /* ap 30 */
2334                          <0x00080000 0x00080000 0x002000>,      /* ap 31 */
2335                          <0x00082000 0x00082000 0x001000>,      /* ap 32 */
2336                          <0x0004a000 0x0004a000 0x001000>,      /* ap 33 */
2337                          <0x0004b000 0x0004b000 0x001000>,      /* ap 34 */
2338                          <0x00074000 0x00074000 0x002000>,      /* ap 35 */
2339                          <0x00076000 0x00076000 0x001000>,      /* ap 36 */
2340                          <0x00050000 0x00050000 0x001000>,      /* ap 37 */
2341                          <0x00051000 0x00051000 0x001000>,      /* ap 38 */
2342                          <0x00078000 0x00078000 0x002000>,      /* ap 39 */
2343                          <0x0007a000 0x0007a000 0x001000>,      /* ap 40 */
2344                          <0x00054000 0x00054000 0x001000>,      /* ap 41 */
2345                          <0x00055000 0x00055000 0x001000>,      /* ap 42 */
2346                          <0x0007c000 0x0007c000 0x002000>,      /* ap 43 */
2347                          <0x0007e000 0x0007e000 0x001000>,      /* ap 44 */
2348                          <0x0004c000 0x0004c000 0x001000>,      /* ap 45 */
2349                          <0x0004d000 0x0004d000 0x001000>,      /* ap 46 */
2350                          <0x00020000 0x00020000 0x001000>,      /* ap 47 */
2351                          <0x00021000 0x00021000 0x001000>,      /* ap 48 */
2352                          <0x00022000 0x00022000 0x001000>,      /* ap 49 */
2353                          <0x00023000 0x00023000 0x001000>,      /* ap 50 */
2354                          <0x00024000 0x00024000 0x001000>,      /* ap 51 */
2355                          <0x00025000 0x00025000 0x001000>,      /* ap 52 */
2356                          <0x00046000 0x00046000 0x001000>,      /* ap 53 */
2357                          <0x00047000 0x00047000 0x001000>,      /* ap 54 */
2358                          <0x00048000 0x00048000 0x001000>,      /* ap 55 */
2359                          <0x00049000 0x00049000 0x001000>,      /* ap 56 */
2360                          <0x00058000 0x00058000 0x002000>,      /* ap 57 */
2361                          <0x0005a000 0x0005a000 0x001000>,      /* ap 58 */
2362                          <0x0005b000 0x0005b000 0x001000>,      /* ap 59 */
2363                          <0x0005c000 0x0005c000 0x001000>,      /* ap 60 */
2364                          <0x0005d000 0x0005d000 0x001000>,      /* ap 61 */
2365                          <0x0005e000 0x0005e000 0x001000>,      /* ap 62 */
2366                          <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2367                          <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2368                          <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2369                          <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2370                          <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2371                          <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2372                          <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2373                          <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2374
2375                 target-module@20000 {                   /* 0x48420000, ap 47 02.0 */
2376                         compatible = "ti,sysc-omap2", "ti,sysc";
2377                         reg = <0x20050 0x4>,
2378                               <0x20054 0x4>,
2379                               <0x20058 0x4>;
2380                         reg-names = "rev", "sysc", "syss";
2381                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2382                                          SYSC_OMAP2_SOFTRESET |
2383                                          SYSC_OMAP2_AUTOIDLE)>;
2384                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2385                                         <SYSC_IDLE_NO>,
2386                                         <SYSC_IDLE_SMART>,
2387                                         <SYSC_IDLE_SMART_WKUP>;
2388                         ti,syss-mask = <1>;
2389                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2390                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2391                         clock-names = "fck";
2392                         #address-cells = <1>;
2393                         #size-cells = <1>;
2394                         ranges = <0x0 0x20000 0x1000>;
2395
2396                         uart7: serial@0 {
2397                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2398                                 reg = <0x0 0x100>;
2399                                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2400                                 clock-frequency = <48000000>;
2401                                 status = "disabled";
2402                         };
2403                 };
2404
2405                 target-module@22000 {                   /* 0x48422000, ap 49 0a.0 */
2406                         compatible = "ti,sysc-omap2", "ti,sysc";
2407                         reg = <0x22050 0x4>,
2408                               <0x22054 0x4>,
2409                               <0x22058 0x4>;
2410                         reg-names = "rev", "sysc", "syss";
2411                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2412                                          SYSC_OMAP2_SOFTRESET |
2413                                          SYSC_OMAP2_AUTOIDLE)>;
2414                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2415                                         <SYSC_IDLE_NO>,
2416                                         <SYSC_IDLE_SMART>,
2417                                         <SYSC_IDLE_SMART_WKUP>;
2418                         ti,syss-mask = <1>;
2419                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2420                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2421                         clock-names = "fck";
2422                         #address-cells = <1>;
2423                         #size-cells = <1>;
2424                         ranges = <0x0 0x22000 0x1000>;
2425
2426                         uart8: serial@0 {
2427                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2428                                 reg = <0x0 0x100>;
2429                                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2430                                 clock-frequency = <48000000>;
2431                                 status = "disabled";
2432                         };
2433                 };
2434
2435                 target-module@24000 {                   /* 0x48424000, ap 51 12.0 */
2436                         compatible = "ti,sysc-omap2", "ti,sysc";
2437                         reg = <0x24050 0x4>,
2438                               <0x24054 0x4>,
2439                               <0x24058 0x4>;
2440                         reg-names = "rev", "sysc", "syss";
2441                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2442                                          SYSC_OMAP2_SOFTRESET |
2443                                          SYSC_OMAP2_AUTOIDLE)>;
2444                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2445                                         <SYSC_IDLE_NO>,
2446                                         <SYSC_IDLE_SMART>,
2447                                         <SYSC_IDLE_SMART_WKUP>;
2448                         ti,syss-mask = <1>;
2449                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2450                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2451                         clock-names = "fck";
2452                         #address-cells = <1>;
2453                         #size-cells = <1>;
2454                         ranges = <0x0 0x24000 0x1000>;
2455
2456                         uart9: serial@0 {
2457                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2458                                 reg = <0x0 0x100>;
2459                                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2460                                 clock-frequency = <48000000>;
2461                                 status = "disabled";
2462                         };
2463                 };
2464
2465                 target-module@2c000 {                   /* 0x4842c000, ap 7 18.0 */
2466                         compatible = "ti,sysc";
2467                         status = "disabled";
2468                         #address-cells = <1>;
2469                         #size-cells = <1>;
2470                         ranges = <0x0 0x2c000 0x1000>;
2471                 };
2472
2473                 target-module@36000 {                   /* 0x48436000, ap 17 06.0 */
2474                         compatible = "ti,sysc";
2475                         status = "disabled";
2476                         #address-cells = <1>;
2477                         #size-cells = <1>;
2478                         ranges = <0x0 0x36000 0x1000>;
2479                 };
2480
2481                 target-module@3a000 {                   /* 0x4843a000, ap 21 3e.0 */
2482                         compatible = "ti,sysc";
2483                         status = "disabled";
2484                         #address-cells = <1>;
2485                         #size-cells = <1>;
2486                         ranges = <0x0 0x3a000 0x1000>;
2487                 };
2488
2489                 atl_tm: target-module@3c000 {           /* 0x4843c000, ap 23 08.0 */
2490                         compatible = "ti,sysc-omap4", "ti,sysc";
2491                         reg = <0x3c000 0x4>;
2492                         reg-names = "rev";
2493                         clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2494                         clock-names = "fck";
2495                         #address-cells = <1>;
2496                         #size-cells = <1>;
2497                         ranges = <0x0 0x3c000 0x1000>;
2498
2499                         atl: atl@0 {
2500                                 compatible = "ti,dra7-atl";
2501                                 reg = <0x0 0x3ff>;
2502                                 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2503                                                      <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2504                                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2505                                 clock-names = "fck";
2506                                 status = "disabled";
2507                         };
2508                 };
2509
2510                 target-module@3e000 {                   /* 0x4843e000, ap 25 30.0 */
2511                         compatible = "ti,sysc-omap4", "ti,sysc";
2512                         reg = <0x3e000 0x4>,
2513                               <0x3e004 0x4>;
2514                         reg-names = "rev", "sysc";
2515                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2516                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2517                                         <SYSC_IDLE_NO>,
2518                                         <SYSC_IDLE_SMART>;
2519                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2520                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2521                         clock-names = "fck";
2522                         #address-cells = <1>;
2523                         #size-cells = <1>;
2524                         ranges = <0x0 0x3e000 0x1000>;
2525
2526                         epwmss0: epwmss@0 {
2527                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2528                                 reg = <0x0 0x30>;
2529                                 #address-cells = <1>;
2530                                 #size-cells = <1>;
2531                                 status = "disabled";
2532                                 ranges = <0 0 0x1000>;
2533
2534                                 ecap0: ecap@100 {
2535                                         compatible = "ti,dra746-ecap",
2536                                                      "ti,am3352-ecap";
2537                                         #pwm-cells = <3>;
2538                                         reg = <0x100 0x80>;
2539                                         clocks = <&l4_root_clk_div>;
2540                                         clock-names = "fck";
2541                                         status = "disabled";
2542                                 };
2543
2544                                 ehrpwm0: pwm@200 {
2545                                         compatible = "ti,dra746-ehrpwm",
2546                                                      "ti,am3352-ehrpwm";
2547                                         #pwm-cells = <3>;
2548                                         reg = <0x200 0x80>;
2549                                         clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2550                                         clock-names = "tbclk", "fck";
2551                                         status = "disabled";
2552                                 };
2553                         };
2554                 };
2555
2556                 target-module@40000 {                   /* 0x48440000, ap 27 38.0 */
2557                         compatible = "ti,sysc-omap4", "ti,sysc";
2558                         reg = <0x40000 0x4>,
2559                               <0x40004 0x4>;
2560                         reg-names = "rev", "sysc";
2561                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2562                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2563                                         <SYSC_IDLE_NO>,
2564                                         <SYSC_IDLE_SMART>;
2565                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2566                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2567                         clock-names = "fck";
2568                         #address-cells = <1>;
2569                         #size-cells = <1>;
2570                         ranges = <0x0 0x40000 0x1000>;
2571
2572                         epwmss1: epwmss@0 {
2573                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2574                                 reg = <0x0 0x30>;
2575                                 #address-cells = <1>;
2576                                 #size-cells = <1>;
2577                                 status = "disabled";
2578                                 ranges = <0 0 0x1000>;
2579
2580                                 ecap1: ecap@100 {
2581                                         compatible = "ti,dra746-ecap",
2582                                                      "ti,am3352-ecap";
2583                                         #pwm-cells = <3>;
2584                                         reg = <0x100 0x80>;
2585                                         clocks = <&l4_root_clk_div>;
2586                                         clock-names = "fck";
2587                                         status = "disabled";
2588                                 };
2589
2590                                 ehrpwm1: pwm@200 {
2591                                         compatible = "ti,dra746-ehrpwm",
2592                                                      "ti,am3352-ehrpwm";
2593                                         #pwm-cells = <3>;
2594                                         reg = <0x200 0x80>;
2595                                         clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2596                                         clock-names = "tbclk", "fck";
2597                                         status = "disabled";
2598                                 };
2599                         };
2600                 };
2601
2602                 target-module@42000 {                   /* 0x48442000, ap 29 20.0 */
2603                         compatible = "ti,sysc-omap4", "ti,sysc";
2604                         reg = <0x42000 0x4>,
2605                               <0x42004 0x4>;
2606                         reg-names = "rev", "sysc";
2607                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2608                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2609                                         <SYSC_IDLE_NO>,
2610                                         <SYSC_IDLE_SMART>;
2611                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2612                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2613                         clock-names = "fck";
2614                         #address-cells = <1>;
2615                         #size-cells = <1>;
2616                         ranges = <0x0 0x42000 0x1000>;
2617
2618                         epwmss2: epwmss@0 {
2619                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2620                                 reg = <0x0 0x30>;
2621                                 #address-cells = <1>;
2622                                 #size-cells = <1>;
2623                                 status = "disabled";
2624                                 ranges = <0 0 0x1000>;
2625
2626                                 ecap2: ecap@100 {
2627                                         compatible = "ti,dra746-ecap",
2628                                                      "ti,am3352-ecap";
2629                                         #pwm-cells = <3>;
2630                                         reg = <0x100 0x80>;
2631                                         clocks = <&l4_root_clk_div>;
2632                                         clock-names = "fck";
2633                                         status = "disabled";
2634                                 };
2635
2636                                 ehrpwm2: pwm@200 {
2637                                         compatible = "ti,dra746-ehrpwm",
2638                                                      "ti,am3352-ehrpwm";
2639                                         #pwm-cells = <3>;
2640                                         reg = <0x200 0x80>;
2641                                         clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2642                                         clock-names = "tbclk", "fck";
2643                                         status = "disabled";
2644                                 };
2645                         };
2646                 };
2647
2648                 target-module@46000 {                   /* 0x48446000, ap 53 40.0 */
2649                         compatible = "ti,sysc";
2650                         status = "disabled";
2651                         #address-cells = <1>;
2652                         #size-cells = <1>;
2653                         ranges = <0x0 0x46000 0x1000>;
2654                 };
2655
2656                 target-module@48000 {                   /* 0x48448000, ap 55 48.0 */
2657                         compatible = "ti,sysc";
2658                         status = "disabled";
2659                         #address-cells = <1>;
2660                         #size-cells = <1>;
2661                         ranges = <0x0 0x48000 0x1000>;
2662                 };
2663
2664                 target-module@4a000 {                   /* 0x4844a000, ap 33 1a.0 */
2665                         compatible = "ti,sysc";
2666                         status = "disabled";
2667                         #address-cells = <1>;
2668                         #size-cells = <1>;
2669                         ranges = <0x0 0x4a000 0x1000>;
2670                 };
2671
2672                 target-module@4c000 {                   /* 0x4844c000, ap 45 1c.0 */
2673                         compatible = "ti,sysc";
2674                         status = "disabled";
2675                         #address-cells = <1>;
2676                         #size-cells = <1>;
2677                         ranges = <0x0 0x4c000 0x1000>;
2678                 };
2679
2680                 target-module@50000 {                   /* 0x48450000, ap 37 24.0 */
2681                         compatible = "ti,sysc";
2682                         status = "disabled";
2683                         #address-cells = <1>;
2684                         #size-cells = <1>;
2685                         ranges = <0x0 0x50000 0x1000>;
2686                 };
2687
2688                 target-module@54000 {                   /* 0x48454000, ap 41 2c.0 */
2689                         compatible = "ti,sysc";
2690                         status = "disabled";
2691                         #address-cells = <1>;
2692                         #size-cells = <1>;
2693                         ranges = <0x0 0x54000 0x1000>;
2694                 };
2695
2696                 target-module@58000 {                   /* 0x48458000, ap 57 28.0 */
2697                         compatible = "ti,sysc";
2698                         status = "disabled";
2699                         #address-cells = <1>;
2700                         #size-cells = <1>;
2701                         ranges = <0x0 0x58000 0x2000>;
2702                 };
2703
2704                 target-module@5b000 {                   /* 0x4845b000, ap 59 46.0 */
2705                         compatible = "ti,sysc";
2706                         status = "disabled";
2707                         #address-cells = <1>;
2708                         #size-cells = <1>;
2709                         ranges = <0x0 0x5b000 0x1000>;
2710                 };
2711
2712                 target-module@5d000 {                   /* 0x4845d000, ap 61 22.0 */
2713                         compatible = "ti,sysc";
2714                         status = "disabled";
2715                         #address-cells = <1>;
2716                         #size-cells = <1>;
2717                         ranges = <0x0 0x5d000 0x1000>;
2718                 };
2719
2720                 target-module@60000 {                   /* 0x48460000, ap 9 0e.0 */
2721                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2722                         reg = <0x60000 0x4>,
2723                               <0x60004 0x4>;
2724                         reg-names = "rev", "sysc";
2725                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2726                                         <SYSC_IDLE_NO>,
2727                                         <SYSC_IDLE_SMART>;
2728                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2729                         clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2730                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2731                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2732                         clock-names = "fck", "ahclkx", "ahclkr";
2733                         #address-cells = <1>;
2734                         #size-cells = <1>;
2735                         ranges = <0x0 0x60000 0x2000>,
2736                                  <0x45800000 0x45800000 0x400000>;
2737
2738                         mcasp1: mcasp@0 {
2739                                 compatible = "ti,dra7-mcasp-audio";
2740                                 reg = <0x0 0x2000>,
2741                                       <0x45800000 0x1000>;      /* L3 data port */
2742                                 reg-names = "mpu","dat";
2743                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2744                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2745                                 interrupt-names = "tx", "rx";
2746                                 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2747                                 dma-names = "tx", "rx";
2748                                 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2749                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2750                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2751                                 clock-names = "fck", "ahclkx", "ahclkr";
2752                                 status = "disabled";
2753                         };
2754                 };
2755
2756                 target-module@64000 {                   /* 0x48464000, ap 11 1e.0 */
2757                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2758                         reg = <0x64000 0x4>,
2759                               <0x64004 0x4>;
2760                         reg-names = "rev", "sysc";
2761                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2762                                         <SYSC_IDLE_NO>,
2763                                         <SYSC_IDLE_SMART>;
2764                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2765                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2766                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2767                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2768                         clock-names = "fck", "ahclkx", "ahclkr";
2769                         #address-cells = <1>;
2770                         #size-cells = <1>;
2771                         ranges = <0x0 0x64000 0x2000>,
2772                                  <0x45c00000 0x45c00000 0x400000>;
2773
2774                         mcasp2: mcasp@0 {
2775                                 compatible = "ti,dra7-mcasp-audio";
2776                                 reg = <0x0 0x2000>,
2777                                       <0x45c00000 0x1000>;      /* L3 data port */
2778                                 reg-names = "mpu","dat";
2779                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2780                                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2781                                 interrupt-names = "tx", "rx";
2782                                 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2783                                 dma-names = "tx", "rx";
2784                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2785                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2786                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2787                                 clock-names = "fck", "ahclkx", "ahclkr";
2788                                 status = "disabled";
2789                         };
2790                 };
2791
2792                 target-module@68000 {                   /* 0x48468000, ap 13 26.0 */
2793                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2794                         reg = <0x68000 0x4>,
2795                               <0x68004 0x4>;
2796                         reg-names = "rev", "sysc";
2797                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2798                                         <SYSC_IDLE_NO>,
2799                                         <SYSC_IDLE_SMART>;
2800                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2801                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2802                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2803                         clock-names = "fck", "ahclkx";
2804                         #address-cells = <1>;
2805                         #size-cells = <1>;
2806                         ranges = <0x0 0x68000 0x2000>,
2807                                  <0x46000000 0x46000000 0x400000>;
2808
2809                         mcasp3: mcasp@0 {
2810                                 compatible = "ti,dra7-mcasp-audio";
2811                                 reg = <0x0 0x2000>,
2812                                       <0x46000000 0x1000>;      /* L3 data port */
2813                                 reg-names = "mpu","dat";
2814                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2815                                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2816                                 interrupt-names = "tx", "rx";
2817                                 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2818                                 dma-names = "tx", "rx";
2819                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2820                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2821                                 clock-names = "fck", "ahclkx";
2822                                 status = "disabled";
2823                         };
2824                 };
2825
2826                 target-module@6c000 {                   /* 0x4846c000, ap 15 2e.0 */
2827                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2828                         reg = <0x6c000 0x4>,
2829                               <0x6c004 0x4>;
2830                         reg-names = "rev", "sysc";
2831                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2832                                         <SYSC_IDLE_NO>,
2833                                         <SYSC_IDLE_SMART>;
2834                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2835                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2836                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2837                         clock-names = "fck", "ahclkx";
2838                         #address-cells = <1>;
2839                         #size-cells = <1>;
2840                         ranges = <0x0 0x6c000 0x2000>,
2841                                  <0x48436000 0x48436000 0x400000>;
2842
2843                         mcasp4: mcasp@0 {
2844                                 compatible = "ti,dra7-mcasp-audio";
2845                                 reg = <0x0 0x2000>,
2846                                       <0x48436000 0x1000>;      /* L3 data port */
2847                                 reg-names = "mpu","dat";
2848                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2849                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2850                                 interrupt-names = "tx", "rx";
2851                                 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2852                                 dma-names = "tx", "rx";
2853                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2854                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2855                                 clock-names = "fck", "ahclkx";
2856                                 status = "disabled";
2857                         };
2858                 };
2859
2860                 target-module@70000 {                   /* 0x48470000, ap 19 36.0 */
2861                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2862                         reg = <0x70000 0x4>,
2863                               <0x70004 0x4>;
2864                         reg-names = "rev", "sysc";
2865                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2866                                         <SYSC_IDLE_NO>,
2867                                         <SYSC_IDLE_SMART>;
2868                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2869                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2870                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2871                         clock-names = "fck", "ahclkx";
2872                         #address-cells = <1>;
2873                         #size-cells = <1>;
2874                         ranges = <0x0 0x70000 0x2000>,
2875                                  <0x4843a000 0x4843a000 0x400000>;
2876
2877                         mcasp5: mcasp@0 {
2878                                 compatible = "ti,dra7-mcasp-audio";
2879                                 reg = <0x0 0x2000>,
2880                                       <0x4843a000 0x1000>;      /* L3 data port */
2881                                 reg-names = "mpu","dat";
2882                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2883                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2884                                 interrupt-names = "tx", "rx";
2885                                 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2886                                 dma-names = "tx", "rx";
2887                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2888                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2889                                 clock-names = "fck", "ahclkx";
2890                                 status = "disabled";
2891                         };
2892                 };
2893
2894                 target-module@74000 {                   /* 0x48474000, ap 35 14.0 */
2895                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2896                         reg = <0x74000 0x4>,
2897                               <0x74004 0x4>;
2898                         reg-names = "rev", "sysc";
2899                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2900                                         <SYSC_IDLE_NO>,
2901                                         <SYSC_IDLE_SMART>;
2902                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2903                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2904                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2905                         clock-names = "fck", "ahclkx";
2906                         #address-cells = <1>;
2907                         #size-cells = <1>;
2908                         ranges = <0x0 0x74000 0x2000>,
2909                                  <0x4844c000 0x4844c000 0x400000>;
2910
2911                         mcasp6: mcasp@0 {
2912                                 compatible = "ti,dra7-mcasp-audio";
2913                                 reg = <0x0 0x2000>,
2914                                       <0x4844c000 0x1000>;      /* L3 data port */
2915                                 reg-names = "mpu","dat";
2916                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2917                                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2918                                 interrupt-names = "tx", "rx";
2919                                 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2920                                 dma-names = "tx", "rx";
2921                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2922                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2923                                 clock-names = "fck", "ahclkx";
2924                                 status = "disabled";
2925                         };
2926                 };
2927
2928                 target-module@78000 {                   /* 0x48478000, ap 39 0c.0 */
2929                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2930                         reg = <0x78000 0x4>,
2931                               <0x78004 0x4>;
2932                         reg-names = "rev", "sysc";
2933                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2934                                         <SYSC_IDLE_NO>,
2935                                         <SYSC_IDLE_SMART>;
2936                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2937                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2938                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2939                         clock-names = "fck", "ahclkx";
2940                         #address-cells = <1>;
2941                         #size-cells = <1>;
2942                         ranges = <0x0 0x78000 0x2000>,
2943                                  <0x48450000 0x48450000 0x400000>;
2944
2945                         mcasp7: mcasp@0 {
2946                                 compatible = "ti,dra7-mcasp-audio";
2947                                 reg = <0x0 0x2000>,
2948                                       <0x48450000 0x1000>;      /* L3 data port */
2949                                 reg-names = "mpu","dat";
2950                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2951                                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2952                                 interrupt-names = "tx", "rx";
2953                                 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2954                                 dma-names = "tx", "rx";
2955                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2956                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2957                                 clock-names = "fck", "ahclkx";
2958                                 status = "disabled";
2959                         };
2960                 };
2961
2962                 target-module@7c000 {                   /* 0x4847c000, ap 43 04.0 */
2963                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2964                         reg = <0x7c000 0x4>,
2965                               <0x7c004 0x4>;
2966                         reg-names = "rev", "sysc";
2967                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2968                                         <SYSC_IDLE_NO>,
2969                                         <SYSC_IDLE_SMART>;
2970                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2971                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2972                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2973                         clock-names = "fck", "ahclkx";
2974                         #address-cells = <1>;
2975                         #size-cells = <1>;
2976                         ranges = <0x0 0x7c000 0x2000>,
2977                                  <0x48454000 0x48454000 0x400000>;
2978
2979                         mcasp8: mcasp@0 {
2980                                 compatible = "ti,dra7-mcasp-audio";
2981                                 reg = <0x0 0x2000>,
2982                                       <0x48454000 0x1000>;      /* L3 data port */
2983                                 reg-names = "mpu","dat";
2984                                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2985                                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2986                                 interrupt-names = "tx", "rx";
2987                                 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2988                                 dma-names = "tx", "rx";
2989                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2990                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2991                                 clock-names = "fck", "ahclkx";
2992                                 status = "disabled";
2993                         };
2994                 };
2995
2996                 target-module@80000 {                   /* 0x48480000, ap 31 16.0 */
2997                         compatible = "ti,sysc-omap4", "ti,sysc";
2998                         reg = <0x80020 0x4>;
2999                         reg-names = "rev";
3000                         clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3001                         clock-names = "fck";
3002                         #address-cells = <1>;
3003                         #size-cells = <1>;
3004                         ranges = <0x0 0x80000 0x2000>;
3005
3006                         dcan2: can@0 {
3007                                 compatible = "ti,dra7-d_can";
3008                                 reg = <0x0 0x2000>;
3009                                 syscon-raminit = <&scm_conf 0x558 1>;
3010                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
3011                                 clocks = <&sys_clkin1>;
3012                                 status = "disabled";
3013                         };
3014                 };
3015
3016                 target-module@84000 {                   /* 0x48484000, ap 3 10.0 */
3017                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3018                         reg = <0x85200 0x4>,
3019                               <0x85208 0x4>,
3020                               <0x85204 0x4>;
3021                         reg-names = "rev", "sysc", "syss";
3022                         ti,sysc-mask = <0>;
3023                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
3024                                         <SYSC_IDLE_NO>;
3025                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3026                                         <SYSC_IDLE_NO>;
3027                         ti,syss-mask = <1>;
3028                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3029                         clock-names = "fck";
3030                         #address-cells = <1>;
3031                         #size-cells = <1>;
3032                         ranges = <0x0 0x84000 0x4000>;
3033                         /*
3034                          * Do not allow gating of cpsw clock as workaround
3035                          * for errata i877. Keeping internal clock disabled
3036                          * causes the device switching characteristics
3037                          * to degrade over time and eventually fail to meet
3038                          * the data manual delay time/skew specs.
3039                          */
3040                         ti,no-idle;
3041
3042                         mac: ethernet@0 {
3043                                 compatible = "ti,dra7-cpsw","ti,cpsw";
3044                                 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3045                                 clock-names = "fck", "cpts";
3046                                 cpdma_channels = <8>;
3047                                 ale_entries = <1024>;
3048                                 bd_ram_size = <0x2000>;
3049                                 mac_control = <0x20>;
3050                                 slaves = <2>;
3051                                 active_slave = <0>;
3052                                 cpts_clock_mult = <0x784CFE14>;
3053                                 cpts_clock_shift = <29>;
3054                                 reg = <0x0 0x1000
3055                                        0x1200 0x2e00>;
3056                                 #address-cells = <1>;
3057                                 #size-cells = <1>;
3058
3059                                 /*
3060                                  * rx_thresh_pend
3061                                  * rx_pend
3062                                  * tx_pend
3063                                  * misc_pend
3064                                  */
3065                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3066                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3067                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3068                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3069                                 ranges = <0 0 0x4000>;
3070                                 syscon = <&scm_conf>;
3071                                 status = "disabled";
3072
3073                                 davinci_mdio: mdio@1000 {
3074                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3075                                         clocks = <&gmac_main_clk>;
3076                                         clock-names = "fck";
3077                                         #address-cells = <1>;
3078                                         #size-cells = <0>;
3079                                         bus_freq = <1000000>;
3080                                         reg = <0x1000 0x100>;
3081                                 };
3082
3083                                 cpsw_emac0: slave@200 {
3084                                         /* Filled in by U-Boot */
3085                                         mac-address = [ 00 00 00 00 00 00 ];
3086                                         phys = <&phy_gmii_sel 1>;
3087                                 };
3088
3089                                 cpsw_emac1: slave@300 {
3090                                         /* Filled in by U-Boot */
3091                                         mac-address = [ 00 00 00 00 00 00 ];
3092                                         phys = <&phy_gmii_sel 2>;
3093                                 };
3094                         };
3095
3096                         mac_sw: switch@0 {
3097                                 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
3098                                 reg = <0x0 0x4000>;
3099                                 ranges = <0 0 0x4000>;
3100                                 clocks = <&gmac_main_clk>;
3101                                 clock-names = "fck";
3102                                 #address-cells = <1>;
3103                                 #size-cells = <1>;
3104                                 syscon = <&scm_conf>;
3105                                 status = "disabled";
3106
3107                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3108                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3109                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3110                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3111                                 interrupt-names = "rx_thresh", "rx", "tx", "misc";
3112
3113                                 ethernet-ports {
3114                                         #address-cells = <1>;
3115                                         #size-cells = <0>;
3116
3117                                         cpsw_port1: port@1 {
3118                                                 reg = <1>;
3119                                                 label = "port1";
3120                                                 mac-address = [ 00 00 00 00 00 00 ];
3121                                                 phys = <&phy_gmii_sel 1>;
3122                                         };
3123
3124                                         cpsw_port2: port@2 {
3125                                                 reg = <2>;
3126                                                 label = "port2";
3127                                                 mac-address = [ 00 00 00 00 00 00 ];
3128                                                 phys = <&phy_gmii_sel 2>;
3129                                         };
3130                                 };
3131
3132                                 davinci_mdio_sw: mdio@1000 {
3133                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3134                                         clocks = <&gmac_main_clk>;
3135                                         clock-names = "fck";
3136                                         #address-cells = <1>;
3137                                         #size-cells = <0>;
3138                                         bus_freq = <1000000>;
3139                                         reg = <0x1000 0x100>;
3140                                 };
3141
3142                                 cpts {
3143                                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3144                                         clock-names = "cpts";
3145                                 };
3146                         };
3147                 };
3148         };
3149 };
3150
3151 &l4_per3 {                                              /* 0x48800000 */
3152         compatible = "ti,dra7-l4-per3", "simple-bus";
3153         reg = <0x48800000 0x800>,
3154               <0x48800800 0x800>,
3155               <0x48801000 0x400>,
3156               <0x48801400 0x400>,
3157               <0x48801800 0x400>;
3158         reg-names = "ap", "la", "ia0", "ia1", "ia2";
3159         #address-cells = <1>;
3160         #size-cells = <1>;
3161         ranges = <0x00000000 0x48800000 0x200000>;      /* segment 0 */
3162
3163         segment@0 {                                     /* 0x48800000 */
3164                 compatible = "simple-bus";
3165                 #address-cells = <1>;
3166                 #size-cells = <1>;
3167                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
3168                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
3169                          <0x00001000 0x00001000 0x000400>,      /* ap 2 */
3170                          <0x00001400 0x00001400 0x000400>,      /* ap 3 */
3171                          <0x00001800 0x00001800 0x000400>,      /* ap 4 */
3172                          <0x00020000 0x00020000 0x001000>,      /* ap 5 */
3173                          <0x00021000 0x00021000 0x001000>,      /* ap 6 */
3174                          <0x00022000 0x00022000 0x001000>,      /* ap 7 */
3175                          <0x00023000 0x00023000 0x001000>,      /* ap 8 */
3176                          <0x00024000 0x00024000 0x001000>,      /* ap 9 */
3177                          <0x00025000 0x00025000 0x001000>,      /* ap 10 */
3178                          <0x00026000 0x00026000 0x001000>,      /* ap 11 */
3179                          <0x00027000 0x00027000 0x001000>,      /* ap 12 */
3180                          <0x00028000 0x00028000 0x001000>,      /* ap 13 */
3181                          <0x00029000 0x00029000 0x001000>,      /* ap 14 */
3182                          <0x0002a000 0x0002a000 0x001000>,      /* ap 15 */
3183                          <0x0002b000 0x0002b000 0x001000>,      /* ap 16 */
3184                          <0x0002c000 0x0002c000 0x001000>,      /* ap 17 */
3185                          <0x0002d000 0x0002d000 0x001000>,      /* ap 18 */
3186                          <0x0002e000 0x0002e000 0x001000>,      /* ap 19 */
3187                          <0x0002f000 0x0002f000 0x001000>,      /* ap 20 */
3188                          <0x00170000 0x00170000 0x010000>,      /* ap 21 */
3189                          <0x00180000 0x00180000 0x001000>,      /* ap 22 */
3190                          <0x00190000 0x00190000 0x010000>,      /* ap 23 */
3191                          <0x001a0000 0x001a0000 0x001000>,      /* ap 24 */
3192                          <0x001b0000 0x001b0000 0x010000>,      /* ap 25 */
3193                          <0x001c0000 0x001c0000 0x001000>,      /* ap 26 */
3194                          <0x001d0000 0x001d0000 0x010000>,      /* ap 27 */
3195                          <0x001e0000 0x001e0000 0x001000>,      /* ap 28 */
3196                          <0x00038000 0x00038000 0x001000>,      /* ap 29 */
3197                          <0x00039000 0x00039000 0x001000>,      /* ap 30 */
3198                          <0x0005c000 0x0005c000 0x001000>,      /* ap 31 */
3199                          <0x0005d000 0x0005d000 0x001000>,      /* ap 32 */
3200                          <0x0003a000 0x0003a000 0x001000>,      /* ap 33 */
3201                          <0x0003b000 0x0003b000 0x001000>,      /* ap 34 */
3202                          <0x0003c000 0x0003c000 0x001000>,      /* ap 35 */
3203                          <0x0003d000 0x0003d000 0x001000>,      /* ap 36 */
3204                          <0x0003e000 0x0003e000 0x001000>,      /* ap 37 */
3205                          <0x0003f000 0x0003f000 0x001000>,      /* ap 38 */
3206                          <0x00040000 0x00040000 0x001000>,      /* ap 39 */
3207                          <0x00041000 0x00041000 0x001000>,      /* ap 40 */
3208                          <0x00042000 0x00042000 0x001000>,      /* ap 41 */
3209                          <0x00043000 0x00043000 0x001000>,      /* ap 42 */
3210                          <0x00044000 0x00044000 0x001000>,      /* ap 43 */
3211                          <0x00045000 0x00045000 0x001000>,      /* ap 44 */
3212                          <0x00046000 0x00046000 0x001000>,      /* ap 45 */
3213                          <0x00047000 0x00047000 0x001000>,      /* ap 46 */
3214                          <0x00048000 0x00048000 0x001000>,      /* ap 47 */
3215                          <0x00049000 0x00049000 0x001000>,      /* ap 48 */
3216                          <0x0004a000 0x0004a000 0x001000>,      /* ap 49 */
3217                          <0x0004b000 0x0004b000 0x001000>,      /* ap 50 */
3218                          <0x0004c000 0x0004c000 0x001000>,      /* ap 51 */
3219                          <0x0004d000 0x0004d000 0x001000>,      /* ap 52 */
3220                          <0x0004e000 0x0004e000 0x001000>,      /* ap 53 */
3221                          <0x0004f000 0x0004f000 0x001000>,      /* ap 54 */
3222                          <0x00050000 0x00050000 0x001000>,      /* ap 55 */
3223                          <0x00051000 0x00051000 0x001000>,      /* ap 56 */
3224                          <0x00052000 0x00052000 0x001000>,      /* ap 57 */
3225                          <0x00053000 0x00053000 0x001000>,      /* ap 58 */
3226                          <0x00054000 0x00054000 0x001000>,      /* ap 59 */
3227                          <0x00055000 0x00055000 0x001000>,      /* ap 60 */
3228                          <0x00056000 0x00056000 0x001000>,      /* ap 61 */
3229                          <0x00057000 0x00057000 0x001000>,      /* ap 62 */
3230                          <0x00058000 0x00058000 0x001000>,      /* ap 63 */
3231                          <0x00059000 0x00059000 0x001000>,      /* ap 64 */
3232                          <0x0005a000 0x0005a000 0x001000>,      /* ap 65 */
3233                          <0x0005b000 0x0005b000 0x001000>,      /* ap 66 */
3234                          <0x00064000 0x00064000 0x001000>,      /* ap 67 */
3235                          <0x00065000 0x00065000 0x001000>,      /* ap 68 */
3236                          <0x0005e000 0x0005e000 0x001000>,      /* ap 69 */
3237                          <0x0005f000 0x0005f000 0x001000>,      /* ap 70 */
3238                          <0x00060000 0x00060000 0x001000>,      /* ap 71 */
3239                          <0x00061000 0x00061000 0x001000>,      /* ap 72 */
3240                          <0x00062000 0x00062000 0x001000>,      /* ap 73 */
3241                          <0x00063000 0x00063000 0x001000>,      /* ap 74 */
3242                          <0x00140000 0x00140000 0x020000>,      /* ap 75 */
3243                          <0x00160000 0x00160000 0x001000>,      /* ap 76 */
3244                          <0x00016000 0x00016000 0x001000>,      /* ap 77 */
3245                          <0x00017000 0x00017000 0x001000>,      /* ap 78 */
3246                          <0x000c0000 0x000c0000 0x020000>,      /* ap 79 */
3247                          <0x000e0000 0x000e0000 0x001000>,      /* ap 80 */
3248                          <0x00004000 0x00004000 0x001000>,      /* ap 81 */
3249                          <0x00005000 0x00005000 0x001000>,      /* ap 82 */
3250                          <0x00080000 0x00080000 0x020000>,      /* ap 83 */
3251                          <0x000a0000 0x000a0000 0x001000>,      /* ap 84 */
3252                          <0x00100000 0x00100000 0x020000>,      /* ap 85 */
3253                          <0x00120000 0x00120000 0x001000>,      /* ap 86 */
3254                          <0x00010000 0x00010000 0x001000>,      /* ap 87 */
3255                          <0x00011000 0x00011000 0x001000>,      /* ap 88 */
3256                          <0x0000a000 0x0000a000 0x001000>,      /* ap 89 */
3257                          <0x0000b000 0x0000b000 0x001000>,      /* ap 90 */
3258                          <0x0001c000 0x0001c000 0x001000>,      /* ap 91 */
3259                          <0x0001d000 0x0001d000 0x001000>,      /* ap 92 */
3260                          <0x0001e000 0x0001e000 0x001000>,      /* ap 93 */
3261                          <0x0001f000 0x0001f000 0x001000>,      /* ap 94 */
3262                          <0x00002000 0x00002000 0x001000>,      /* ap 95 */
3263                          <0x00003000 0x00003000 0x001000>;      /* ap 96 */
3264
3265                 target-module@2000 {                    /* 0x48802000, ap 95 7c.0 */
3266                         compatible = "ti,sysc-omap4", "ti,sysc";
3267                         reg = <0x2000 0x4>,
3268                               <0x2010 0x4>;
3269                         reg-names = "rev", "sysc";
3270                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3271                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3272                                         <SYSC_IDLE_NO>,
3273                                         <SYSC_IDLE_SMART>;
3274                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3275                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3276                         clock-names = "fck";
3277                         #address-cells = <1>;
3278                         #size-cells = <1>;
3279                         ranges = <0x0 0x2000 0x1000>;
3280
3281                         mailbox13: mailbox@0 {
3282                                 compatible = "ti,omap4-mailbox";
3283                                 reg = <0x0 0x200>;
3284                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3285                                              <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3286                                              <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3287                                              <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3288                                 #mbox-cells = <1>;
3289                                 ti,mbox-num-users = <4>;
3290                                 ti,mbox-num-fifos = <12>;
3291                                 status = "disabled";
3292                         };
3293                 };
3294
3295                 target-module@4000 {                    /* 0x48804000, ap 81 20.0 */
3296                         compatible = "ti,sysc";
3297                         status = "disabled";
3298                         #address-cells = <1>;
3299                         #size-cells = <1>;
3300                         ranges = <0x0 0x4000 0x1000>;
3301                 };
3302
3303                 target-module@a000 {                    /* 0x4880a000, ap 89 18.0 */
3304                         compatible = "ti,sysc";
3305                         status = "disabled";
3306                         #address-cells = <1>;
3307                         #size-cells = <1>;
3308                         ranges = <0x0 0xa000 0x1000>;
3309                 };
3310
3311                 target-module@10000 {                   /* 0x48810000, ap 87 28.0 */
3312                         compatible = "ti,sysc";
3313                         status = "disabled";
3314                         #address-cells = <1>;
3315                         #size-cells = <1>;
3316                         ranges = <0x0 0x10000 0x1000>;
3317                 };
3318
3319                 target-module@16000 {                   /* 0x48816000, ap 77 1e.0 */
3320                         compatible = "ti,sysc";
3321                         status = "disabled";
3322                         #address-cells = <1>;
3323                         #size-cells = <1>;
3324                         ranges = <0x0 0x16000 0x1000>;
3325                 };
3326
3327                 target-module@1c000 {                   /* 0x4881c000, ap 91 1c.0 */
3328                         compatible = "ti,sysc";
3329                         status = "disabled";
3330                         #address-cells = <1>;
3331                         #size-cells = <1>;
3332                         ranges = <0x0 0x1c000 0x1000>;
3333                 };
3334
3335                 target-module@1e000 {                   /* 0x4881e000, ap 93 2c.0 */
3336                         compatible = "ti,sysc";
3337                         status = "disabled";
3338                         #address-cells = <1>;
3339                         #size-cells = <1>;
3340                         ranges = <0x0 0x1e000 0x1000>;
3341                 };
3342
3343                 target-module@20000 {                   /* 0x48820000, ap 5 08.0 */
3344                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3345                         reg = <0x20000 0x4>,
3346                               <0x20010 0x4>;
3347                         reg-names = "rev", "sysc";
3348                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3349                                          SYSC_OMAP4_SOFTRESET)>;
3350                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3351                                         <SYSC_IDLE_NO>,
3352                                         <SYSC_IDLE_SMART>,
3353                                         <SYSC_IDLE_SMART_WKUP>;
3354                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3355                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>, <&timer_sys_clk_div>;
3356                         clock-names = "fck", "timer_sys_ck";
3357                         #address-cells = <1>;
3358                         #size-cells = <1>;
3359                         ranges = <0x0 0x20000 0x1000>;
3360
3361                         timer5: timer@0 {
3362                                 compatible = "ti,omap5430-timer";
3363                                 reg = <0x0 0x80>;
3364                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
3365                                 clock-names = "fck";
3366                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3367                         };
3368                 };
3369
3370                 target-module@22000 {                   /* 0x48822000, ap 7 24.0 */
3371                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3372                         reg = <0x22000 0x4>,
3373                               <0x22010 0x4>;
3374                         reg-names = "rev", "sysc";
3375                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3376                                          SYSC_OMAP4_SOFTRESET)>;
3377                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3378                                         <SYSC_IDLE_NO>,
3379                                         <SYSC_IDLE_SMART>,
3380                                         <SYSC_IDLE_SMART_WKUP>;
3381                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3382                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>,
3383                                  <&timer_sys_clk_div>;
3384                         clock-names = "fck", "timer_sys_ck";
3385                         #address-cells = <1>;
3386                         #size-cells = <1>;
3387                         ranges = <0x0 0x22000 0x1000>;
3388
3389                         timer6: timer@0 {
3390                                 compatible = "ti,omap5430-timer";
3391                                 reg = <0x0 0x80>;
3392                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
3393                                 clock-names = "fck";
3394                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3395                         };
3396                 };
3397
3398                 target-module@24000 {                   /* 0x48824000, ap 9 26.0 */
3399                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3400                         reg = <0x24000 0x4>,
3401                               <0x24010 0x4>;
3402                         reg-names = "rev", "sysc";
3403                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3404                                          SYSC_OMAP4_SOFTRESET)>;
3405                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3406                                         <SYSC_IDLE_NO>,
3407                                         <SYSC_IDLE_SMART>,
3408                                         <SYSC_IDLE_SMART_WKUP>;
3409                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3410                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3411                         clock-names = "fck";
3412                         #address-cells = <1>;
3413                         #size-cells = <1>;
3414                         ranges = <0x0 0x24000 0x1000>;
3415
3416                         timer7: timer@0 {
3417                                 compatible = "ti,omap5430-timer";
3418                                 reg = <0x0 0x80>;
3419                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
3420                                 clock-names = "fck", "timer_sys_ck";
3421                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3422                         };
3423                 };
3424
3425                 target-module@26000 {                   /* 0x48826000, ap 11 0c.0 */
3426                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3427                         reg = <0x26000 0x4>,
3428                               <0x26010 0x4>;
3429                         reg-names = "rev", "sysc";
3430                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3431                                          SYSC_OMAP4_SOFTRESET)>;
3432                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3433                                         <SYSC_IDLE_NO>,
3434                                         <SYSC_IDLE_SMART>,
3435                                         <SYSC_IDLE_SMART_WKUP>;
3436                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3437                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3438                         clock-names = "fck";
3439                         #address-cells = <1>;
3440                         #size-cells = <1>;
3441                         ranges = <0x0 0x26000 0x1000>;
3442
3443                         timer8: timer@0 {
3444                                 compatible = "ti,omap5430-timer";
3445                                 reg = <0x0 0x80>;
3446                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;
3447                                 clock-names = "fck", "timer_sys_ck";
3448                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3449                         };
3450                 };
3451
3452                 target-module@28000 {                   /* 0x48828000, ap 13 16.0 */
3453                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3454                         reg = <0x28000 0x4>,
3455                               <0x28010 0x4>;
3456                         reg-names = "rev", "sysc";
3457                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3458                                          SYSC_OMAP4_SOFTRESET)>;
3459                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3460                                         <SYSC_IDLE_NO>,
3461                                         <SYSC_IDLE_SMART>,
3462                                         <SYSC_IDLE_SMART_WKUP>;
3463                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3464                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3465                         clock-names = "fck";
3466                         #address-cells = <1>;
3467                         #size-cells = <1>;
3468                         ranges = <0x0 0x28000 0x1000>;
3469
3470                         timer13: timer@0 {
3471                                 compatible = "ti,omap5430-timer";
3472                                 reg = <0x0 0x80>;
3473                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;
3474                                 clock-names = "fck", "timer_sys_ck";
3475                                 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3476                                 ti,timer-pwm;
3477                         };
3478                 };
3479
3480                 target-module@2a000 {                   /* 0x4882a000, ap 15 10.0 */
3481                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3482                         reg = <0x2a000 0x4>,
3483                               <0x2a010 0x4>;
3484                         reg-names = "rev", "sysc";
3485                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3486                                          SYSC_OMAP4_SOFTRESET)>;
3487                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3488                                         <SYSC_IDLE_NO>,
3489                                         <SYSC_IDLE_SMART>,
3490                                         <SYSC_IDLE_SMART_WKUP>;
3491                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3492                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3493                         clock-names = "fck";
3494                         #address-cells = <1>;
3495                         #size-cells = <1>;
3496                         ranges = <0x0 0x2a000 0x1000>;
3497
3498                         timer14: timer@0 {
3499                                 compatible = "ti,omap5430-timer";
3500                                 reg = <0x0 0x80>;
3501                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
3502                                 clock-names = "fck";
3503                                 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3504                                 ti,timer-pwm;
3505                         };
3506                 };
3507
3508                 target-module@2c000 {                   /* 0x4882c000, ap 17 02.0 */
3509                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3510                         reg = <0x2c000 0x4>,
3511                               <0x2c010 0x4>;
3512                         reg-names = "rev", "sysc";
3513                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3514                                          SYSC_OMAP4_SOFTRESET)>;
3515                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3516                                         <SYSC_IDLE_NO>,
3517                                         <SYSC_IDLE_SMART>,
3518                                         <SYSC_IDLE_SMART_WKUP>;
3519                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3520                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3521                         clock-names = "fck";
3522                         #address-cells = <1>;
3523                         #size-cells = <1>;
3524                         ranges = <0x0 0x2c000 0x1000>;
3525
3526                         timer15: timer@0 {
3527                                 compatible = "ti,omap5430-timer";
3528                                 reg = <0x0 0x80>;
3529                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
3530                                 clock-names = "fck";
3531                                 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3532                                 ti,timer-pwm;
3533                         };
3534                 };
3535
3536                 target-module@2e000 {                   /* 0x4882e000, ap 19 14.0 */
3537                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3538                         reg = <0x2e000 0x4>,
3539                               <0x2e010 0x4>;
3540                         reg-names = "rev", "sysc";
3541                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3542                                          SYSC_OMAP4_SOFTRESET)>;
3543                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3544                                         <SYSC_IDLE_NO>,
3545                                         <SYSC_IDLE_SMART>,
3546                                         <SYSC_IDLE_SMART_WKUP>;
3547                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3548                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3549                         clock-names = "fck";
3550                         #address-cells = <1>;
3551                         #size-cells = <1>;
3552                         ranges = <0x0 0x2e000 0x1000>;
3553
3554                         timer16: timer@0 {
3555                                 compatible = "ti,omap5430-timer";
3556                                 reg = <0x0 0x80>;
3557                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
3558                                 clock-names = "fck";
3559                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3560                                 ti,timer-pwm;
3561                         };
3562                 };
3563
3564                 rtctarget: target-module@38000 {                        /* 0x48838000, ap 29 12.0 */
3565                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3566                         ti,hwmods = "rtcss";
3567                         reg = <0x38074 0x4>,
3568                               <0x38078 0x4>;
3569                         reg-names = "rev", "sysc";
3570                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3571                                         <SYSC_IDLE_NO>,
3572                                         <SYSC_IDLE_SMART>,
3573                                         <SYSC_IDLE_SMART_WKUP>;
3574                         /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3575                         clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3576                         clock-names = "fck";
3577                         #address-cells = <1>;
3578                         #size-cells = <1>;
3579                         ranges = <0x0 0x38000 0x1000>;
3580
3581                         rtc: rtc@0 {
3582                                 compatible = "ti,am3352-rtc";
3583                                 reg = <0x0 0x100>;
3584                                 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3585                                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3586                                 clocks = <&sys_32k_ck>;
3587                         };
3588                 };
3589
3590                 target-module@3a000 {                   /* 0x4883a000, ap 33 3e.0 */
3591                         compatible = "ti,sysc-omap4", "ti,sysc";
3592                         reg = <0x3a000 0x4>,
3593                               <0x3a010 0x4>;
3594                         reg-names = "rev", "sysc";
3595                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3596                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3597                                         <SYSC_IDLE_NO>,
3598                                         <SYSC_IDLE_SMART>;
3599                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3600                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3601                         clock-names = "fck";
3602                         #address-cells = <1>;
3603                         #size-cells = <1>;
3604                         ranges = <0x0 0x3a000 0x1000>;
3605
3606                         mailbox2: mailbox@0 {
3607                                 compatible = "ti,omap4-mailbox";
3608                                 reg = <0x0 0x200>;
3609                                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3610                                              <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3611                                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3612                                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3613                                 #mbox-cells = <1>;
3614                                 ti,mbox-num-users = <4>;
3615                                 ti,mbox-num-fifos = <12>;
3616                                 status = "disabled";
3617                         };
3618                 };
3619
3620                 target-module@3c000 {                   /* 0x4883c000, ap 35 3a.0 */
3621                         compatible = "ti,sysc-omap4", "ti,sysc";
3622                         reg = <0x3c000 0x4>,
3623                               <0x3c010 0x4>;
3624                         reg-names = "rev", "sysc";
3625                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3626                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3627                                         <SYSC_IDLE_NO>,
3628                                         <SYSC_IDLE_SMART>;
3629                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3630                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3631                         clock-names = "fck";
3632                         #address-cells = <1>;
3633                         #size-cells = <1>;
3634                         ranges = <0x0 0x3c000 0x1000>;
3635
3636                         mailbox3: mailbox@0 {
3637                                 compatible = "ti,omap4-mailbox";
3638                                 reg = <0x0 0x200>;
3639                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3640                                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3641                                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3642                                              <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3643                                 #mbox-cells = <1>;
3644                                 ti,mbox-num-users = <4>;
3645                                 ti,mbox-num-fifos = <12>;
3646                                 status = "disabled";
3647                         };
3648                 };
3649
3650                 target-module@3e000 {                   /* 0x4883e000, ap 37 46.0 */
3651                         compatible = "ti,sysc-omap4", "ti,sysc";
3652                         reg = <0x3e000 0x4>,
3653                               <0x3e010 0x4>;
3654                         reg-names = "rev", "sysc";
3655                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3656                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3657                                         <SYSC_IDLE_NO>,
3658                                         <SYSC_IDLE_SMART>;
3659                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3660                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3661                         clock-names = "fck";
3662                         #address-cells = <1>;
3663                         #size-cells = <1>;
3664                         ranges = <0x0 0x3e000 0x1000>;
3665
3666                         mailbox4: mailbox@0 {
3667                                 compatible = "ti,omap4-mailbox";
3668                                 reg = <0x0 0x200>;
3669                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3670                                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3671                                              <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3672                                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3673                                 #mbox-cells = <1>;
3674                                 ti,mbox-num-users = <4>;
3675                                 ti,mbox-num-fifos = <12>;
3676                                 status = "disabled";
3677                         };
3678                 };
3679
3680                 target-module@40000 {                   /* 0x48840000, ap 39 64.0 */
3681                         compatible = "ti,sysc-omap4", "ti,sysc";
3682                         reg = <0x40000 0x4>,
3683                               <0x40010 0x4>;
3684                         reg-names = "rev", "sysc";
3685                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3686                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3687                                         <SYSC_IDLE_NO>,
3688                                         <SYSC_IDLE_SMART>;
3689                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3690                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3691                         clock-names = "fck";
3692                         #address-cells = <1>;
3693                         #size-cells = <1>;
3694                         ranges = <0x0 0x40000 0x1000>;
3695
3696                         mailbox5: mailbox@0 {
3697                                 compatible = "ti,omap4-mailbox";
3698                                 reg = <0x0 0x200>;
3699                                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3700                                              <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3701                                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3702                                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3703                                 #mbox-cells = <1>;
3704                                 ti,mbox-num-users = <4>;
3705                                 ti,mbox-num-fifos = <12>;
3706                                 status = "disabled";
3707                         };
3708                 };
3709
3710                 target-module@42000 {                   /* 0x48842000, ap 41 4e.0 */
3711                         compatible = "ti,sysc-omap4", "ti,sysc";
3712                         reg = <0x42000 0x4>,
3713                               <0x42010 0x4>;
3714                         reg-names = "rev", "sysc";
3715                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3716                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3717                                         <SYSC_IDLE_NO>,
3718                                         <SYSC_IDLE_SMART>;
3719                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3720                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3721                         clock-names = "fck";
3722                         #address-cells = <1>;
3723                         #size-cells = <1>;
3724                         ranges = <0x0 0x42000 0x1000>;
3725
3726                         mailbox6: mailbox@0 {
3727                                 compatible = "ti,omap4-mailbox";
3728                                 reg = <0x0 0x200>;
3729                                 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3730                                              <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3731                                              <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3732                                              <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3733                                 #mbox-cells = <1>;
3734                                 ti,mbox-num-users = <4>;
3735                                 ti,mbox-num-fifos = <12>;
3736                                 status = "disabled";
3737                         };
3738                 };
3739
3740                 target-module@44000 {                   /* 0x48844000, ap 43 42.0 */
3741                         compatible = "ti,sysc-omap4", "ti,sysc";
3742                         reg = <0x44000 0x4>,
3743                               <0x44010 0x4>;
3744                         reg-names = "rev", "sysc";
3745                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3746                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3747                                         <SYSC_IDLE_NO>,
3748                                         <SYSC_IDLE_SMART>;
3749                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3750                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3751                         clock-names = "fck";
3752                         #address-cells = <1>;
3753                         #size-cells = <1>;
3754                         ranges = <0x0 0x44000 0x1000>;
3755
3756                         mailbox7: mailbox@0 {
3757                                 compatible = "ti,omap4-mailbox";
3758                                 reg = <0x0 0x200>;
3759                                 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3760                                              <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3761                                              <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3762                                              <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3763                                 #mbox-cells = <1>;
3764                                 ti,mbox-num-users = <4>;
3765                                 ti,mbox-num-fifos = <12>;
3766                                 status = "disabled";
3767                         };
3768                 };
3769
3770                 target-module@46000 {                   /* 0x48846000, ap 45 48.0 */
3771                         compatible = "ti,sysc-omap4", "ti,sysc";
3772                         reg = <0x46000 0x4>,
3773                               <0x46010 0x4>;
3774                         reg-names = "rev", "sysc";
3775                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3776                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3777                                         <SYSC_IDLE_NO>,
3778                                         <SYSC_IDLE_SMART>;
3779                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3780                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3781                         clock-names = "fck";
3782                         #address-cells = <1>;
3783                         #size-cells = <1>;
3784                         ranges = <0x0 0x46000 0x1000>;
3785
3786                         mailbox8: mailbox@0 {
3787                                 compatible = "ti,omap4-mailbox";
3788                                 reg = <0x0 0x200>;
3789                                 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3790                                              <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3791                                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3792                                              <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3793                                 #mbox-cells = <1>;
3794                                 ti,mbox-num-users = <4>;
3795                                 ti,mbox-num-fifos = <12>;
3796                                 status = "disabled";
3797                         };
3798                 };
3799
3800                 target-module@48000 {                   /* 0x48848000, ap 47 36.0 */
3801                         compatible = "ti,sysc";
3802                         status = "disabled";
3803                         #address-cells = <1>;
3804                         #size-cells = <1>;
3805                         ranges = <0x0 0x48000 0x1000>;
3806                 };
3807
3808                 target-module@4a000 {                   /* 0x4884a000, ap 49 38.0 */
3809                         compatible = "ti,sysc";
3810                         status = "disabled";
3811                         #address-cells = <1>;
3812                         #size-cells = <1>;
3813                         ranges = <0x0 0x4a000 0x1000>;
3814                 };
3815
3816                 target-module@4c000 {                   /* 0x4884c000, ap 51 44.0 */
3817                         compatible = "ti,sysc";
3818                         status = "disabled";
3819                         #address-cells = <1>;
3820                         #size-cells = <1>;
3821                         ranges = <0x0 0x4c000 0x1000>;
3822                 };
3823
3824                 target-module@4e000 {                   /* 0x4884e000, ap 53 4c.0 */
3825                         compatible = "ti,sysc";
3826                         status = "disabled";
3827                         #address-cells = <1>;
3828                         #size-cells = <1>;
3829                         ranges = <0x0 0x4e000 0x1000>;
3830                 };
3831
3832                 target-module@50000 {                   /* 0x48850000, ap 55 40.0 */
3833                         compatible = "ti,sysc";
3834                         status = "disabled";
3835                         #address-cells = <1>;
3836                         #size-cells = <1>;
3837                         ranges = <0x0 0x50000 0x1000>;
3838                 };
3839
3840                 target-module@52000 {                   /* 0x48852000, ap 57 54.0 */
3841                         compatible = "ti,sysc";
3842                         status = "disabled";
3843                         #address-cells = <1>;
3844                         #size-cells = <1>;
3845                         ranges = <0x0 0x52000 0x1000>;
3846                 };
3847
3848                 target-module@54000 {                   /* 0x48854000, ap 59 1a.0 */
3849                         compatible = "ti,sysc";
3850                         status = "disabled";
3851                         #address-cells = <1>;
3852                         #size-cells = <1>;
3853                         ranges = <0x0 0x54000 0x1000>;
3854                 };
3855
3856                 target-module@56000 {                   /* 0x48856000, ap 61 22.0 */
3857                         compatible = "ti,sysc";
3858                         status = "disabled";
3859                         #address-cells = <1>;
3860                         #size-cells = <1>;
3861                         ranges = <0x0 0x56000 0x1000>;
3862                 };
3863
3864                 target-module@58000 {                   /* 0x48858000, ap 63 2a.0 */
3865                         compatible = "ti,sysc";
3866                         status = "disabled";
3867                         #address-cells = <1>;
3868                         #size-cells = <1>;
3869                         ranges = <0x0 0x58000 0x1000>;
3870                 };
3871
3872                 target-module@5a000 {                   /* 0x4885a000, ap 65 5c.0 */
3873                         compatible = "ti,sysc";
3874                         status = "disabled";
3875                         #address-cells = <1>;
3876                         #size-cells = <1>;
3877                         ranges = <0x0 0x5a000 0x1000>;
3878                 };
3879
3880                 target-module@5c000 {                   /* 0x4885c000, ap 31 32.0 */
3881                         compatible = "ti,sysc";
3882                         status = "disabled";
3883                         #address-cells = <1>;
3884                         #size-cells = <1>;
3885                         ranges = <0x0 0x5c000 0x1000>;
3886                 };
3887
3888                 target-module@5e000 {                   /* 0x4885e000, ap 69 6c.0 */
3889                         compatible = "ti,sysc-omap4", "ti,sysc";
3890                         reg = <0x5e000 0x4>,
3891                               <0x5e010 0x4>;
3892                         reg-names = "rev", "sysc";
3893                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3894                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3895                                         <SYSC_IDLE_NO>,
3896                                         <SYSC_IDLE_SMART>;
3897                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3898                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3899                         clock-names = "fck";
3900                         #address-cells = <1>;
3901                         #size-cells = <1>;
3902                         ranges = <0x0 0x5e000 0x1000>;
3903
3904                         mailbox9: mailbox@0 {
3905                                 compatible = "ti,omap4-mailbox";
3906                                 reg = <0x0 0x200>;
3907                                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3908                                              <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3909                                              <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3910                                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3911                                 #mbox-cells = <1>;
3912                                 ti,mbox-num-users = <4>;
3913                                 ti,mbox-num-fifos = <12>;
3914                                 status = "disabled";
3915                         };
3916                 };
3917
3918                 target-module@60000 {                   /* 0x48860000, ap 71 4a.0 */
3919                         compatible = "ti,sysc-omap4", "ti,sysc";
3920                         reg = <0x60000 0x4>,
3921                               <0x60010 0x4>;
3922                         reg-names = "rev", "sysc";
3923                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3924                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3925                                         <SYSC_IDLE_NO>,
3926                                         <SYSC_IDLE_SMART>;
3927                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3928                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3929                         clock-names = "fck";
3930                         #address-cells = <1>;
3931                         #size-cells = <1>;
3932                         ranges = <0x0 0x60000 0x1000>;
3933
3934                         mailbox10: mailbox@0 {
3935                                 compatible = "ti,omap4-mailbox";
3936                                 reg = <0x0 0x200>;
3937                                 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3938                                              <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3939                                              <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3940                                              <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3941                                 #mbox-cells = <1>;
3942                                 ti,mbox-num-users = <4>;
3943                                 ti,mbox-num-fifos = <12>;
3944                                 status = "disabled";
3945                         };
3946                 };
3947
3948                 target-module@62000 {                   /* 0x48862000, ap 73 74.0 */
3949                         compatible = "ti,sysc-omap4", "ti,sysc";
3950                         reg = <0x62000 0x4>,
3951                               <0x62010 0x4>;
3952                         reg-names = "rev", "sysc";
3953                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3954                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3955                                         <SYSC_IDLE_NO>,
3956                                         <SYSC_IDLE_SMART>;
3957                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3958                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3959                         clock-names = "fck";
3960                         #address-cells = <1>;
3961                         #size-cells = <1>;
3962                         ranges = <0x0 0x62000 0x1000>;
3963
3964                         mailbox11: mailbox@0 {
3965                                 compatible = "ti,omap4-mailbox";
3966                                 reg = <0x0 0x200>;
3967                                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3968                                              <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3969                                              <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3970                                              <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3971                                 #mbox-cells = <1>;
3972                                 ti,mbox-num-users = <4>;
3973                                 ti,mbox-num-fifos = <12>;
3974                                 status = "disabled";
3975                         };
3976                 };
3977
3978                 target-module@64000 {                   /* 0x48864000, ap 67 52.0 */
3979                         compatible = "ti,sysc-omap4", "ti,sysc";
3980                         reg = <0x64000 0x4>,
3981                               <0x64010 0x4>;
3982                         reg-names = "rev", "sysc";
3983                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3984                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3985                                         <SYSC_IDLE_NO>,
3986                                         <SYSC_IDLE_SMART>;
3987                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3988                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3989                         clock-names = "fck";
3990                         #address-cells = <1>;
3991                         #size-cells = <1>;
3992                         ranges = <0x0 0x64000 0x1000>;
3993
3994                         mailbox12: mailbox@0 {
3995                                 compatible = "ti,omap4-mailbox";
3996                                 reg = <0x0 0x200>;
3997                                 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3998                                              <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3999                                              <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
4000                                              <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
4001                                 #mbox-cells = <1>;
4002                                 ti,mbox-num-users = <4>;
4003                                 ti,mbox-num-fifos = <12>;
4004                                 status = "disabled";
4005                         };
4006                 };
4007
4008                 target-module@80000 {                   /* 0x48880000, ap 83 0e.1 */
4009                         compatible = "ti,sysc-omap4", "ti,sysc";
4010                         ti,hwmods = "usb_otg_ss1";
4011                         reg = <0x80000 0x4>,
4012                               <0x80010 0x4>;
4013                         reg-names = "rev", "sysc";
4014                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4015                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4016                                         <SYSC_IDLE_NO>,
4017                                         <SYSC_IDLE_SMART>,
4018                                         <SYSC_IDLE_SMART_WKUP>;
4019                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4020                                         <SYSC_IDLE_NO>,
4021                                         <SYSC_IDLE_SMART>,
4022                                         <SYSC_IDLE_SMART_WKUP>;
4023                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4024                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
4025                         clock-names = "fck";
4026                         #address-cells = <1>;
4027                         #size-cells = <1>;
4028                         ranges = <0x0 0x80000 0x20000>;
4029
4030                         omap_dwc3_1: omap_dwc3_1@0 {
4031                                 compatible = "ti,dwc3";
4032                                 reg = <0x0 0x10000>;
4033                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4034                                 #address-cells = <1>;
4035                                 #size-cells = <1>;
4036                                 utmi-mode = <2>;
4037                                 ranges = <0 0 0x20000>;
4038
4039                                 usb1: usb@10000 {
4040                                         compatible = "snps,dwc3";
4041                                         reg = <0x10000 0x17000>;
4042                                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4043                                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4044                                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4045                                         interrupt-names = "peripheral",
4046                                                           "host",
4047                                                           "otg";
4048                                         phys = <&usb2_phy1>, <&usb3_phy1>;
4049                                         phy-names = "usb2-phy", "usb3-phy";
4050                                         maximum-speed = "super-speed";
4051                                         dr_mode = "otg";
4052                                         snps,dis_u3_susphy_quirk;
4053                                         snps,dis_u2_susphy_quirk;
4054                                 };
4055                         };
4056                 };
4057
4058                 target-module@c0000 {                   /* 0x488c0000, ap 79 06.0 */
4059                         compatible = "ti,sysc-omap4", "ti,sysc";
4060                         ti,hwmods = "usb_otg_ss2";
4061                         reg = <0xc0000 0x4>,
4062                               <0xc0010 0x4>;
4063                         reg-names = "rev", "sysc";
4064                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4065                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4066                                         <SYSC_IDLE_NO>,
4067                                         <SYSC_IDLE_SMART>,
4068                                         <SYSC_IDLE_SMART_WKUP>;
4069                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4070                                         <SYSC_IDLE_NO>,
4071                                         <SYSC_IDLE_SMART>,
4072                                         <SYSC_IDLE_SMART_WKUP>;
4073                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4074                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4075                         clock-names = "fck";
4076                         #address-cells = <1>;
4077                         #size-cells = <1>;
4078                         ranges = <0x0 0xc0000 0x20000>;
4079
4080                         omap_dwc3_2: omap_dwc3_2@0 {
4081                                 compatible = "ti,dwc3";
4082                                 reg = <0x0 0x10000>;
4083                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4084                                 #address-cells = <1>;
4085                                 #size-cells = <1>;
4086                                 utmi-mode = <2>;
4087                                 ranges = <0 0 0x20000>;
4088
4089                                 usb2: usb@10000 {
4090                                         compatible = "snps,dwc3";
4091                                         reg = <0x10000 0x17000>;
4092                                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4093                                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4094                                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4095                                         interrupt-names = "peripheral",
4096                                                           "host",
4097                                                           "otg";
4098                                         phys = <&usb2_phy2>;
4099                                         phy-names = "usb2-phy";
4100                                         maximum-speed = "high-speed";
4101                                         dr_mode = "otg";
4102                                         snps,dis_u3_susphy_quirk;
4103                                         snps,dis_u2_susphy_quirk;
4104                                         snps,dis_metastability_quirk;
4105                                 };
4106                         };
4107                 };
4108
4109                 usb3_tm: target-module@100000 {         /* 0x48900000, ap 85 04.0 */
4110                         compatible = "ti,sysc-omap4", "ti,sysc";
4111                         ti,hwmods = "usb_otg_ss3";
4112                         reg = <0x100000 0x4>,
4113                               <0x100010 0x4>;
4114                         reg-names = "rev", "sysc";
4115                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4116                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4117                                         <SYSC_IDLE_NO>,
4118                                         <SYSC_IDLE_SMART>,
4119                                         <SYSC_IDLE_SMART_WKUP>;
4120                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4121                                         <SYSC_IDLE_NO>,
4122                                         <SYSC_IDLE_SMART>,
4123                                         <SYSC_IDLE_SMART_WKUP>;
4124                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4125                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4126                         clock-names = "fck";
4127                         #address-cells = <1>;
4128                         #size-cells = <1>;
4129                         ranges = <0x0 0x100000 0x20000>;
4130
4131                         omap_dwc3_3: omap_dwc3_3@0 {
4132                                 compatible = "ti,dwc3";
4133                                 reg = <0x0 0x10000>;
4134                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4135                                 #address-cells = <1>;
4136                                 #size-cells = <1>;
4137                                 utmi-mode = <2>;
4138                                 ranges = <0 0 0x20000>;
4139                                 status = "disabled";
4140
4141                                 usb3: usb@10000 {
4142                                         compatible = "snps,dwc3";
4143                                         reg = <0x10000 0x17000>;
4144                                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4145                                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4146                                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4147                                         interrupt-names = "peripheral",
4148                                                           "host",
4149                                                           "otg";
4150                                         maximum-speed = "high-speed";
4151                                         dr_mode = "otg";
4152                                         snps,dis_u3_susphy_quirk;
4153                                         snps,dis_u2_susphy_quirk;
4154                                 };
4155                         };
4156                 };
4157
4158                 usb4_tm: target-module@140000 {         /* 0x48940000, ap 75 3c.0 */
4159                         compatible = "ti,sysc-omap4", "ti,sysc";
4160                         ti,hwmods = "usb_otg_ss4";
4161                         reg = <0x140000 0x4>,
4162                               <0x140010 0x4>;
4163                         reg-names = "rev", "sysc";
4164                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4165                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4166                                         <SYSC_IDLE_NO>,
4167                                         <SYSC_IDLE_SMART>,
4168                                         <SYSC_IDLE_SMART_WKUP>;
4169                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4170                                         <SYSC_IDLE_NO>,
4171                                         <SYSC_IDLE_SMART>,
4172                                         <SYSC_IDLE_SMART_WKUP>;
4173                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4174                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4175                         clock-names = "fck";
4176                         #address-cells = <1>;
4177                         #size-cells = <1>;
4178                         ranges = <0x0 0x140000 0x20000>;
4179                 };
4180
4181                 target-module@170000 {                  /* 0x48970000, ap 21 0a.0 */
4182                         compatible = "ti,sysc-omap4", "ti,sysc";
4183                         reg = <0x170010 0x4>;
4184                         reg-names = "sysc";
4185                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4186                                         <SYSC_IDLE_NO>,
4187                                         <SYSC_IDLE_SMART>;
4188                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4189                                         <SYSC_IDLE_NO>,
4190                                         <SYSC_IDLE_SMART>;
4191                         clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4192                         clock-names = "fck";
4193                         #address-cells = <1>;
4194                         #size-cells = <1>;
4195                         ranges = <0x0 0x170000 0x10000>;
4196                         status = "disabled";
4197                 };
4198
4199                 target-module@190000 {                  /* 0x48990000, ap 23 2e.0 */
4200                         compatible = "ti,sysc-omap4", "ti,sysc";
4201                         reg = <0x190010 0x4>;
4202                         reg-names = "sysc";
4203                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4204                                         <SYSC_IDLE_NO>,
4205                                         <SYSC_IDLE_SMART>;
4206                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4207                                         <SYSC_IDLE_NO>,
4208                                         <SYSC_IDLE_SMART>;
4209                         clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4210                         clock-names = "fck";
4211                         #address-cells = <1>;
4212                         #size-cells = <1>;
4213                         ranges = <0x0 0x190000 0x10000>;
4214                         status = "disabled";
4215                 };
4216
4217                 target-module@1b0000 {                  /* 0x489b0000, ap 25 34.0 */
4218                         compatible = "ti,sysc-omap4", "ti,sysc";
4219                         reg = <0x1b0000 0x4>,
4220                               <0x1b0010 0x4>;
4221                         reg-names = "rev", "sysc";
4222                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4223                                         <SYSC_IDLE_NO>,
4224                                         <SYSC_IDLE_SMART>;
4225                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4226                                         <SYSC_IDLE_NO>,
4227                                         <SYSC_IDLE_SMART>;
4228                         clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4229                         clock-names = "fck";
4230                         #address-cells = <1>;
4231                         #size-cells = <1>;
4232                         ranges = <0x0 0x1b0000 0x10000>;
4233                         status = "disabled";
4234                 };
4235
4236                 target-module@1d0010 {                  /* 0x489d0000, ap 27 30.0 */
4237                         compatible = "ti,sysc-omap4", "ti,sysc";
4238                         reg = <0x1d0010 0x4>;
4239                         reg-names = "sysc";
4240                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4241                                         <SYSC_IDLE_NO>,
4242                                         <SYSC_IDLE_SMART>;
4243                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4244                                         <SYSC_IDLE_NO>,
4245                                         <SYSC_IDLE_SMART>;
4246                         clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4247                         clock-names = "fck";
4248                         #address-cells = <1>;
4249                         #size-cells = <1>;
4250                         ranges = <0x0 0x1d0000 0x10000>;
4251
4252                         vpe: vpe@0 {
4253                                 compatible = "ti,dra7-vpe";
4254                                 reg = <0x0000 0x120>,
4255                                       <0x0700 0x80>,
4256                                       <0x5700 0x18>,
4257                                       <0xd000 0x400>;
4258                                 reg-names = "vpe_top",
4259                                             "sc",
4260                                             "csc",
4261                                             "vpdma";
4262                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
4263                         };
4264                 };
4265         };
4266 };
4267
4268 &l4_wkup {                                              /* 0x4ae00000 */
4269         compatible = "ti,dra7-l4-wkup", "simple-bus";
4270         reg = <0x4ae00000 0x800>,
4271               <0x4ae00800 0x800>,
4272               <0x4ae01000 0x1000>;
4273         reg-names = "ap", "la", "ia0";
4274         #address-cells = <1>;
4275         #size-cells = <1>;
4276         ranges = <0x00000000 0x4ae00000 0x010000>,      /* segment 0 */
4277                  <0x00010000 0x4ae10000 0x010000>,      /* segment 1 */
4278                  <0x00020000 0x4ae20000 0x010000>,      /* segment 2 */
4279                  <0x00030000 0x4ae30000 0x010000>;      /* segment 3 */
4280
4281         segment@0 {                                     /* 0x4ae00000 */
4282                 compatible = "simple-bus";
4283                 #address-cells = <1>;
4284                 #size-cells = <1>;
4285                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
4286                          <0x00001000 0x00001000 0x001000>,      /* ap 1 */
4287                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
4288                          <0x00006000 0x00006000 0x002000>,      /* ap 3 */
4289                          <0x00008000 0x00008000 0x001000>,      /* ap 4 */
4290                          <0x00004000 0x00004000 0x001000>,      /* ap 15 */
4291                          <0x00005000 0x00005000 0x001000>,      /* ap 16 */
4292                          <0x0000c000 0x0000c000 0x001000>,      /* ap 17 */
4293                          <0x0000d000 0x0000d000 0x001000>;      /* ap 18 */
4294
4295                 target-module@4000 {                    /* 0x4ae04000, ap 15 40.0 */
4296                         compatible = "ti,sysc-omap2", "ti,sysc";
4297                         reg = <0x4000 0x4>,
4298                               <0x4010 0x4>;
4299                         reg-names = "rev", "sysc";
4300                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4301                                         <SYSC_IDLE_NO>,
4302                                         <SYSC_IDLE_SMART>,
4303                                         <SYSC_IDLE_SMART_WKUP>;
4304                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4305                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4306                         clock-names = "fck";
4307                         #address-cells = <1>;
4308                         #size-cells = <1>;
4309                         ranges = <0x0 0x4000 0x1000>;
4310
4311                         counter32k: counter@0 {
4312                                 compatible = "ti,omap-counter32k";
4313                                 reg = <0x0 0x40>;
4314                         };
4315                 };
4316
4317                 target-module@6000 {                    /* 0x4ae06000, ap 3 10.0 */
4318                         compatible = "ti,sysc-omap4", "ti,sysc";
4319                         reg = <0x6000 0x4>;
4320                         reg-names = "rev";
4321                         #address-cells = <1>;
4322                         #size-cells = <1>;
4323                         ranges = <0x0 0x6000 0x2000>;
4324
4325                         prm: prm@0 {
4326                                 compatible = "ti,dra7-prm", "simple-bus";
4327                                 reg = <0 0x3000>;
4328                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4329                                 #address-cells = <1>;
4330                                 #size-cells = <1>;
4331                                 ranges = <0 0 0x3000>;
4332
4333                                 prm_clocks: clocks {
4334                                         #address-cells = <1>;
4335                                         #size-cells = <0>;
4336                                 };
4337
4338                                 prm_clockdomains: clockdomains {
4339                                 };
4340                         };
4341                 };
4342
4343                 target-module@c000 {                    /* 0x4ae0c000, ap 17 50.0 */
4344                         compatible = "ti,sysc-omap4", "ti,sysc";
4345                         reg = <0xc000 0x4>;
4346                         reg-names = "rev";
4347                         #address-cells = <1>;
4348                         #size-cells = <1>;
4349                         ranges = <0x0 0xc000 0x1000>;
4350
4351                         scm_wkup: scm_conf@0 {
4352                                 compatible = "syscon";
4353                                 reg = <0 0x1000>;
4354                         };
4355                 };
4356         };
4357
4358         segment@10000 {                                 /* 0x4ae10000 */
4359                 compatible = "simple-bus";
4360                 #address-cells = <1>;
4361                 #size-cells = <1>;
4362                 ranges = <0x00000000 0x00010000 0x001000>,      /* ap 5 */
4363                          <0x00001000 0x00011000 0x001000>,      /* ap 6 */
4364                          <0x00004000 0x00014000 0x001000>,      /* ap 7 */
4365                          <0x00005000 0x00015000 0x001000>,      /* ap 8 */
4366                          <0x00008000 0x00018000 0x001000>,      /* ap 9 */
4367                          <0x00009000 0x00019000 0x001000>,      /* ap 10 */
4368                          <0x0000c000 0x0001c000 0x001000>,      /* ap 11 */
4369                          <0x0000d000 0x0001d000 0x001000>;      /* ap 12 */
4370
4371                 target-module@0 {                       /* 0x4ae10000, ap 5 20.0 */
4372                         compatible = "ti,sysc-omap2", "ti,sysc";
4373                         reg = <0x0 0x4>,
4374                               <0x10 0x4>,
4375                               <0x114 0x4>;
4376                         reg-names = "rev", "sysc", "syss";
4377                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4378                                          SYSC_OMAP2_SOFTRESET |
4379                                          SYSC_OMAP2_AUTOIDLE)>;
4380                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4381                                         <SYSC_IDLE_NO>,
4382                                         <SYSC_IDLE_SMART>,
4383                                         <SYSC_IDLE_SMART_WKUP>;
4384                         ti,syss-mask = <1>;
4385                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4386                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4387                                  <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4388                         clock-names = "fck", "dbclk";
4389                         #address-cells = <1>;
4390                         #size-cells = <1>;
4391                         ranges = <0x0 0x0 0x1000>;
4392
4393                         gpio1: gpio@0 {
4394                                 compatible = "ti,omap4-gpio";
4395                                 reg = <0x0 0x200>;
4396                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4397                                 gpio-controller;
4398                                 #gpio-cells = <2>;
4399                                 interrupt-controller;
4400                                 #interrupt-cells = <2>;
4401                         };
4402                 };
4403
4404                 target-module@4000 {                    /* 0x4ae14000, ap 7 28.0 */
4405                         compatible = "ti,sysc-omap2", "ti,sysc";
4406                         reg = <0x4000 0x4>,
4407                               <0x4010 0x4>,
4408                               <0x4014 0x4>;
4409                         reg-names = "rev", "sysc", "syss";
4410                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4411                                          SYSC_OMAP2_SOFTRESET)>;
4412                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4413                                         <SYSC_IDLE_NO>,
4414                                         <SYSC_IDLE_SMART>,
4415                                         <SYSC_IDLE_SMART_WKUP>;
4416                         ti,syss-mask = <1>;
4417                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4418                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4419                         clock-names = "fck";
4420                         #address-cells = <1>;
4421                         #size-cells = <1>;
4422                         ranges = <0x0 0x4000 0x1000>;
4423
4424                         wdt2: wdt@0 {
4425                                 compatible = "ti,omap3-wdt";
4426                                 reg = <0x0 0x80>;
4427                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4428                         };
4429                 };
4430
4431                 timer1_target: target-module@8000 {     /* 0x4ae18000, ap 9 30.0 */
4432                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4433                         reg = <0x8000 0x4>,
4434                               <0x8010 0x4>;
4435                         reg-names = "rev", "sysc";
4436                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4437                                          SYSC_OMAP4_SOFTRESET)>;
4438                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4439                                         <SYSC_IDLE_NO>,
4440                                         <SYSC_IDLE_SMART>,
4441                                         <SYSC_IDLE_SMART_WKUP>;
4442                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4443                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4444                         clock-names = "fck";
4445                         #address-cells = <1>;
4446                         #size-cells = <1>;
4447                         ranges = <0x0 0x8000 0x1000>;
4448
4449                         timer1: timer@0 {
4450                                 compatible = "ti,omap5430-timer";
4451                                 reg = <0x0 0x80>;
4452                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4453                                 clock-names = "fck";
4454                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4455                                 ti,timer-alwon;
4456                         };
4457                 };
4458
4459                 target-module@c000 {                    /* 0x4ae1c000, ap 11 38.0 */
4460                         compatible = "ti,sysc";
4461                         status = "disabled";
4462                         #address-cells = <1>;
4463                         #size-cells = <1>;
4464                         ranges = <0x0 0xc000 0x1000>;
4465                 };
4466         };
4467
4468         segment@20000 {                                 /* 0x4ae20000 */
4469                 compatible = "simple-bus";
4470                 #address-cells = <1>;
4471                 #size-cells = <1>;
4472                 ranges = <0x00006000 0x00026000 0x001000>,      /* ap 13 */
4473                          <0x0000a000 0x0002a000 0x001000>,      /* ap 14 */
4474                          <0x00000000 0x00020000 0x001000>,      /* ap 19 */
4475                          <0x00001000 0x00021000 0x001000>,      /* ap 20 */
4476                          <0x00002000 0x00022000 0x001000>,      /* ap 21 */
4477                          <0x00003000 0x00023000 0x001000>,      /* ap 22 */
4478                          <0x00007000 0x00027000 0x000400>,      /* ap 23 */
4479                          <0x00008000 0x00028000 0x000800>,      /* ap 24 */
4480                          <0x00009000 0x00029000 0x000100>,      /* ap 25 */
4481                          <0x00008800 0x00028800 0x000200>,      /* ap 26 */
4482                          <0x00008a00 0x00028a00 0x000100>,      /* ap 27 */
4483                          <0x0000b000 0x0002b000 0x001000>,      /* ap 28 */
4484                          <0x0000c000 0x0002c000 0x001000>,      /* ap 29 */
4485                          <0x0000f000 0x0002f000 0x001000>;      /* ap 32 */
4486
4487                 target-module@0 {                       /* 0x4ae20000, ap 19 08.0 */
4488                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4489                         reg = <0x0 0x4>,
4490                               <0x10 0x4>;
4491                         reg-names = "rev", "sysc";
4492                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4493                                          SYSC_OMAP4_SOFTRESET)>;
4494                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4495                                         <SYSC_IDLE_NO>,
4496                                         <SYSC_IDLE_SMART>,
4497                                         <SYSC_IDLE_SMART_WKUP>;
4498                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4499                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4500                         clock-names = "fck";
4501                         #address-cells = <1>;
4502                         #size-cells = <1>;
4503                         ranges = <0x0 0x0 0x1000>;
4504
4505                         timer12: timer@0 {
4506                                 compatible = "ti,omap5430-timer";
4507                                 reg = <0x0 0x80>;
4508                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4509                                 ti,timer-alwon;
4510                                 ti,timer-secure;
4511                         };
4512                 };
4513
4514                 target-module@2000 {                    /* 0x4ae22000, ap 21 18.0 */
4515                         compatible = "ti,sysc";
4516                         status = "disabled";
4517                         #address-cells = <1>;
4518                         #size-cells = <1>;
4519                         ranges = <0x0 0x2000 0x1000>;
4520                 };
4521
4522                 target-module@6000 {                    /* 0x4ae26000, ap 13 48.0 */
4523                         compatible = "ti,sysc";
4524                         status = "disabled";
4525                         #address-cells = <1>;
4526                         #size-cells = <1>;
4527                         ranges = <0x00000000 0x00006000 0x00001000>,
4528                                  <0x00001000 0x00007000 0x00000400>,
4529                                  <0x00002000 0x00008000 0x00000800>,
4530                                  <0x00002800 0x00008800 0x00000200>,
4531                                  <0x00002a00 0x00008a00 0x00000100>,
4532                                  <0x00003000 0x00009000 0x00000100>;
4533                 };
4534
4535                 target-module@b000 {                    /* 0x4ae2b000, ap 28 02.0 */
4536                         compatible = "ti,sysc-omap2", "ti,sysc";
4537                         reg = <0xb050 0x4>,
4538                               <0xb054 0x4>,
4539                               <0xb058 0x4>;
4540                         reg-names = "rev", "sysc", "syss";
4541                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4542                                          SYSC_OMAP2_SOFTRESET |
4543                                          SYSC_OMAP2_AUTOIDLE)>;
4544                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4545                                         <SYSC_IDLE_NO>,
4546                                         <SYSC_IDLE_SMART>,
4547                                         <SYSC_IDLE_SMART_WKUP>;
4548                         ti,syss-mask = <1>;
4549                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4550                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4551                         clock-names = "fck";
4552                         #address-cells = <1>;
4553                         #size-cells = <1>;
4554                         ranges = <0x0 0xb000 0x1000>;
4555
4556                         uart10: serial@0 {
4557                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
4558                                 reg = <0x0 0x100>;
4559                                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4560                                 clock-frequency = <48000000>;
4561                                 status = "disabled";
4562                         };
4563                 };
4564
4565                 target-module@f000 {                    /* 0x4ae2f000, ap 32 58.0 */
4566                         compatible = "ti,sysc";
4567                         status = "disabled";
4568                         #address-cells = <1>;
4569                         #size-cells = <1>;
4570                         ranges = <0x0 0xf000 0x1000>;
4571                 };
4572         };
4573
4574         segment@30000 {                                 /* 0x4ae30000 */
4575                 compatible = "simple-bus";
4576                 #address-cells = <1>;
4577                 #size-cells = <1>;
4578                 ranges = <0x0000c000 0x0003c000 0x002000>,      /* ap 30 */
4579                          <0x0000e000 0x0003e000 0x001000>,      /* ap 31 */
4580                          <0x00000000 0x00030000 0x001000>,      /* ap 33 */
4581                          <0x00001000 0x00031000 0x001000>,      /* ap 34 */
4582                          <0x00002000 0x00032000 0x001000>,      /* ap 35 */
4583                          <0x00003000 0x00033000 0x001000>,      /* ap 36 */
4584                          <0x00004000 0x00034000 0x001000>,      /* ap 37 */
4585                          <0x00005000 0x00035000 0x001000>,      /* ap 38 */
4586                          <0x00006000 0x00036000 0x001000>,      /* ap 39 */
4587                          <0x00007000 0x00037000 0x001000>,      /* ap 40 */
4588                          <0x00008000 0x00038000 0x001000>,      /* ap 41 */
4589                          <0x00009000 0x00039000 0x001000>,      /* ap 42 */
4590                          <0x0000a000 0x0003a000 0x001000>;      /* ap 43 */
4591
4592                 target-module@1000 {                    /* 0x4ae31000, ap 34 60.0 */
4593                         compatible = "ti,sysc";
4594                         status = "disabled";
4595                         #address-cells = <1>;
4596                         #size-cells = <1>;
4597                         ranges = <0x0 0x1000 0x1000>;
4598                 };
4599
4600                 target-module@3000 {                    /* 0x4ae33000, ap 36 0a.0 */
4601                         compatible = "ti,sysc";
4602                         status = "disabled";
4603                         #address-cells = <1>;
4604                         #size-cells = <1>;
4605                         ranges = <0x0 0x3000 0x1000>;
4606                 };
4607
4608                 target-module@5000 {                    /* 0x4ae35000, ap 38 0c.0 */
4609                         compatible = "ti,sysc";
4610                         status = "disabled";
4611                         #address-cells = <1>;
4612                         #size-cells = <1>;
4613                         ranges = <0x0 0x5000 0x1000>;
4614                 };
4615
4616                 target-module@7000 {                    /* 0x4ae37000, ap 40 68.0 */
4617                         compatible = "ti,sysc";
4618                         status = "disabled";
4619                         #address-cells = <1>;
4620                         #size-cells = <1>;
4621                         ranges = <0x0 0x7000 0x1000>;
4622                 };
4623
4624                 target-module@9000 {                    /* 0x4ae39000, ap 42 70.0 */
4625                         compatible = "ti,sysc";
4626                         status = "disabled";
4627                         #address-cells = <1>;
4628                         #size-cells = <1>;
4629                         ranges = <0x0 0x9000 0x1000>;
4630                 };
4631
4632                 target-module@c000 {                    /* 0x4ae3c000, ap 30 04.0 */
4633                         compatible = "ti,sysc-omap4", "ti,sysc";
4634                         reg = <0xc020 0x4>;
4635                         reg-names = "rev";
4636                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4637                         clock-names = "fck";
4638                         #address-cells = <1>;
4639                         #size-cells = <1>;
4640                         ranges = <0x0 0xc000 0x2000>;
4641
4642                         dcan1: can@0 {
4643                                 compatible = "ti,dra7-d_can";
4644                                 reg = <0x0 0x2000>;
4645                                 syscon-raminit = <&scm_conf 0x558 0>;
4646                                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4647                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4648                                 status = "disabled";
4649                         };
4650                 };
4651         };
4652 };
4653