1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
11 /memreserve/ 0x00000000 0x00001000;
13 /* This include file covers the common peripherals and configuration between
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
19 compatible = "brcm,bcm2835";
30 stdout-path = "serial0:115200n8";
33 rmem: reserved-memory {
39 compatible = "shared-dma-pool";
40 size = <0x4000000>; /* 64MB */
47 cpu_thermal: cpu-thermal {
48 polling-delay-passive = <0>;
49 polling-delay = <1000>;
53 temperature = <90000>;
65 compatible = "simple-bus";
69 system_timer: timer@7e003000 {
70 compatible = "brcm,bcm2835-system-timer";
71 reg = <0x7e003000 0x1000>;
72 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
73 /* This could be a reference to BCM2835_CLOCK_TIMER,
74 * but we don't have the driver using the common clock
77 clock-frequency = <1000000>;
81 compatible = "brcm,bcm2835-txp";
82 reg = <0x7e004000 0x20>;
86 clocks: cprman@7e101000 {
87 compatible = "brcm,bcm2835-cprman";
89 reg = <0x7e101000 0x2000>;
91 /* CPRMAN derives almost everything from the
92 * platform's oscillator. However, the DSI
93 * pixel clocks come from the DSI analog PHY.
96 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
97 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
100 mailbox: mailbox@7e00b880 {
101 compatible = "brcm,bcm2835-mbox";
102 reg = <0x7e00b880 0x40>;
107 gpio: gpio@7e200000 {
108 compatible = "brcm,bcm2835-gpio";
109 reg = <0x7e200000 0xb4>;
111 * The GPIO IP block is designed for 3 banks of GPIOs.
112 * Each bank has a GPIO interrupt for itself.
113 * There is an overall "any bank" interrupt.
114 * In order, these are GIC interrupts 17, 18, 19, 20.
115 * Since the BCM2835 only has 2 banks, the 2nd bank
116 * interrupt output appears to be mirrored onto the
117 * 3rd bank's interrupt signal.
118 * So, a bank0 interrupt shows up on 17, 20, and
119 * a bank1 interrupt shows up on 18, 19, 20!
121 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
129 gpio-ranges = <&gpio 0 0 54>;
131 /* Defines common pin muxing groups
133 * While each pin can have its mux selected
134 * for various functions individually, some
135 * groups only make sense to switch to a
136 * particular function together.
138 dpi_gpio0: dpi_gpio0 {
139 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
140 12 13 14 15 16 17 18 19
141 20 21 22 23 24 25 26 27>;
142 brcm,function = <BCM2835_FSEL_ALT2>;
144 emmc_gpio22: emmc_gpio22 {
145 brcm,pins = <22 23 24 25 26 27>;
146 brcm,function = <BCM2835_FSEL_ALT3>;
148 emmc_gpio34: emmc_gpio34 {
149 brcm,pins = <34 35 36 37 38 39>;
150 brcm,function = <BCM2835_FSEL_ALT3>;
151 brcm,pull = <BCM2835_PUD_OFF
158 emmc_gpio48: emmc_gpio48 {
159 brcm,pins = <48 49 50 51 52 53>;
160 brcm,function = <BCM2835_FSEL_ALT3>;
163 gpclk0_gpio4: gpclk0_gpio4 {
165 brcm,function = <BCM2835_FSEL_ALT0>;
167 gpclk1_gpio5: gpclk1_gpio5 {
169 brcm,function = <BCM2835_FSEL_ALT0>;
171 gpclk1_gpio42: gpclk1_gpio42 {
173 brcm,function = <BCM2835_FSEL_ALT0>;
175 gpclk1_gpio44: gpclk1_gpio44 {
177 brcm,function = <BCM2835_FSEL_ALT0>;
179 gpclk2_gpio6: gpclk2_gpio6 {
181 brcm,function = <BCM2835_FSEL_ALT0>;
183 gpclk2_gpio43: gpclk2_gpio43 {
185 brcm,function = <BCM2835_FSEL_ALT0>;
186 brcm,pull = <BCM2835_PUD_OFF>;
189 i2c0_gpio0: i2c0_gpio0 {
191 brcm,function = <BCM2835_FSEL_ALT0>;
193 i2c0_gpio28: i2c0_gpio28 {
195 brcm,function = <BCM2835_FSEL_ALT0>;
197 i2c0_gpio44: i2c0_gpio44 {
199 brcm,function = <BCM2835_FSEL_ALT1>;
201 i2c1_gpio2: i2c1_gpio2 {
203 brcm,function = <BCM2835_FSEL_ALT0>;
205 i2c1_gpio44: i2c1_gpio44 {
207 brcm,function = <BCM2835_FSEL_ALT2>;
210 jtag_gpio22: jtag_gpio22 {
211 brcm,pins = <22 23 24 25 26 27>;
212 brcm,function = <BCM2835_FSEL_ALT4>;
215 pcm_gpio18: pcm_gpio18 {
216 brcm,pins = <18 19 20 21>;
217 brcm,function = <BCM2835_FSEL_ALT0>;
219 pcm_gpio28: pcm_gpio28 {
220 brcm,pins = <28 29 30 31>;
221 brcm,function = <BCM2835_FSEL_ALT2>;
224 sdhost_gpio48: sdhost_gpio48 {
225 brcm,pins = <48 49 50 51 52 53>;
226 brcm,function = <BCM2835_FSEL_ALT0>;
229 spi0_gpio7: spi0_gpio7 {
230 brcm,pins = <7 8 9 10 11>;
231 brcm,function = <BCM2835_FSEL_ALT0>;
233 spi0_gpio35: spi0_gpio35 {
234 brcm,pins = <35 36 37 38 39>;
235 brcm,function = <BCM2835_FSEL_ALT0>;
237 spi1_gpio16: spi1_gpio16 {
238 brcm,pins = <16 17 18 19 20 21>;
239 brcm,function = <BCM2835_FSEL_ALT4>;
241 spi2_gpio40: spi2_gpio40 {
242 brcm,pins = <40 41 42 43 44 45>;
243 brcm,function = <BCM2835_FSEL_ALT4>;
246 uart0_gpio14: uart0_gpio14 {
248 brcm,function = <BCM2835_FSEL_ALT0>;
250 /* Separate from the uart0_gpio14 group
251 * because it conflicts with spi1_gpio16, and
252 * people often run uart0 on the two pins
253 * without flow control.
255 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
257 brcm,function = <BCM2835_FSEL_ALT3>;
259 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
261 brcm,function = <BCM2835_FSEL_ALT3>;
262 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
264 uart0_gpio32: uart0_gpio32 {
266 brcm,function = <BCM2835_FSEL_ALT3>;
267 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
269 uart0_gpio36: uart0_gpio36 {
271 brcm,function = <BCM2835_FSEL_ALT2>;
273 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
275 brcm,function = <BCM2835_FSEL_ALT2>;
278 uart1_gpio14: uart1_gpio14 {
280 brcm,function = <BCM2835_FSEL_ALT5>;
282 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
284 brcm,function = <BCM2835_FSEL_ALT5>;
286 uart1_gpio32: uart1_gpio32 {
288 brcm,function = <BCM2835_FSEL_ALT5>;
290 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
292 brcm,function = <BCM2835_FSEL_ALT5>;
294 uart1_gpio40: uart1_gpio40 {
296 brcm,function = <BCM2835_FSEL_ALT5>;
298 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
300 brcm,function = <BCM2835_FSEL_ALT5>;
304 uart0: serial@7e201000 {
305 compatible = "arm,pl011", "arm,primecell";
306 reg = <0x7e201000 0x200>;
308 clocks = <&clocks BCM2835_CLOCK_UART>,
309 <&clocks BCM2835_CLOCK_VPU>;
310 clock-names = "uartclk", "apb_pclk";
311 arm,primecell-periphid = <0x00241011>;
314 sdhost: mmc@7e202000 {
315 compatible = "brcm,bcm2835-sdhost";
316 reg = <0x7e202000 0x100>;
318 clocks = <&clocks BCM2835_CLOCK_VPU>;
323 compatible = "brcm,bcm2835-i2s";
324 reg = <0x7e203000 0x24>;
325 clocks = <&clocks BCM2835_CLOCK_PCM>;
330 compatible = "brcm,bcm2835-spi";
331 reg = <0x7e204000 0x200>;
333 clocks = <&clocks BCM2835_CLOCK_VPU>;
334 #address-cells = <1>;
339 i2c0if: i2c@7e205000 {
340 compatible = "brcm,bcm2835-i2c";
341 reg = <0x7e205000 0x200>;
343 clocks = <&clocks BCM2835_CLOCK_VPU>;
344 #address-cells = <1>;
350 compatible = "i2c-mux-pinctrl";
351 #address-cells = <1>;
354 i2c-parent = <&i2c0if>;
356 pinctrl-names = "i2c0", "i2c_csi_dsi";
362 #address-cells = <1>;
368 #address-cells = <1>;
374 compatible = "brcm,bcm2835-dpi";
375 reg = <0x7e208000 0x8c>;
376 clocks = <&clocks BCM2835_CLOCK_VPU>,
377 <&clocks BCM2835_CLOCK_DPI>;
378 clock-names = "core", "pixel";
379 #address-cells = <1>;
385 compatible = "brcm,bcm2835-dsi0";
386 reg = <0x7e209000 0x78>;
388 #address-cells = <1>;
392 clocks = <&clocks BCM2835_PLLA_DSI0>,
393 <&clocks BCM2835_CLOCK_DSI0E>,
394 <&clocks BCM2835_CLOCK_DSI0P>;
395 clock-names = "phy", "escape", "pixel";
397 clock-output-names = "dsi0_byte",
405 compatible = "brcm,bcm2835-aux";
407 reg = <0x7e215000 0x8>;
408 clocks = <&clocks BCM2835_CLOCK_VPU>;
411 uart1: serial@7e215040 {
412 compatible = "brcm,bcm2835-aux-uart";
413 reg = <0x7e215040 0x40>;
415 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
420 compatible = "brcm,bcm2835-aux-spi";
421 reg = <0x7e215080 0x40>;
423 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
424 #address-cells = <1>;
430 compatible = "brcm,bcm2835-aux-spi";
431 reg = <0x7e2150c0 0x40>;
433 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
434 #address-cells = <1>;
440 compatible = "brcm,bcm2835-pwm";
441 reg = <0x7e20c000 0x28>;
442 clocks = <&clocks BCM2835_CLOCK_PWM>;
443 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
444 assigned-clock-rates = <10000000>;
449 sdhci: mmc@7e300000 {
450 compatible = "brcm,bcm2835-sdhci";
451 reg = <0x7e300000 0x100>;
453 clocks = <&clocks BCM2835_CLOCK_EMMC>;
458 compatible = "brcm,bcm2835-hvs";
459 reg = <0x7e400000 0x6000>;
464 compatible = "brcm,bcm2835-dsi1";
465 reg = <0x7e700000 0x8c>;
467 #address-cells = <1>;
471 clocks = <&clocks BCM2835_PLLD_DSI1>,
472 <&clocks BCM2835_CLOCK_DSI1E>,
473 <&clocks BCM2835_CLOCK_DSI1P>;
474 clock-names = "phy", "escape", "pixel";
476 clock-output-names = "dsi1_byte",
484 compatible = "brcm,bcm2835-i2c";
485 reg = <0x7e804000 0x1000>;
487 clocks = <&clocks BCM2835_CLOCK_VPU>;
488 #address-cells = <1>;
494 compatible = "brcm,bcm2835-usb";
495 reg = <0x7e980000 0x10000>;
497 #address-cells = <1>;
502 phy-names = "usb2-phy";
507 /* The oscillator is the root of the clock tree. */
509 compatible = "fixed-clock";
511 clock-output-names = "osc";
512 clock-frequency = <19200000>;
516 compatible = "fixed-clock";
518 clock-output-names = "otg";
519 clock-frequency = <480000000>;
524 compatible = "usb-nop-xceiv";