arch/arm/boot/dts/bcm2711.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "bcm283x.dtsi"
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/soc/bcm2835-pm.h>
   6
   7 / {
   8         compatible = "brcm,bcm2711";
   9
  10         #address-cells = <2>;
  11         #size-cells = <1>;
  12
  13         interrupt-parent = <&gicv2>;
  14
  15         vc4: gpu {
  16                 compatible = "brcm,bcm2711-vc5";
  17                 status = "disabled";
  18         };
  19
  20         clk_27MHz: clk-27M {
  21                 #clock-cells = <0>;
  22                 compatible = "fixed-clock";
  23                 clock-frequency = <27000000>;
  24                 clock-output-names = "27MHz-clock";
  25         };
  26
  27         clk_108MHz: clk-108M {
  28                 #clock-cells = <0>;
  29                 compatible = "fixed-clock";
  30                 clock-frequency = <108000000>;
  31                 clock-output-names = "108MHz-clock";
  32         };
  33
  34         soc {
  35                 /*
  36                  * Defined ranges:
  37                  *   Common BCM283x peripherals
  38                  *   BCM2711-specific peripherals
  39                  *   ARM-local peripherals
  40                  */
  41                 ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
  42                          <0x7c000000  0x0 0xfc000000  0x02000000>,
  43                          <0x40000000  0x0 0xff800000  0x00800000>;
  44                 /* Emulate a contiguous 30-bit address range for DMA */
  45                 dma-ranges = <0xc0000000  0x0 0x00000000  0x40000000>;
  46
  47                 /*
  48                  * This node is the provider for the enable-method for
  49                  * bringing up secondary cores.
  50                  */
  51                 local_intc: local_intc@40000000 {
  52                         compatible = "brcm,bcm2836-l1-intc";
  53                         reg = <0x40000000 0x100>;
  54                 };
  55
  56                 gicv2: interrupt-controller@40041000 {
  57                         interrupt-controller;
  58                         #interrupt-cells = <3>;
  59                         compatible = "arm,gic-400";
  60                         reg =   <0x40041000 0x1000>,
  61                                 <0x40042000 0x2000>,
  62                                 <0x40044000 0x2000>,
  63                                 <0x40046000 0x2000>;
  64                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
  65                                                  IRQ_TYPE_LEVEL_HIGH)>;
  66                 };
  67
  68                 avs_monitor: avs-monitor@7d5d2000 {
  69                         compatible = "brcm,bcm2711-avs-monitor",
  70                                      "syscon", "simple-mfd";
  71                         reg = <0x7d5d2000 0xf00>;
  72
  73                         thermal: thermal {
  74                                 compatible = "brcm,bcm2711-thermal";
  75                                 #thermal-sensor-cells = <0>;
  76                         };
  77                 };
  78
  79                 dma: dma@7e007000 {
  80                         compatible = "brcm,bcm2835-dma";
  81                         reg = <0x7e007000 0xb00>;
  82                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
  89                                      /* DMA lite 7 - 10 */
  90                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  94                         interrupt-names = "dma0",
  95                                           "dma1",
  96                                           "dma2",
  97                                           "dma3",
  98                                           "dma4",
  99                                           "dma5",
 100                                           "dma6",
 101                                           "dma7",
 102                                           "dma8",
 103                                           "dma9",
 104                                           "dma10";
 105                         #dma-cells = <1>;
 106                         brcm,dma-channel-mask = <0x07f5>;
 107                 };
 108
 109                 pm: watchdog@7e100000 {
 110                         compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
 111                         #power-domain-cells = <1>;
 112                         #reset-cells = <1>;
 113                         reg = <0x7e100000 0x114>,
 114                               <0x7e00a000 0x24>,
 115                               <0x7ec11000 0x20>;
 116                         clocks = <&clocks BCM2835_CLOCK_V3D>,
 117                                  <&clocks BCM2835_CLOCK_PERI_IMAGE>,
 118                                  <&clocks BCM2835_CLOCK_H264>,
 119                                  <&clocks BCM2835_CLOCK_ISP>;
 120                         clock-names = "v3d", "peri_image", "h264", "isp";
 121                         system-power-controller;
 122                 };
 123
 124                 rng@7e104000 {
 125                         compatible = "brcm,bcm2711-rng200";
 126                         reg = <0x7e104000 0x28>;
 127                 };
 128
 129                 uart2: serial@7e201400 {
 130                         compatible = "arm,pl011", "arm,primecell";
 131                         reg = <0x7e201400 0x200>;
 132                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 133                         clocks = <&clocks BCM2835_CLOCK_UART>,
 134                                  <&clocks BCM2835_CLOCK_VPU>;
 135                         clock-names = "uartclk", "apb_pclk";
 136                         arm,primecell-periphid = <0x00241011>;
 137                         status = "disabled";
 138                 };
 139
 140                 uart3: serial@7e201600 {
 141                         compatible = "arm,pl011", "arm,primecell";
 142                         reg = <0x7e201600 0x200>;
 143                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&clocks BCM2835_CLOCK_UART>,
 145                                  <&clocks BCM2835_CLOCK_VPU>;
 146                         clock-names = "uartclk", "apb_pclk";
 147                         arm,primecell-periphid = <0x00241011>;
 148                         status = "disabled";
 149                 };
 150
 151                 uart4: serial@7e201800 {
 152                         compatible = "arm,pl011", "arm,primecell";
 153                         reg = <0x7e201800 0x200>;
 154                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&clocks BCM2835_CLOCK_UART>,
 156                                  <&clocks BCM2835_CLOCK_VPU>;
 157                         clock-names = "uartclk", "apb_pclk";
 158                         arm,primecell-periphid = <0x00241011>;
 159                         status = "disabled";
 160                 };
 161
 162                 uart5: serial@7e201a00 {
 163                         compatible = "arm,pl011", "arm,primecell";
 164                         reg = <0x7e201a00 0x200>;
 165                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 166                         clocks = <&clocks BCM2835_CLOCK_UART>,
 167                                  <&clocks BCM2835_CLOCK_VPU>;
 168                         clock-names = "uartclk", "apb_pclk";
 169                         arm,primecell-periphid = <0x00241011>;
 170                         status = "disabled";
 171                 };
 172
 173                 spi3: spi@7e204600 {
 174                         compatible = "brcm,bcm2835-spi";
 175                         reg = <0x7e204600 0x0200>;
 176                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 177                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         status = "disabled";
 181                 };
 182
 183                 spi4: spi@7e204800 {
 184                         compatible = "brcm,bcm2835-spi";
 185                         reg = <0x7e204800 0x0200>;
 186                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 187                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         status = "disabled";
 191                 };
 192
 193                 spi5: spi@7e204a00 {
 194                         compatible = "brcm,bcm2835-spi";
 195                         reg = <0x7e204a00 0x0200>;
 196                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 197                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                         status = "disabled";
 201                 };
 202
 203                 spi6: spi@7e204c00 {
 204                         compatible = "brcm,bcm2835-spi";
 205                         reg = <0x7e204c00 0x0200>;
 206                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         status = "disabled";
 211                 };
 212
 213                 i2c3: i2c@7e205600 {
 214                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 215                         reg = <0x7e205600 0x200>;
 216                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                         status = "disabled";
 221                 };
 222
 223                 i2c4: i2c@7e205800 {
 224                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 225                         reg = <0x7e205800 0x200>;
 226                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 227                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         status = "disabled";
 231                 };
 232
 233                 i2c5: i2c@7e205a00 {
 234                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 235                         reg = <0x7e205a00 0x200>;
 236                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 237                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241                 };
 242
 243                 i2c6: i2c@7e205c00 {
 244                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 245                         reg = <0x7e205c00 0x200>;
 246                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 247                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         status = "disabled";
 251                 };
 252
 253                 pixelvalve0: pixelvalve@7e206000 {
 254                         compatible = "brcm,bcm2711-pixelvalve0";
 255                         reg = <0x7e206000 0x100>;
 256                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 257                         status = "disabled";
 258                 };
 259
 260                 pixelvalve1: pixelvalve@7e207000 {
 261                         compatible = "brcm,bcm2711-pixelvalve1";
 262                         reg = <0x7e207000 0x100>;
 263                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 264                         status = "disabled";
 265                 };
 266
 267                 pixelvalve2: pixelvalve@7e20a000 {
 268                         compatible = "brcm,bcm2711-pixelvalve2";
 269                         reg = <0x7e20a000 0x100>;
 270                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 271                         status = "disabled";
 272                 };
 273
 274                 pwm1: pwm@7e20c800 {
 275                         compatible = "brcm,bcm2835-pwm";
 276                         reg = <0x7e20c800 0x28>;
 277                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 278                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 279                         assigned-clock-rates = <10000000>;
 280                         #pwm-cells = <2>;
 281                         status = "disabled";
 282                 };
 283
 284                 pixelvalve4: pixelvalve@7e216000 {
 285                         compatible = "brcm,bcm2711-pixelvalve4";
 286                         reg = <0x7e216000 0x100>;
 287                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 288                         status = "disabled";
 289                 };
 290
 291                 hvs: hvs@7e400000 {
 292                         compatible = "brcm,bcm2711-hvs";
 293                         reg = <0x7e400000 0x8000>;
 294                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 295                 };
 296
 297                 pixelvalve3: pixelvalve@7ec12000 {
 298                         compatible = "brcm,bcm2711-pixelvalve3";
 299                         reg = <0x7ec12000 0x100>;
 300                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 301                         status = "disabled";
 302                 };
 303
 304                 vec: vec@7ec13000 {
 305                         compatible = "brcm,bcm2711-vec";
 306                         reg = <0x7ec13000 0x1000>;
 307                         clocks = <&firmware_clocks 15>;
 308                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 309                         status = "disabled";
 310                 };
 311
 312                 dvp: clock@7ef00000 {
 313                         compatible = "brcm,brcm2711-dvp";
 314                         reg = <0x7ef00000 0x10>;
 315                         clocks = <&clk_108MHz>;
 316                         #clock-cells = <1>;
 317                         #reset-cells = <1>;
 318                 };
 319
 320                 aon_intr: interrupt-controller@7ef00100 {
 321                         compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
 322                         reg = <0x7ef00100 0x30>;
 323                         interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
 324                         interrupt-controller;
 325                         #interrupt-cells = <1>;
 326                         status = "disabled";
 327                 };
 328
 329                 hdmi0: hdmi@7ef00700 {
 330                         compatible = "brcm,bcm2711-hdmi0";
 331                         reg = <0x7ef00700 0x300>,
 332                               <0x7ef00300 0x200>,
 333                               <0x7ef00f00 0x80>,
 334                               <0x7ef00f80 0x80>,
 335                               <0x7ef01b00 0x200>,
 336                               <0x7ef01f00 0x400>,
 337                               <0x7ef00200 0x80>,
 338                               <0x7ef04300 0x100>,
 339                               <0x7ef20000 0x100>,
 340                               <0x7ef00100 0x30>;
 341                         reg-names = "hdmi",
 342                                     "dvp",
 343                                     "phy",
 344                                     "rm",
 345                                     "packet",
 346                                     "metadata",
 347                                     "csc",
 348                                     "cec",
 349                                     "hd",
 350                                     "intr2";
 351                         clocks = <&firmware_clocks 13>,
 352                                  <&firmware_clocks 14>,
 353                                  <&dvp 0>,
 354                                  <&clk_27MHz>;
 355                         clock-names = "hdmi", "bvb", "audio", "cec";
 356                         resets = <&dvp 0>;
 357                         interrupt-parent = <&aon_intr>;
 358                         interrupts = <0>, <1>, <2>,
 359                                      <3>, <4>, <5>;
 360                         interrupt-names = "cec-tx", "cec-rx", "cec-low",
 361                                           "wakeup", "hpd-connected", "hpd-removed";
 362                         ddc = <&ddc0>;
 363                         dmas = <&dma (10 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>;
 364                         dma-names = "audio-rx";
 365                         status = "disabled";
 366                 };
 367
 368                 ddc0: i2c@7ef04500 {
 369                         compatible = "brcm,bcm2711-hdmi-i2c";
 370                         reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
 371                         reg-names = "bsc", "auto-i2c";
 372                         clock-frequency = <97500>;
 373                         status = "disabled";
 374                 };
 375
 376                 hdmi1: hdmi@7ef05700 {
 377                         compatible = "brcm,bcm2711-hdmi1";
 378                         reg = <0x7ef05700 0x300>,
 379                               <0x7ef05300 0x200>,
 380                               <0x7ef05f00 0x80>,
 381                               <0x7ef05f80 0x80>,
 382                               <0x7ef06b00 0x200>,
 383                               <0x7ef06f00 0x400>,
 384                               <0x7ef00280 0x80>,
 385                               <0x7ef09300 0x100>,
 386                               <0x7ef20000 0x100>,
 387                               <0x7ef00100 0x30>;
 388                         reg-names = "hdmi",
 389                                     "dvp",
 390                                     "phy",
 391                                     "rm",
 392                                     "packet",
 393                                     "metadata",
 394                                     "csc",
 395                                     "cec",
 396                                     "hd",
 397                                     "intr2";
 398                         ddc = <&ddc1>;
 399                         clock-names = "hdmi", "bvb", "audio", "cec";
 400                         clocks = <&firmware_clocks 13>,
 401                                  <&firmware_clocks 14>,
 402                                  <&dvp 0>,
 403                                  <&clk_27MHz>;
 404                         resets = <&dvp 1>;
 405                         interrupt-parent = <&aon_intr>;
 406                         interrupts = <8>, <7>, <6>,     // This is correct
 407                                      <9>, <10>, <11>;
 408                         interrupt-names = "cec-tx", "cec-rx", "cec-low",
 409                                           "wakeup", "hpd-connected", "hpd-removed";
 410                         dmas = <&dma (17 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>;
 411                         dma-names = "audio-rx";
 412                         status = "disabled";
 413                 };
 414
 415                 ddc1: i2c@7ef09500 {
 416                         compatible = "brcm,bcm2711-hdmi-i2c";
 417                         reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
 418                         reg-names = "bsc", "auto-i2c";
 419                         clock-frequency = <97500>;
 420                         status = "disabled";
 421                 };
 422         };
 423
 424         /*
 425          * emmc2 has different DMA constraints based on SoC revisions. It was
 426          * moved into its own bus, so as for RPi4's firmware to update them.
 427          * The firmware will find whether the emmc2bus alias is defined, and if
 428          * so, it'll edit the dma-ranges property below accordingly.
 429          */
 430         emmc2bus: emmc2bus {
 431                 compatible = "simple-bus";
 432                 #address-cells = <2>;
 433                 #size-cells = <1>;
 434
 435                 ranges = <0x0 0x7e000000  0x0 0xfe000000  0x01800000>;
 436                 dma-ranges = <0x0 0xc0000000  0x0 0x00000000  0x40000000>;
 437
 438                 emmc2: mmc@7e340000 {
 439                         compatible = "brcm,bcm2711-emmc2";
 440                         reg = <0x0 0x7e340000 0x100>;
 441                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&clocks BCM2711_CLOCK_EMMC2>;
 443                         status = "disabled";
 444                 };
 445         };
 446
 447         arm-pmu {
 448                 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3", "arm,cortex-a7-pmu";
 449                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 450                         <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 451                         <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 452                         <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 453                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 454         };
 455
 456         timer {
 457                 compatible = "arm,armv8-timer";
 458                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 459                                           IRQ_TYPE_LEVEL_LOW)>,
 460                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 461                                           IRQ_TYPE_LEVEL_LOW)>,
 462                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 463                                           IRQ_TYPE_LEVEL_LOW)>,
 464                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 465                                           IRQ_TYPE_LEVEL_LOW)>;
 466                 /* This only applies to the ARMv7 stub */
 467                 arm,cpu-registers-not-fw-configured;
 468         };
 469
 470         cpus: cpus {
 471                 #address-cells = <1>;
 472                 #size-cells = <0>;
 473                 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 474
 475                 /* Source for d/i-cache-line-size and d/i-cache-sets
 476                  * https://developer.arm.com/documentation/100095/0003
 477                  * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
 478                  * Source for d/i-cache-size
 479                  * https://www.raspberrypi.com/documentation/computers
 480                  * /processors.html#bcm2711
 481                  */
 482                 cpu0: cpu@0 {
 483                         device_type = "cpu";
 484                         compatible = "arm,cortex-a72";
 485                         reg = <0>;
 486                         enable-method = "spin-table";
 487                         cpu-release-addr = <0x0 0x000000d8>;
 488                         d-cache-size = <0x8000>;
 489                         d-cache-line-size = <64>;
 490                         d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
 491                         i-cache-size = <0xc000>;
 492                         i-cache-line-size = <64>;
 493                         i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
 494                         next-level-cache = <&l2>;
 495                 };
 496
 497                 cpu1: cpu@1 {
 498                         device_type = "cpu";
 499                         compatible = "arm,cortex-a72";
 500                         reg = <1>;
 501                         enable-method = "spin-table";
 502                         cpu-release-addr = <0x0 0x000000e0>;
 503                         d-cache-size = <0x8000>;
 504                         d-cache-line-size = <64>;
 505                         d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
 506                         i-cache-size = <0xc000>;
 507                         i-cache-line-size = <64>;
 508                         i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
 509                         next-level-cache = <&l2>;
 510                 };
 511
 512                 cpu2: cpu@2 {
 513                         device_type = "cpu";
 514                         compatible = "arm,cortex-a72";
 515                         reg = <2>;
 516                         enable-method = "spin-table";
 517                         cpu-release-addr = <0x0 0x000000e8>;
 518                         d-cache-size = <0x8000>;
 519                         d-cache-line-size = <64>;
 520                         d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
 521                         i-cache-size = <0xc000>;
 522                         i-cache-line-size = <64>;
 523                         i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
 524                         next-level-cache = <&l2>;
 525                 };
 526
 527                 cpu3: cpu@3 {
 528                         device_type = "cpu";
 529                         compatible = "arm,cortex-a72";
 530                         reg = <3>;
 531                         enable-method = "spin-table";
 532                         cpu-release-addr = <0x0 0x000000f0>;
 533                         d-cache-size = <0x8000>;
 534                         d-cache-line-size = <64>;
 535                         d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
 536                         i-cache-size = <0xc000>;
 537                         i-cache-line-size = <64>;
 538                         i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
 539                         next-level-cache = <&l2>;
 540                 };
 541
 542                 /* Source for d/i-cache-line-size and d/i-cache-sets
 543                  *  https://developer.arm.com/documentation/100095/0003
 544                  *  /Level-2-Memory-System/About-the-L2-memory-system?lang=en
 545                  *  Source for d/i-cache-size
 546                  *  https://www.raspberrypi.com/documentation/computers
 547                  *  /processors.html#bcm2711
 548                  */
 549                 l2: l2-cache0 {
 550                         compatible = "cache";
 551                         cache-size = <0x100000>;
 552                         cache-line-size = <64>;
 553                         cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
 554                         cache-level = <2>;
 555                 };
 556         };
 557
 558         scb {
 559                 compatible = "simple-bus";
 560                 #address-cells = <2>;
 561                 #size-cells = <2>;
 562
 563                 ranges = <0x0 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,
 564                          <0x6 0x00000000  0x6 0x00000000  0x0 0x40000000>;
 565
 566                 pcie0: pcie@7d500000 {
 567                         compatible = "brcm,bcm2711-pcie";
 568                         reg = <0x0 0x7d500000  0x0 0x9310>;
 569                         device_type = "pci";
 570                         #address-cells = <3>;
 571                         #interrupt-cells = <1>;
 572                         #size-cells = <2>;
 573                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 575                         interrupt-names = "pcie", "msi";
 576                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 577                         interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
 578                                                         IRQ_TYPE_LEVEL_HIGH>,
 579                                         <0 0 0 2 &gicv2 GIC_SPI 144
 580                                                         IRQ_TYPE_LEVEL_HIGH>,
 581                                         <0 0 0 3 &gicv2 GIC_SPI 145
 582                                                         IRQ_TYPE_LEVEL_HIGH>,
 583                                         <0 0 0 4 &gicv2 GIC_SPI 146
 584                                                         IRQ_TYPE_LEVEL_HIGH>;
 585                         msi-controller;
 586                         msi-parent = <&pcie0>;
 587
 588                         ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000
 589                                   0x0 0x40000000>;
 590                         /*
 591                          * The wrapper around the PCIe block has a bug
 592                          * preventing it from accessing beyond the first 3GB of
 593                          * memory.
 594                          */
 595                         dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
 596                                       0x0 0xc0000000>;
 597                         brcm,enable-ssc;
 598                 };
 599
 600                 genet: ethernet@7d580000 {
 601                         compatible = "brcm,bcm2711-genet-v5";
 602                         reg = <0x0 0x7d580000  0x0 0x10000>;
 603                         #address-cells = <0x1>;
 604                         #size-cells = <0x1>;
 605                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 606                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 607                         status = "disabled";
 608
 609                         genet_mdio: mdio@e14 {
 610                                 compatible = "brcm,genet-mdio-v5";
 611                                 reg = <0xe14 0x8>;
 612                                 reg-names = "mdio";
 613                                 #address-cells = <0x1>;
 614                                 #size-cells = <0x0>;
 615                         };
 616                 };
 617         };
 618 };
 619
 620 &clk_osc {
 621         clock-frequency = <54000000>;
 622 };
 623
 624 &clocks {
 625         compatible = "brcm,bcm2711-cprman";
 626 };
 627
 628 &cpu_thermal {
 629         coefficients = <(-487) 410040>;
 630         thermal-sensors = <&thermal>;
 631 };
 632
 633 &dsi0 {
 634         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 635 };
 636
 637 &dsi1 {
 638         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 639         compatible = "brcm,bcm2711-dsi1";
 640 };
 641
 642 &gpio {
 643         compatible = "brcm,bcm2711-gpio";
 644         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 645                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 646                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 647                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 648
 649         gpio-ranges = <&gpio 0 0 58>;
 650
 651         gpclk0_gpio49: gpclk0_gpio49 {
 652                 pin-gpclk {
 653                         pins = "gpio49";
 654                         function = "alt1";
 655                         bias-disable;
 656                 };
 657         };
 658         gpclk1_gpio50: gpclk1_gpio50 {
 659                 pin-gpclk {
 660                         pins = "gpio50";
 661                         function = "alt1";
 662                         bias-disable;
 663                 };
 664         };
 665         gpclk2_gpio51: gpclk2_gpio51 {
 666                 pin-gpclk {
 667                         pins = "gpio51";
 668                         function = "alt1";
 669                         bias-disable;
 670                 };
 671         };
 672
 673         i2c0_gpio46: i2c0_gpio46 {
 674                 pin-sda {
 675                         function = "alt0";
 676                         pins = "gpio46";
 677                         bias-pull-up;
 678                 };
 679                 pin-scl {
 680                         function = "alt0";
 681                         pins = "gpio47";
 682                         bias-disable;
 683                 };
 684         };
 685         i2c1_gpio46: i2c1_gpio46 {
 686                 pin-sda {
 687                         function = "alt1";
 688                         pins = "gpio46";
 689                         bias-pull-up;
 690                 };
 691                 pin-scl {
 692                         function = "alt1";
 693                         pins = "gpio47";
 694                         bias-disable;
 695                 };
 696         };
 697         i2c3_gpio2: i2c3_gpio2 {
 698                 pin-sda {
 699                         function = "alt5";
 700                         pins = "gpio2";
 701                         bias-pull-up;
 702                 };
 703                 pin-scl {
 704                         function = "alt5";
 705                         pins = "gpio3";
 706                         bias-disable;
 707                 };
 708         };
 709         i2c3_gpio4: i2c3_gpio4 {
 710                 pin-sda {
 711                         function = "alt5";
 712                         pins = "gpio4";
 713                         bias-pull-up;
 714                 };
 715                 pin-scl {
 716                         function = "alt5";
 717                         pins = "gpio5";
 718                         bias-disable;
 719                 };
 720         };
 721         i2c4_gpio6: i2c4_gpio6 {
 722                 pin-sda {
 723                         function = "alt5";
 724                         pins = "gpio6";
 725                         bias-pull-up;
 726                 };
 727                 pin-scl {
 728                         function = "alt5";
 729                         pins = "gpio7";
 730                         bias-disable;
 731                 };
 732         };
 733         i2c4_gpio8: i2c4_gpio8 {
 734                 pin-sda {
 735                         function = "alt5";
 736                         pins = "gpio8";
 737                         bias-pull-up;
 738                 };
 739                 pin-scl {
 740                         function = "alt5";
 741                         pins = "gpio9";
 742                         bias-disable;
 743                 };
 744         };
 745         i2c5_gpio10: i2c5_gpio10 {
 746                 pin-sda {
 747                         function = "alt5";
 748                         pins = "gpio10";
 749                         bias-pull-up;
 750                 };
 751                 pin-scl {
 752                         function = "alt5";
 753                         pins = "gpio11";
 754                         bias-disable;
 755                 };
 756         };
 757         i2c5_gpio12: i2c5_gpio12 {
 758                 pin-sda {
 759                         function = "alt5";
 760                         pins = "gpio12";
 761                         bias-pull-up;
 762                 };
 763                 pin-scl {
 764                         function = "alt5";
 765                         pins = "gpio13";
 766                         bias-disable;
 767                 };
 768         };
 769         i2c6_gpio0: i2c6_gpio0 {
 770                 pin-sda {
 771                         function = "alt5";
 772                         pins = "gpio0";
 773                         bias-pull-up;
 774                 };
 775                 pin-scl {
 776                         function = "alt5";
 777                         pins = "gpio1";
 778                         bias-disable;
 779                 };
 780         };
 781         i2c6_gpio22: i2c6_gpio22 {
 782                 pin-sda {
 783                         function = "alt5";
 784                         pins = "gpio22";
 785                         bias-pull-up;
 786                 };
 787                 pin-scl {
 788                         function = "alt5";
 789                         pins = "gpio23";
 790                         bias-disable;
 791                 };
 792         };
 793         i2c_slave_gpio8: i2c_slave_gpio8 {
 794                 pins-i2c-slave {
 795                         pins = "gpio8",
 796                                "gpio9",
 797                                "gpio10",
 798                                "gpio11";
 799                         function = "alt3";
 800                 };
 801         };
 802
 803         jtag_gpio48: jtag_gpio48 {
 804                 pins-jtag {
 805                         pins = "gpio48",
 806                                "gpio49",
 807                                "gpio50",
 808                                "gpio51",
 809                                "gpio52",
 810                                "gpio53";
 811                         function = "alt4";
 812                 };
 813         };
 814
 815         mii_gpio28: mii_gpio28 {
 816                 pins-mii {
 817                         pins = "gpio28",
 818                                "gpio29",
 819                                "gpio30",
 820                                "gpio31";
 821                         function = "alt4";
 822                 };
 823         };
 824         mii_gpio36: mii_gpio36 {
 825                 pins-mii {
 826                         pins = "gpio36",
 827                                "gpio37",
 828                                "gpio38",
 829                                "gpio39";
 830                         function = "alt5";
 831                 };
 832         };
 833
 834         pcm_gpio50: pcm_gpio50 {
 835                 pins-pcm {
 836                         pins = "gpio50",
 837                                "gpio51",
 838                                "gpio52",
 839                                "gpio53";
 840                         function = "alt2";
 841                 };
 842         };
 843
 844         pwm0_0_gpio12: pwm0_0_gpio12 {
 845                 pin-pwm {
 846                         pins = "gpio12";
 847                         function = "alt0";
 848                         bias-disable;
 849                 };
 850         };
 851         pwm0_0_gpio18: pwm0_0_gpio18 {
 852                 pin-pwm {
 853                         pins = "gpio18";
 854                         function = "alt5";
 855                         bias-disable;
 856                 };
 857         };
 858         pwm1_0_gpio40: pwm1_0_gpio40 {
 859                 pin-pwm {
 860                         pins = "gpio40";
 861                         function = "alt0";
 862                         bias-disable;
 863                 };
 864         };
 865         pwm0_1_gpio13: pwm0_1_gpio13 {
 866                 pin-pwm {
 867                         pins = "gpio13";
 868                         function = "alt0";
 869                         bias-disable;
 870                 };
 871         };
 872         pwm0_1_gpio19: pwm0_1_gpio19 {
 873                 pin-pwm {
 874                         pins = "gpio19";
 875                         function = "alt5";
 876                         bias-disable;
 877                 };
 878         };
 879         pwm1_1_gpio41: pwm1_1_gpio41 {
 880                 pin-pwm {
 881                         pins = "gpio41";
 882                         function = "alt0";
 883                         bias-disable;
 884                 };
 885         };
 886         pwm0_1_gpio45: pwm0_1_gpio45 {
 887                 pin-pwm {
 888                         pins = "gpio45";
 889                         function = "alt0";
 890                         bias-disable;
 891                 };
 892         };
 893         pwm0_0_gpio52: pwm0_0_gpio52 {
 894                 pin-pwm {
 895                         pins = "gpio52";
 896                         function = "alt1";
 897                         bias-disable;
 898                 };
 899         };
 900         pwm0_1_gpio53: pwm0_1_gpio53 {
 901                 pin-pwm {
 902                         pins = "gpio53";
 903                         function = "alt1";
 904                         bias-disable;
 905                 };
 906         };
 907
 908         rgmii_gpio35: rgmii_gpio35 {
 909                 pin-start-stop {
 910                         pins = "gpio35";
 911                         function = "alt4";
 912                 };
 913                 pin-rx-ok {
 914                         pins = "gpio36";
 915                         function = "alt4";
 916                 };
 917         };
 918         rgmii_irq_gpio34: rgmii_irq_gpio34 {
 919                 pin-irq {
 920                         pins = "gpio34";
 921                         function = "alt5";
 922                 };
 923         };
 924         rgmii_irq_gpio39: rgmii_irq_gpio39 {
 925                 pin-irq {
 926                         pins = "gpio39";
 927                         function = "alt4";
 928                 };
 929         };
 930         rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
 931                 pins-mdio {
 932                         pins = "gpio28",
 933                                "gpio29";
 934                         function = "alt5";
 935                 };
 936         };
 937         rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
 938                 pins-mdio {
 939                         pins = "gpio37",
 940                                "gpio38";
 941                         function = "alt4";
 942                 };
 943         };
 944
 945         spi0_gpio46: spi0_gpio46 {
 946                 pins-spi {
 947                         pins = "gpio46",
 948                                "gpio47",
 949                                "gpio48",
 950                                "gpio49";
 951                         function = "alt2";
 952                 };
 953         };
 954         spi2_gpio46: spi2_gpio46 {
 955                 pins-spi {
 956                         pins = "gpio46",
 957                                "gpio47",
 958                                "gpio48",
 959                                "gpio49",
 960                                "gpio50";
 961                         function = "alt5";
 962                 };
 963         };
 964         spi3_gpio0: spi3_gpio0 {
 965                 pins-spi {
 966                         pins = "gpio0",
 967                                "gpio1",
 968                                "gpio2",
 969                                "gpio3";
 970                         function = "alt3";
 971                 };
 972         };
 973         spi4_gpio4: spi4_gpio4 {
 974                 pins-spi {
 975                         pins = "gpio4",
 976                                "gpio5",
 977                                "gpio6",
 978                                "gpio7";
 979                         function = "alt3";
 980                 };
 981         };
 982         spi5_gpio12: spi5_gpio12 {
 983                 pins-spi {
 984                         pins = "gpio12",
 985                                "gpio13",
 986                                "gpio14",
 987                                "gpio15";
 988                         function = "alt3";
 989                 };
 990         };
 991         spi6_gpio18: spi6_gpio18 {
 992                 pins-spi {
 993                         pins = "gpio18",
 994                                "gpio19",
 995                                "gpio20",
 996                                "gpio21";
 997                         function = "alt3";
 998                 };
 999         };
1000
1001         uart2_gpio0: uart2_gpio0 {
1002                 pin-tx {
1003                         pins = "gpio0";
1004                         function = "alt4";
1005                         bias-disable;
1006                 };
1007                 pin-rx {
1008                         pins = "gpio1";
1009                         function = "alt4";
1010                         bias-pull-up;
1011                 };
1012         };
1013         uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
1014                 pin-cts {
1015                         pins = "gpio2";
1016                         function = "alt4";
1017                         bias-pull-up;
1018                 };
1019                 pin-rts {
1020                         pins = "gpio3";
1021                         function = "alt4";
1022                         bias-disable;
1023                 };
1024         };
1025         uart3_gpio4: uart3_gpio4 {
1026                 pin-tx {
1027                         pins = "gpio4";
1028                         function = "alt4";
1029                         bias-disable;
1030                 };
1031                 pin-rx {
1032                         pins = "gpio5";
1033                         function = "alt4";
1034                         bias-pull-up;
1035                 };
1036         };
1037         uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
1038                 pin-cts {
1039                         pins = "gpio6";
1040                         function = "alt4";
1041                         bias-pull-up;
1042                 };
1043                 pin-rts {
1044                         pins = "gpio7";
1045                         function = "alt4";
1046                         bias-disable;
1047                 };
1048         };
1049         uart4_gpio8: uart4_gpio8 {
1050                 pin-tx {
1051                         pins = "gpio8";
1052                         function = "alt4";
1053                         bias-disable;
1054                 };
1055                 pin-rx {
1056                         pins = "gpio9";
1057                         function = "alt4";
1058                         bias-pull-up;
1059                 };
1060         };
1061         uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1062                 pin-cts {
1063                         pins = "gpio10";
1064                         function = "alt4";
1065                         bias-pull-up;
1066                 };
1067                 pin-rts {
1068                         pins = "gpio11";
1069                         function = "alt4";
1070                         bias-disable;
1071                 };
1072         };
1073         uart5_gpio12: uart5_gpio12 {
1074                 pin-tx {
1075                         pins = "gpio12";
1076                         function = "alt4";
1077                         bias-disable;
1078                 };
1079                 pin-rx {
1080                         pins = "gpio13";
1081                         function = "alt4";
1082                         bias-pull-up;
1083                 };
1084         };
1085         uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1086                 pin-cts {
1087                         pins = "gpio14";
1088                         function = "alt4";
1089                         bias-pull-up;
1090                 };
1091                 pin-rts {
1092                         pins = "gpio15";
1093                         function = "alt4";
1094                         bias-disable;
1095                 };
1096         };
1097 };
1098
1099 &rmem {
1100         #address-cells = <2>;
1101 };
1102
1103 &cma {
1104         /*
1105          * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1106          * that's not good enough for the BCM2711 as some devices can
1107          * only address the lower 1G of memory (ZONE_DMA).
1108          */
1109         alloc-ranges = <0x0 0x00000000 0x40000000>;
1110 };
1111
1112 &i2c0if {
1113         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1114         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1115 };
1116
1117 &i2c1 {
1118         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1119         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1120 };
1121
1122 &mailbox {
1123         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1124 };
1125
1126 &sdhci {
1127         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1128 };
1129
1130 &sdhost {
1131         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1132 };
1133
1134 &spi {
1135         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1136 };
1137
1138 &spi1 {
1139         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1140 };
1141
1142 &spi2 {
1143         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1144 };
1145
1146 &system_timer {
1147         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1148                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1149                      <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1150                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1151 };
1152
1153 &txp {
1154         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1155 };
1156
1157 &uart0 {
1158         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1159 };
1160
1161 &uart1 {
1162         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1163 };
1164
1165 &usb {
1166         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1167 };