1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
8 compatible = "brcm,bcm2711";
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
37 * Common BCM283x peripherals
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
49 * bringing up secondary cores.
51 local_intc: local_intc@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
53 reg = <0x40000000 0x100>;
56 gicv2: interrupt-controller@40041000 {
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
60 reg = <0x40041000 0x1000>,
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
65 IRQ_TYPE_LEVEL_HIGH)>;
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
71 reg = <0x7d5d2000 0xf00>;
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
80 compatible = "brcm,bcm2835-dma";
81 reg = <0x7e007000 0xb00>;
82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-names = "dma0",
106 brcm,dma-channel-mask = <0x07f5>;
109 pm: watchdog@7e100000 {
110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
113 reg = <0x7e100000 0x114>,
116 clocks = <&clocks BCM2835_CLOCK_V3D>,
117 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
118 <&clocks BCM2835_CLOCK_H264>,
119 <&clocks BCM2835_CLOCK_ISP>;
120 clock-names = "v3d", "peri_image", "h264", "isp";
121 system-power-controller;
125 compatible = "brcm,bcm2711-rng200";
126 reg = <0x7e104000 0x28>;
129 uart2: serial@7e201400 {
130 compatible = "arm,pl011", "arm,primecell";
131 reg = <0x7e201400 0x200>;
132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&clocks BCM2835_CLOCK_UART>,
134 <&clocks BCM2835_CLOCK_VPU>;
135 clock-names = "uartclk", "apb_pclk";
136 arm,primecell-periphid = <0x00241011>;
140 uart3: serial@7e201600 {
141 compatible = "arm,pl011", "arm,primecell";
142 reg = <0x7e201600 0x200>;
143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&clocks BCM2835_CLOCK_UART>,
145 <&clocks BCM2835_CLOCK_VPU>;
146 clock-names = "uartclk", "apb_pclk";
147 arm,primecell-periphid = <0x00241011>;
151 uart4: serial@7e201800 {
152 compatible = "arm,pl011", "arm,primecell";
153 reg = <0x7e201800 0x200>;
154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clocks BCM2835_CLOCK_UART>,
156 <&clocks BCM2835_CLOCK_VPU>;
157 clock-names = "uartclk", "apb_pclk";
158 arm,primecell-periphid = <0x00241011>;
162 uart5: serial@7e201a00 {
163 compatible = "arm,pl011", "arm,primecell";
164 reg = <0x7e201a00 0x200>;
165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clocks BCM2835_CLOCK_UART>,
167 <&clocks BCM2835_CLOCK_VPU>;
168 clock-names = "uartclk", "apb_pclk";
169 arm,primecell-periphid = <0x00241011>;
174 compatible = "brcm,bcm2835-spi";
175 reg = <0x7e204600 0x0200>;
176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&clocks BCM2835_CLOCK_VPU>;
178 #address-cells = <1>;
184 compatible = "brcm,bcm2835-spi";
185 reg = <0x7e204800 0x0200>;
186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clocks BCM2835_CLOCK_VPU>;
188 #address-cells = <1>;
194 compatible = "brcm,bcm2835-spi";
195 reg = <0x7e204a00 0x0200>;
196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clocks BCM2835_CLOCK_VPU>;
198 #address-cells = <1>;
204 compatible = "brcm,bcm2835-spi";
205 reg = <0x7e204c00 0x0200>;
206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clocks BCM2835_CLOCK_VPU>;
208 #address-cells = <1>;
214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
215 reg = <0x7e205600 0x200>;
216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clocks BCM2835_CLOCK_VPU>;
218 #address-cells = <1>;
224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
225 reg = <0x7e205800 0x200>;
226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clocks BCM2835_CLOCK_VPU>;
228 #address-cells = <1>;
234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
235 reg = <0x7e205a00 0x200>;
236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clocks BCM2835_CLOCK_VPU>;
238 #address-cells = <1>;
244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
245 reg = <0x7e205c00 0x200>;
246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clocks BCM2835_CLOCK_VPU>;
248 #address-cells = <1>;
253 pixelvalve0: pixelvalve@7e206000 {
254 compatible = "brcm,bcm2711-pixelvalve0";
255 reg = <0x7e206000 0x100>;
256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
260 pixelvalve1: pixelvalve@7e207000 {
261 compatible = "brcm,bcm2711-pixelvalve1";
262 reg = <0x7e207000 0x100>;
263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
267 pixelvalve2: pixelvalve@7e20a000 {
268 compatible = "brcm,bcm2711-pixelvalve2";
269 reg = <0x7e20a000 0x100>;
270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
275 compatible = "brcm,bcm2835-pwm";
276 reg = <0x7e20c800 0x28>;
277 clocks = <&clocks BCM2835_CLOCK_PWM>;
278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
279 assigned-clock-rates = <10000000>;
284 pixelvalve4: pixelvalve@7e216000 {
285 compatible = "brcm,bcm2711-pixelvalve4";
286 reg = <0x7e216000 0x100>;
287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
292 compatible = "brcm,bcm2711-hvs";
293 reg = <0x7e400000 0x8000>;
294 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
297 pixelvalve3: pixelvalve@7ec12000 {
298 compatible = "brcm,bcm2711-pixelvalve3";
299 reg = <0x7ec12000 0x100>;
300 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
305 compatible = "brcm,bcm2711-vec";
306 reg = <0x7ec13000 0x1000>;
307 clocks = <&firmware_clocks 15>;
308 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
312 dvp: clock@7ef00000 {
313 compatible = "brcm,brcm2711-dvp";
314 reg = <0x7ef00000 0x10>;
315 clocks = <&clk_108MHz>;
320 aon_intr: interrupt-controller@7ef00100 {
321 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
322 reg = <0x7ef00100 0x30>;
323 interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
324 interrupt-controller;
325 #interrupt-cells = <1>;
329 hdmi0: hdmi@7ef00700 {
330 compatible = "brcm,bcm2711-hdmi0";
331 reg = <0x7ef00700 0x300>,
351 clocks = <&firmware_clocks 13>,
352 <&firmware_clocks 14>,
355 clock-names = "hdmi", "bvb", "audio", "cec";
357 interrupt-parent = <&aon_intr>;
358 interrupts = <0>, <1>, <2>,
360 interrupt-names = "cec-tx", "cec-rx", "cec-low",
361 "wakeup", "hpd-connected", "hpd-removed";
363 dmas = <&dma (10 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>;
364 dma-names = "audio-rx";
369 compatible = "brcm,bcm2711-hdmi-i2c";
370 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
371 reg-names = "bsc", "auto-i2c";
372 clock-frequency = <97500>;
376 hdmi1: hdmi@7ef05700 {
377 compatible = "brcm,bcm2711-hdmi1";
378 reg = <0x7ef05700 0x300>,
399 clock-names = "hdmi", "bvb", "audio", "cec";
400 clocks = <&firmware_clocks 13>,
401 <&firmware_clocks 14>,
405 interrupt-parent = <&aon_intr>;
406 interrupts = <8>, <7>, <6>, // This is correct
408 interrupt-names = "cec-tx", "cec-rx", "cec-low",
409 "wakeup", "hpd-connected", "hpd-removed";
410 dmas = <&dma (17 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>;
411 dma-names = "audio-rx";
416 compatible = "brcm,bcm2711-hdmi-i2c";
417 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
418 reg-names = "bsc", "auto-i2c";
419 clock-frequency = <97500>;
425 * emmc2 has different DMA constraints based on SoC revisions. It was
426 * moved into its own bus, so as for RPi4's firmware to update them.
427 * The firmware will find whether the emmc2bus alias is defined, and if
428 * so, it'll edit the dma-ranges property below accordingly.
431 compatible = "simple-bus";
432 #address-cells = <2>;
435 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
436 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
438 emmc2: mmc@7e340000 {
439 compatible = "brcm,bcm2711-emmc2";
440 reg = <0x0 0x7e340000 0x100>;
441 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
448 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3", "arm,cortex-a7-pmu";
449 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
453 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
457 compatible = "arm,armv8-timer";
458 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
459 IRQ_TYPE_LEVEL_LOW)>,
460 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
461 IRQ_TYPE_LEVEL_LOW)>,
462 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
463 IRQ_TYPE_LEVEL_LOW)>,
464 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
465 IRQ_TYPE_LEVEL_LOW)>;
466 /* This only applies to the ARMv7 stub */
467 arm,cpu-registers-not-fw-configured;
471 #address-cells = <1>;
473 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
475 /* Source for d/i-cache-line-size and d/i-cache-sets
476 * https://developer.arm.com/documentation/100095/0003
477 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
478 * Source for d/i-cache-size
479 * https://www.raspberrypi.com/documentation/computers
480 * /processors.html#bcm2711
484 compatible = "arm,cortex-a72";
486 enable-method = "spin-table";
487 cpu-release-addr = <0x0 0x000000d8>;
488 d-cache-size = <0x8000>;
489 d-cache-line-size = <64>;
490 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
491 i-cache-size = <0xc000>;
492 i-cache-line-size = <64>;
493 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
494 next-level-cache = <&l2>;
499 compatible = "arm,cortex-a72";
501 enable-method = "spin-table";
502 cpu-release-addr = <0x0 0x000000e0>;
503 d-cache-size = <0x8000>;
504 d-cache-line-size = <64>;
505 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
506 i-cache-size = <0xc000>;
507 i-cache-line-size = <64>;
508 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
509 next-level-cache = <&l2>;
514 compatible = "arm,cortex-a72";
516 enable-method = "spin-table";
517 cpu-release-addr = <0x0 0x000000e8>;
518 d-cache-size = <0x8000>;
519 d-cache-line-size = <64>;
520 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
521 i-cache-size = <0xc000>;
522 i-cache-line-size = <64>;
523 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
524 next-level-cache = <&l2>;
529 compatible = "arm,cortex-a72";
531 enable-method = "spin-table";
532 cpu-release-addr = <0x0 0x000000f0>;
533 d-cache-size = <0x8000>;
534 d-cache-line-size = <64>;
535 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
536 i-cache-size = <0xc000>;
537 i-cache-line-size = <64>;
538 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
539 next-level-cache = <&l2>;
542 /* Source for d/i-cache-line-size and d/i-cache-sets
543 * https://developer.arm.com/documentation/100095/0003
544 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
545 * Source for d/i-cache-size
546 * https://www.raspberrypi.com/documentation/computers
547 * /processors.html#bcm2711
550 compatible = "cache";
551 cache-size = <0x100000>;
552 cache-line-size = <64>;
553 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
559 compatible = "simple-bus";
560 #address-cells = <2>;
563 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x0 0x03800000>,
564 <0x6 0x00000000 0x6 0x00000000 0x0 0x40000000>;
566 pcie0: pcie@7d500000 {
567 compatible = "brcm,bcm2711-pcie";
568 reg = <0x0 0x7d500000 0x0 0x9310>;
570 #address-cells = <3>;
571 #interrupt-cells = <1>;
573 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "pcie", "msi";
576 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
577 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
578 IRQ_TYPE_LEVEL_HIGH>,
579 <0 0 0 2 &gicv2 GIC_SPI 144
580 IRQ_TYPE_LEVEL_HIGH>,
581 <0 0 0 3 &gicv2 GIC_SPI 145
582 IRQ_TYPE_LEVEL_HIGH>,
583 <0 0 0 4 &gicv2 GIC_SPI 146
584 IRQ_TYPE_LEVEL_HIGH>;
586 msi-parent = <&pcie0>;
588 ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000
591 * The wrapper around the PCIe block has a bug
592 * preventing it from accessing beyond the first 3GB of
595 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
600 genet: ethernet@7d580000 {
601 compatible = "brcm,bcm2711-genet-v5";
602 reg = <0x0 0x7d580000 0x0 0x10000>;
603 #address-cells = <0x1>;
605 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
609 genet_mdio: mdio@e14 {
610 compatible = "brcm,genet-mdio-v5";
613 #address-cells = <0x1>;
621 clock-frequency = <54000000>;
625 compatible = "brcm,bcm2711-cprman";
629 coefficients = <(-487) 410040>;
630 thermal-sensors = <&thermal>;
634 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
638 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
639 compatible = "brcm,bcm2711-dsi1";
643 compatible = "brcm,bcm2711-gpio";
644 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
649 gpio-ranges = <&gpio 0 0 58>;
651 gpclk0_gpio49: gpclk0_gpio49 {
658 gpclk1_gpio50: gpclk1_gpio50 {
665 gpclk2_gpio51: gpclk2_gpio51 {
673 i2c0_gpio46: i2c0_gpio46 {
685 i2c1_gpio46: i2c1_gpio46 {
697 i2c3_gpio2: i2c3_gpio2 {
709 i2c3_gpio4: i2c3_gpio4 {
721 i2c4_gpio6: i2c4_gpio6 {
733 i2c4_gpio8: i2c4_gpio8 {
745 i2c5_gpio10: i2c5_gpio10 {
757 i2c5_gpio12: i2c5_gpio12 {
769 i2c6_gpio0: i2c6_gpio0 {
781 i2c6_gpio22: i2c6_gpio22 {
793 i2c_slave_gpio8: i2c_slave_gpio8 {
803 jtag_gpio48: jtag_gpio48 {
815 mii_gpio28: mii_gpio28 {
824 mii_gpio36: mii_gpio36 {
834 pcm_gpio50: pcm_gpio50 {
844 pwm0_0_gpio12: pwm0_0_gpio12 {
851 pwm0_0_gpio18: pwm0_0_gpio18 {
858 pwm1_0_gpio40: pwm1_0_gpio40 {
865 pwm0_1_gpio13: pwm0_1_gpio13 {
872 pwm0_1_gpio19: pwm0_1_gpio19 {
879 pwm1_1_gpio41: pwm1_1_gpio41 {
886 pwm0_1_gpio45: pwm0_1_gpio45 {
893 pwm0_0_gpio52: pwm0_0_gpio52 {
900 pwm0_1_gpio53: pwm0_1_gpio53 {
908 rgmii_gpio35: rgmii_gpio35 {
918 rgmii_irq_gpio34: rgmii_irq_gpio34 {
924 rgmii_irq_gpio39: rgmii_irq_gpio39 {
930 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
937 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
945 spi0_gpio46: spi0_gpio46 {
954 spi2_gpio46: spi2_gpio46 {
964 spi3_gpio0: spi3_gpio0 {
973 spi4_gpio4: spi4_gpio4 {
982 spi5_gpio12: spi5_gpio12 {
991 spi6_gpio18: spi6_gpio18 {
1001 uart2_gpio0: uart2_gpio0 {
1013 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
1025 uart3_gpio4: uart3_gpio4 {
1037 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
1049 uart4_gpio8: uart4_gpio8 {
1061 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1073 uart5_gpio12: uart5_gpio12 {
1085 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1100 #address-cells = <2>;
1105 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1106 * that's not good enough for the BCM2711 as some devices can
1107 * only address the lower 1G of memory (ZONE_DMA).
1109 alloc-ranges = <0x0 0x00000000 0x40000000>;
1113 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1118 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1119 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1123 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1127 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1131 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1139 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1143 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1147 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1154 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1158 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1162 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;