arch/arm/boot/dts/bcm2711.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "bcm283x.dtsi"
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/soc/bcm2835-pm.h>
   6
   7 / {
   8         compatible = "brcm,bcm2711";
   9
  10         #address-cells = <2>;
  11         #size-cells = <1>;
  12
  13         interrupt-parent = <&gicv2>;
  14
  15         vc4: gpu {
  16                 compatible = "brcm,bcm2711-vc5";
  17                 status = "disabled";
  18         };
  19
  20         clk_108MHz: clk-108M {
  21                 #clock-cells = <0>;
  22                 compatible = "fixed-clock";
  23                 clock-frequency = <108000000>;
  24                 clock-output-names = "108MHz-clock";
  25         };
  26
  27         soc {
  28                 /*
  29                  * Defined ranges:
  30                  *   Common BCM283x peripherals
  31                  *   BCM2711-specific peripherals
  32                  *   ARM-local peripherals
  33                  */
  34                 ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
  35                          <0x7c000000  0x0 0xfc000000  0x02000000>,
  36                          <0x40000000  0x0 0xff800000  0x00800000>;
  37                 /* Emulate a contiguous 30-bit address range for DMA */
  38                 dma-ranges = <0xc0000000  0x0 0x00000000  0x40000000>;
  39
  40                 /*
  41                  * This node is the provider for the enable-method for
  42                  * bringing up secondary cores.
  43                  */
  44                 local_intc: local_intc@40000000 {
  45                         compatible = "brcm,bcm2836-l1-intc";
  46                         reg = <0x40000000 0x100>;
  47                 };
  48
  49                 gicv2: interrupt-controller@40041000 {
  50                         interrupt-controller;
  51                         #interrupt-cells = <3>;
  52                         compatible = "arm,gic-400";
  53                         reg =   <0x40041000 0x1000>,
  54                                 <0x40042000 0x2000>,
  55                                 <0x40044000 0x2000>,
  56                                 <0x40046000 0x2000>;
  57                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
  58                                                  IRQ_TYPE_LEVEL_HIGH)>;
  59                 };
  60
  61                 avs_monitor: avs-monitor@7d5d2000 {
  62                         compatible = "brcm,bcm2711-avs-monitor",
  63                                      "syscon", "simple-mfd";
  64                         reg = <0x7d5d2000 0xf00>;
  65
  66                         thermal: thermal {
  67                                 compatible = "brcm,bcm2711-thermal";
  68                                 #thermal-sensor-cells = <0>;
  69                         };
  70                 };
  71
  72                 dma: dma@7e007000 {
  73                         compatible = "brcm,bcm2835-dma";
  74                         reg = <0x7e007000 0xb00>;
  75                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  76                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
  77                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
  82                                      /* DMA lite 7 - 10 */
  83                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  87                         interrupt-names = "dma0",
  88                                           "dma1",
  89                                           "dma2",
  90                                           "dma3",
  91                                           "dma4",
  92                                           "dma5",
  93                                           "dma6",
  94                                           "dma7",
  95                                           "dma8",
  96                                           "dma9",
  97                                           "dma10";
  98                         #dma-cells = <1>;
  99                         brcm,dma-channel-mask = <0x07f5>;
 100                 };
 101
 102                 pm: watchdog@7e100000 {
 103                         compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
 104                         #power-domain-cells = <1>;
 105                         #reset-cells = <1>;
 106                         reg = <0x7e100000 0x114>,
 107                               <0x7e00a000 0x24>,
 108                               <0x7ec11000 0x20>;
 109                         clocks = <&clocks BCM2835_CLOCK_V3D>,
 110                                  <&clocks BCM2835_CLOCK_PERI_IMAGE>,
 111                                  <&clocks BCM2835_CLOCK_H264>,
 112                                  <&clocks BCM2835_CLOCK_ISP>;
 113                         clock-names = "v3d", "peri_image", "h264", "isp";
 114                         system-power-controller;
 115                 };
 116
 117                 rng@7e104000 {
 118                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 119
 120                         /* RNG is incompatible with brcm,bcm2835-rng */
 121                         status = "disabled";
 122                 };
 123
 124                 uart2: serial@7e201400 {
 125                         compatible = "arm,pl011", "arm,primecell";
 126                         reg = <0x7e201400 0x200>;
 127                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 128                         clocks = <&clocks BCM2835_CLOCK_UART>,
 129                                  <&clocks BCM2835_CLOCK_VPU>;
 130                         clock-names = "uartclk", "apb_pclk";
 131                         arm,primecell-periphid = <0x00241011>;
 132                         status = "disabled";
 133                 };
 134
 135                 uart3: serial@7e201600 {
 136                         compatible = "arm,pl011", "arm,primecell";
 137                         reg = <0x7e201600 0x200>;
 138                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&clocks BCM2835_CLOCK_UART>,
 140                                  <&clocks BCM2835_CLOCK_VPU>;
 141                         clock-names = "uartclk", "apb_pclk";
 142                         arm,primecell-periphid = <0x00241011>;
 143                         status = "disabled";
 144                 };
 145
 146                 uart4: serial@7e201800 {
 147                         compatible = "arm,pl011", "arm,primecell";
 148                         reg = <0x7e201800 0x200>;
 149                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&clocks BCM2835_CLOCK_UART>,
 151                                  <&clocks BCM2835_CLOCK_VPU>;
 152                         clock-names = "uartclk", "apb_pclk";
 153                         arm,primecell-periphid = <0x00241011>;
 154                         status = "disabled";
 155                 };
 156
 157                 uart5: serial@7e201a00 {
 158                         compatible = "arm,pl011", "arm,primecell";
 159                         reg = <0x7e201a00 0x200>;
 160                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 161                         clocks = <&clocks BCM2835_CLOCK_UART>,
 162                                  <&clocks BCM2835_CLOCK_VPU>;
 163                         clock-names = "uartclk", "apb_pclk";
 164                         arm,primecell-periphid = <0x00241011>;
 165                         status = "disabled";
 166                 };
 167
 168                 spi3: spi@7e204600 {
 169                         compatible = "brcm,bcm2835-spi";
 170                         reg = <0x7e204600 0x0200>;
 171                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 172                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         status = "disabled";
 176                 };
 177
 178                 spi4: spi@7e204800 {
 179                         compatible = "brcm,bcm2835-spi";
 180                         reg = <0x7e204800 0x0200>;
 181                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 182                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                         status = "disabled";
 186                 };
 187
 188                 spi5: spi@7e204a00 {
 189                         compatible = "brcm,bcm2835-spi";
 190                         reg = <0x7e204a00 0x0200>;
 191                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 192                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         status = "disabled";
 196                 };
 197
 198                 spi6: spi@7e204c00 {
 199                         compatible = "brcm,bcm2835-spi";
 200                         reg = <0x7e204c00 0x0200>;
 201                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         status = "disabled";
 206                 };
 207
 208                 i2c3: i2c@7e205600 {
 209                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 210                         reg = <0x7e205600 0x200>;
 211                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         status = "disabled";
 216                 };
 217
 218                 i2c4: i2c@7e205800 {
 219                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 220                         reg = <0x7e205800 0x200>;
 221                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 222                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         status = "disabled";
 226                 };
 227
 228                 i2c5: i2c@7e205a00 {
 229                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 230                         reg = <0x7e205a00 0x200>;
 231                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 233                         #address-cells = <1>;
 234                         #size-cells = <0>;
 235                         status = "disabled";
 236                 };
 237
 238                 i2c6: i2c@7e205c00 {
 239                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 240                         reg = <0x7e205c00 0x200>;
 241                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         status = "disabled";
 246                 };
 247
 248                 pixelvalve0: pixelvalve@7e206000 {
 249                         compatible = "brcm,bcm2711-pixelvalve0";
 250                         reg = <0x7e206000 0x100>;
 251                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 252                         status = "disabled";
 253                 };
 254
 255                 pixelvalve1: pixelvalve@7e207000 {
 256                         compatible = "brcm,bcm2711-pixelvalve1";
 257                         reg = <0x7e207000 0x100>;
 258                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 259                         status = "disabled";
 260                 };
 261
 262                 pixelvalve2: pixelvalve@7e20a000 {
 263                         compatible = "brcm,bcm2711-pixelvalve2";
 264                         reg = <0x7e20a000 0x100>;
 265                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 266                         status = "disabled";
 267                 };
 268
 269                 pwm1: pwm@7e20c800 {
 270                         compatible = "brcm,bcm2835-pwm";
 271                         reg = <0x7e20c800 0x28>;
 272                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 273                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 274                         assigned-clock-rates = <10000000>;
 275                         #pwm-cells = <2>;
 276                         status = "disabled";
 277                 };
 278
 279                 pixelvalve4: pixelvalve@7e216000 {
 280                         compatible = "brcm,bcm2711-pixelvalve4";
 281                         reg = <0x7e216000 0x100>;
 282                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 283                         status = "disabled";
 284                 };
 285
 286                 emmc2: emmc2@7e340000 {
 287                         compatible = "brcm,bcm2711-emmc2";
 288                         reg = <0x7e340000 0x100>;
 289                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 290                         clocks = <&clocks BCM2711_CLOCK_EMMC2>;
 291                         status = "disabled";
 292                 };
 293
 294                 hvs@7e400000 {
 295                         clocks = <&firmware_clocks 4>;
 296                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 297                 };
 298
 299                 pixelvalve3: pixelvalve@7ec12000 {
 300                         compatible = "brcm,bcm2711-pixelvalve3";
 301                         reg = <0x7ec12000 0x100>;
 302                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 303                         status = "disabled";
 304                 };
 305
 306                 dvp: clock@7ef00000 {
 307                         compatible = "brcm,brcm2711-dvp";
 308                         reg = <0x7ef00000 0x10>;
 309                         clocks = <&clk_108MHz>;
 310                         #clock-cells = <1>;
 311                         #reset-cells = <1>;
 312                 };
 313
 314                 hdmi0: hdmi@7ef00700 {
 315                         compatible = "brcm,bcm2711-hdmi0";
 316                         reg = <0x7ef00700 0x300>,
 317                               <0x7ef00300 0x200>,
 318                               <0x7ef00f00 0x80>,
 319                               <0x7ef00f80 0x80>,
 320                               <0x7ef01b00 0x200>,
 321                               <0x7ef01f00 0x400>,
 322                               <0x7ef00200 0x80>,
 323                               <0x7ef04300 0x100>,
 324                               <0x7ef20000 0x100>,
 325                               <0x7ef00100 0x30>;
 326                         reg-names = "hdmi",
 327                                     "dvp",
 328                                     "phy",
 329                                     "rm",
 330                                     "packet",
 331                                     "metadata",
 332                                     "csc",
 333                                     "cec",
 334                                     "hd",
 335                                     "intr2";
 336                         clocks = <&firmware_clocks 13>, <&firmware_clocks 14>;
 337                         clock-names = "hdmi", "bvb";
 338                         resets = <&dvp 0>;
 339                         ddc = <&ddc0>;
 340                         dmas = <&dma 10>;
 341                         dma-names = "audio-rx";
 342                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 343                         status = "disabled";
 344                 };
 345
 346                 ddc0: i2c@7ef04500 {
 347                         compatible = "brcm,bcm2711-hdmi-i2c";
 348                         reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
 349                         reg-names = "bsc", "auto-i2c";
 350                         clock-frequency = <97500>;
 351                         status = "disabled";
 352                 };
 353
 354                 hdmi1: hdmi@7ef05700 {
 355                         compatible = "brcm,bcm2711-hdmi1";
 356                         reg = <0x7ef05700 0x300>,
 357                               <0x7ef05300 0x200>,
 358                               <0x7ef05f00 0x80>,
 359                               <0x7ef05f80 0x80>,
 360                               <0x7ef06b00 0x200>,
 361                               <0x7ef06f00 0x400>,
 362                               <0x7ef00280 0x80>,
 363                               <0x7ef09300 0x100>,
 364                               <0x7ef20000 0x100>,
 365                               <0x7ef00100 0x30>;
 366                         reg-names = "hdmi",
 367                                     "dvp",
 368                                     "phy",
 369                                     "rm",
 370                                     "packet",
 371                                     "metadata",
 372                                     "csc",
 373                                     "cec",
 374                                     "hd",
 375                                     "intr2";
 376                         ddc = <&ddc1>;
 377                         clocks = <&firmware_clocks 13>, <&firmware_clocks 14>;
 378                         clock-names = "hdmi", "bvb";
 379                         resets = <&dvp 1>;
 380                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 381                         status = "disabled";
 382                 };
 383
 384                 ddc1: i2c@7ef09500 {
 385                         compatible = "brcm,bcm2711-hdmi-i2c";
 386                         reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
 387                         reg-names = "bsc", "auto-i2c";
 388                         clock-frequency = <97500>;
 389                         status = "disabled";
 390                 };
 391         };
 392
 393         arm-pmu {
 394                 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
 395                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 396                         <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 397                         <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 398                         <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 399                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 400         };
 401
 402         timer {
 403                 compatible = "arm,armv8-timer";
 404                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 405                                           IRQ_TYPE_LEVEL_LOW)>,
 406                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 407                                           IRQ_TYPE_LEVEL_LOW)>,
 408                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 409                                           IRQ_TYPE_LEVEL_LOW)>,
 410                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 411                                           IRQ_TYPE_LEVEL_LOW)>;
 412                 /* This only applies to the ARMv7 stub */
 413                 arm,cpu-registers-not-fw-configured;
 414         };
 415
 416         cpus: cpus {
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 420
 421                 cpu0: cpu@0 {
 422                         device_type = "cpu";
 423                         compatible = "arm,cortex-a72";
 424                         reg = <0>;
 425                         enable-method = "spin-table";
 426                         cpu-release-addr = <0x0 0x000000d8>;
 427                 };
 428
 429                 cpu1: cpu@1 {
 430                         device_type = "cpu";
 431                         compatible = "arm,cortex-a72";
 432                         reg = <1>;
 433                         enable-method = "spin-table";
 434                         cpu-release-addr = <0x0 0x000000e0>;
 435                 };
 436
 437                 cpu2: cpu@2 {
 438                         device_type = "cpu";
 439                         compatible = "arm,cortex-a72";
 440                         reg = <2>;
 441                         enable-method = "spin-table";
 442                         cpu-release-addr = <0x0 0x000000e8>;
 443                 };
 444
 445                 cpu3: cpu@3 {
 446                         device_type = "cpu";
 447                         compatible = "arm,cortex-a72";
 448                         reg = <3>;
 449                         enable-method = "spin-table";
 450                         cpu-release-addr = <0x0 0x000000f0>;
 451                 };
 452         };
 453
 454         scb {
 455                 compatible = "simple-bus";
 456                 #address-cells = <2>;
 457                 #size-cells = <2>;
 458
 459                 ranges = <0x0 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,
 460                          <0x6 0x00000000  0x6 0x00000000  0x0 0x40000000>;
 461
 462                 pcie0: pcie@7d500000 {
 463                         compatible = "brcm,bcm2711-pcie";
 464                         reg = <0x0 0x7d500000  0x0 0x9310>;
 465                         device_type = "pci";
 466                         #address-cells = <3>;
 467                         #interrupt-cells = <1>;
 468                         #size-cells = <2>;
 469                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 470                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 471                         interrupt-names = "pcie", "msi";
 472                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 473                         interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
 474                                                         IRQ_TYPE_LEVEL_HIGH>;
 475                         msi-controller;
 476                         msi-parent = <&pcie0>;
 477
 478                         ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
 479                                   0x0 0x04000000>;
 480                         /*
 481                          * The wrapper around the PCIe block has a bug
 482                          * preventing it from accessing beyond the first 3GB of
 483                          * memory.
 484                          */
 485                         dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
 486                                       0x0 0xc0000000>;
 487                         brcm,enable-ssc;
 488                 };
 489
 490                 genet: ethernet@7d580000 {
 491                         compatible = "brcm,bcm2711-genet-v5";
 492                         reg = <0x0 0x7d580000  0x0 0x10000>;
 493                         #address-cells = <0x1>;
 494                         #size-cells = <0x1>;
 495                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 497                         status = "disabled";
 498
 499                         genet_mdio: mdio@e14 {
 500                                 compatible = "brcm,genet-mdio-v5";
 501                                 reg = <0xe14 0x8>;
 502                                 reg-names = "mdio";
 503                                 #address-cells = <0x0>;
 504                                 #size-cells = <0x1>;
 505                         };
 506                 };
 507         };
 508 };
 509
 510 &clk_osc {
 511         clock-frequency = <54000000>;
 512 };
 513
 514 &clocks {
 515         compatible = "brcm,bcm2711-cprman";
 516 };
 517
 518 &cpu_thermal {
 519         coefficients = <(-487) 410040>;
 520         thermal-sensors = <&thermal>;
 521 };
 522
 523 &dsi0 {
 524         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 525 };
 526
 527 &dsi1 {
 528         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 529 };
 530
 531 &gpio {
 532         compatible = "brcm,bcm2711-gpio";
 533         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 534                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 535                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 536                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 537
 538         gpclk0_gpio49: gpclk0_gpio49 {
 539                 pin-gpclk {
 540                         pins = "gpio49";
 541                         function = "alt1";
 542                         bias-disable;
 543                 };
 544         };
 545         gpclk1_gpio50: gpclk1_gpio50 {
 546                 pin-gpclk {
 547                         pins = "gpio50";
 548                         function = "alt1";
 549                         bias-disable;
 550                 };
 551         };
 552         gpclk2_gpio51: gpclk2_gpio51 {
 553                 pin-gpclk {
 554                         pins = "gpio51";
 555                         function = "alt1";
 556                         bias-disable;
 557                 };
 558         };
 559
 560         i2c0_gpio46: i2c0_gpio46 {
 561                 pin-sda {
 562                         function = "alt0";
 563                         pins = "gpio46";
 564                         bias-pull-up;
 565                 };
 566                 pin-scl {
 567                         function = "alt0";
 568                         pins = "gpio47";
 569                         bias-disable;
 570                 };
 571         };
 572         i2c1_gpio46: i2c1_gpio46 {
 573                 pin-sda {
 574                         function = "alt1";
 575                         pins = "gpio46";
 576                         bias-pull-up;
 577                 };
 578                 pin-scl {
 579                         function = "alt1";
 580                         pins = "gpio47";
 581                         bias-disable;
 582                 };
 583         };
 584         i2c3_gpio2: i2c3_gpio2 {
 585                 pin-sda {
 586                         function = "alt5";
 587                         pins = "gpio2";
 588                         bias-pull-up;
 589                 };
 590                 pin-scl {
 591                         function = "alt5";
 592                         pins = "gpio3";
 593                         bias-disable;
 594                 };
 595         };
 596         i2c3_gpio4: i2c3_gpio4 {
 597                 pin-sda {
 598                         function = "alt5";
 599                         pins = "gpio4";
 600                         bias-pull-up;
 601                 };
 602                 pin-scl {
 603                         function = "alt5";
 604                         pins = "gpio5";
 605                         bias-disable;
 606                 };
 607         };
 608         i2c4_gpio6: i2c4_gpio6 {
 609                 pin-sda {
 610                         function = "alt5";
 611                         pins = "gpio6";
 612                         bias-pull-up;
 613                 };
 614                 pin-scl {
 615                         function = "alt5";
 616                         pins = "gpio7";
 617                         bias-disable;
 618                 };
 619         };
 620         i2c4_gpio8: i2c4_gpio8 {
 621                 pin-sda {
 622                         function = "alt5";
 623                         pins = "gpio8";
 624                         bias-pull-up;
 625                 };
 626                 pin-scl {
 627                         function = "alt5";
 628                         pins = "gpio9";
 629                         bias-disable;
 630                 };
 631         };
 632         i2c5_gpio10: i2c5_gpio10 {
 633                 pin-sda {
 634                         function = "alt5";
 635                         pins = "gpio10";
 636                         bias-pull-up;
 637                 };
 638                 pin-scl {
 639                         function = "alt5";
 640                         pins = "gpio11";
 641                         bias-disable;
 642                 };
 643         };
 644         i2c5_gpio12: i2c5_gpio12 {
 645                 pin-sda {
 646                         function = "alt5";
 647                         pins = "gpio12";
 648                         bias-pull-up;
 649                 };
 650                 pin-scl {
 651                         function = "alt5";
 652                         pins = "gpio13";
 653                         bias-disable;
 654                 };
 655         };
 656         i2c6_gpio0: i2c6_gpio0 {
 657                 pin-sda {
 658                         function = "alt5";
 659                         pins = "gpio0";
 660                         bias-pull-up;
 661                 };
 662                 pin-scl {
 663                         function = "alt5";
 664                         pins = "gpio1";
 665                         bias-disable;
 666                 };
 667         };
 668         i2c6_gpio22: i2c6_gpio22 {
 669                 pin-sda {
 670                         function = "alt5";
 671                         pins = "gpio22";
 672                         bias-pull-up;
 673                 };
 674                 pin-scl {
 675                         function = "alt5";
 676                         pins = "gpio23";
 677                         bias-disable;
 678                 };
 679         };
 680         i2c_slave_gpio8: i2c_slave_gpio8 {
 681                 pins-i2c-slave {
 682                         pins = "gpio8",
 683                                "gpio9",
 684                                "gpio10",
 685                                "gpio11";
 686                         function = "alt3";
 687                 };
 688         };
 689
 690         jtag_gpio48: jtag_gpio48 {
 691                 pins-jtag {
 692                         pins = "gpio48",
 693                                "gpio49",
 694                                "gpio50",
 695                                "gpio51",
 696                                "gpio52",
 697                                "gpio53";
 698                         function = "alt4";
 699                 };
 700         };
 701
 702         mii_gpio28: mii_gpio28 {
 703                 pins-mii {
 704                         pins = "gpio28",
 705                                "gpio29",
 706                                "gpio30",
 707                                "gpio31";
 708                         function = "alt4";
 709                 };
 710         };
 711         mii_gpio36: mii_gpio36 {
 712                 pins-mii {
 713                         pins = "gpio36",
 714                                "gpio37",
 715                                "gpio38",
 716                                "gpio39";
 717                         function = "alt5";
 718                 };
 719         };
 720
 721         pcm_gpio50: pcm_gpio50 {
 722                 pins-pcm {
 723                         pins = "gpio50",
 724                                "gpio51",
 725                                "gpio52",
 726                                "gpio53";
 727                         function = "alt2";
 728                 };
 729         };
 730
 731         pwm0_0_gpio12: pwm0_0_gpio12 {
 732                 pin-pwm {
 733                         pins = "gpio12";
 734                         function = "alt0";
 735                         bias-disable;
 736                 };
 737         };
 738         pwm0_0_gpio18: pwm0_0_gpio18 {
 739                 pin-pwm {
 740                         pins = "gpio18";
 741                         function = "alt5";
 742                         bias-disable;
 743                 };
 744         };
 745         pwm1_0_gpio40: pwm1_0_gpio40 {
 746                 pin-pwm {
 747                         pins = "gpio40";
 748                         function = "alt0";
 749                         bias-disable;
 750                 };
 751         };
 752         pwm0_1_gpio13: pwm0_1_gpio13 {
 753                 pin-pwm {
 754                         pins = "gpio13";
 755                         function = "alt0";
 756                         bias-disable;
 757                 };
 758         };
 759         pwm0_1_gpio19: pwm0_1_gpio19 {
 760                 pin-pwm {
 761                         pins = "gpio19";
 762                         function = "alt5";
 763                         bias-disable;
 764                 };
 765         };
 766         pwm1_1_gpio41: pwm1_1_gpio41 {
 767                 pin-pwm {
 768                         pins = "gpio41";
 769                         function = "alt0";
 770                         bias-disable;
 771                 };
 772         };
 773         pwm0_1_gpio45: pwm0_1_gpio45 {
 774                 pin-pwm {
 775                         pins = "gpio45";
 776                         function = "alt0";
 777                         bias-disable;
 778                 };
 779         };
 780         pwm0_0_gpio52: pwm0_0_gpio52 {
 781                 pin-pwm {
 782                         pins = "gpio52";
 783                         function = "alt1";
 784                         bias-disable;
 785                 };
 786         };
 787         pwm0_1_gpio53: pwm0_1_gpio53 {
 788                 pin-pwm {
 789                         pins = "gpio53";
 790                         function = "alt1";
 791                         bias-disable;
 792                 };
 793         };
 794
 795         rgmii_gpio35: rgmii_gpio35 {
 796                 pin-start-stop {
 797                         pins = "gpio35";
 798                         function = "alt4";
 799                 };
 800                 pin-rx-ok {
 801                         pins = "gpio36";
 802                         function = "alt4";
 803                 };
 804         };
 805         rgmii_irq_gpio34: rgmii_irq_gpio34 {
 806                 pin-irq {
 807                         pins = "gpio34";
 808                         function = "alt5";
 809                 };
 810         };
 811         rgmii_irq_gpio39: rgmii_irq_gpio39 {
 812                 pin-irq {
 813                         pins = "gpio39";
 814                         function = "alt4";
 815                 };
 816         };
 817         rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
 818                 pins-mdio {
 819                         pins = "gpio28",
 820                                "gpio29";
 821                         function = "alt5";
 822                 };
 823         };
 824         rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
 825                 pins-mdio {
 826                         pins = "gpio37",
 827                                "gpio38";
 828                         function = "alt4";
 829                 };
 830         };
 831
 832         spi0_gpio46: spi0_gpio46 {
 833                 pins-spi {
 834                         pins = "gpio46",
 835                                "gpio47",
 836                                "gpio48",
 837                                "gpio49";
 838                         function = "alt2";
 839                 };
 840         };
 841         spi2_gpio46: spi2_gpio46 {
 842                 pins-spi {
 843                         pins = "gpio46",
 844                                "gpio47",
 845                                "gpio48",
 846                                "gpio49",
 847                                "gpio50";
 848                         function = "alt5";
 849                 };
 850         };
 851         spi3_gpio0: spi3_gpio0 {
 852                 pins-spi {
 853                         pins = "gpio0",
 854                                "gpio1",
 855                                "gpio2",
 856                                "gpio3";
 857                         function = "alt3";
 858                 };
 859         };
 860         spi4_gpio4: spi4_gpio4 {
 861                 pins-spi {
 862                         pins = "gpio4",
 863                                "gpio5",
 864                                "gpio6",
 865                                "gpio7";
 866                         function = "alt3";
 867                 };
 868         };
 869         spi5_gpio12: spi5_gpio12 {
 870                 pins-spi {
 871                         pins = "gpio12",
 872                                "gpio13",
 873                                "gpio14",
 874                                "gpio15";
 875                         function = "alt3";
 876                 };
 877         };
 878         spi6_gpio18: spi6_gpio18 {
 879                 pins-spi {
 880                         pins = "gpio18",
 881                                "gpio19",
 882                                "gpio20",
 883                                "gpio21";
 884                         function = "alt3";
 885                 };
 886         };
 887
 888         uart2_gpio0: uart2_gpio0 {
 889                 pin-tx {
 890                         pins = "gpio0";
 891                         function = "alt4";
 892                         bias-disable;
 893                 };
 894                 pin-rx {
 895                         pins = "gpio1";
 896                         function = "alt4";
 897                         bias-pull-up;
 898                 };
 899         };
 900         uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
 901                 pin-cts {
 902                         pins = "gpio2";
 903                         function = "alt4";
 904                         bias-pull-up;
 905                 };
 906                 pin-rts {
 907                         pins = "gpio3";
 908                         function = "alt4";
 909                         bias-disable;
 910                 };
 911         };
 912         uart3_gpio4: uart3_gpio4 {
 913                 pin-tx {
 914                         pins = "gpio4";
 915                         function = "alt4";
 916                         bias-disable;
 917                 };
 918                 pin-rx {
 919                         pins = "gpio5";
 920                         function = "alt4";
 921                         bias-pull-up;
 922                 };
 923         };
 924         uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
 925                 pin-cts {
 926                         pins = "gpio6";
 927                         function = "alt4";
 928                         bias-pull-up;
 929                 };
 930                 pin-rts {
 931                         pins = "gpio7";
 932                         function = "alt4";
 933                         bias-disable;
 934                 };
 935         };
 936         uart4_gpio8: uart4_gpio8 {
 937                 pin-tx {
 938                         pins = "gpio8";
 939                         function = "alt4";
 940                         bias-disable;
 941                 };
 942                 pin-rx {
 943                         pins = "gpio9";
 944                         function = "alt4";
 945                         bias-pull-up;
 946                 };
 947         };
 948         uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
 949                 pin-cts {
 950                         pins = "gpio10";
 951                         function = "alt4";
 952                         bias-pull-up;
 953                 };
 954                 pin-rts {
 955                         pins = "gpio11";
 956                         function = "alt4";
 957                         bias-disable;
 958                 };
 959         };
 960         uart5_gpio12: uart5_gpio12 {
 961                 pin-tx {
 962                         pins = "gpio12";
 963                         function = "alt4";
 964                         bias-disable;
 965                 };
 966                 pin-rx {
 967                         pins = "gpio13";
 968                         function = "alt4";
 969                         bias-pull-up;
 970                 };
 971         };
 972         uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
 973                 pin-cts {
 974                         pins = "gpio14";
 975                         function = "alt4";
 976                         bias-pull-up;
 977                 };
 978                 pin-rts {
 979                         pins = "gpio15";
 980                         function = "alt4";
 981                         bias-disable;
 982                 };
 983         };
 984 };
 985
 986 &rmem {
 987         #address-cells = <2>;
 988 };
 989
 990 &cma {
 991         /*
 992          * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
 993          * that's not good enough for the BCM2711 as some devices can
 994          * only address the lower 1G of memory (ZONE_DMA).
 995          */
 996         alloc-ranges = <0x0 0x00000000 0x40000000>;
 997 };
 998
 999 &i2c0if {
1000         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1001         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1002 };
1003
1004 &i2c1 {
1005         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1006         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1007 };
1008
1009 &mailbox {
1010         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1011 };
1012
1013 &sdhci {
1014         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1015 };
1016
1017 &sdhost {
1018         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1019 };
1020
1021 &spi {
1022         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1023 };
1024
1025 &spi1 {
1026         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1027 };
1028
1029 &spi2 {
1030         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1031 };
1032
1033 &system_timer {
1034         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1035                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1036                      <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1037                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1038 };
1039
1040 &txp {
1041         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1042 };
1043
1044 &uart0 {
1045         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1046 };
1047
1048 &uart1 {
1049         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1050 };
1051
1052 &usb {
1053         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1054 };
1055
1056 &vec {
1057         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1058 };