1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Broadcom Corporation
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
7 #include "dt-bindings/clock/bcm21664.h"
12 model = "BCM21664 SoC";
13 compatible = "brcm,bcm21664";
14 interrupt-parent = <&gic>;
17 bootargs = "console=ttyS0,115200n8";
26 compatible = "arm,cortex-a9";
32 compatible = "arm,cortex-a9";
33 enable-method = "brcm,bcm11351-cpu-method";
34 secondary-boot-reg = <0x35004178>;
39 gic: interrupt-controller@3ff00100 {
40 compatible = "arm,cortex-a9-gic";
41 #interrupt-cells = <3>;
44 reg = <0x3ff01000 0x1000>,
49 compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
50 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
54 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
56 reg = <0x3e000000 0x118>;
57 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
58 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
64 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
66 reg = <0x3e001000 0x118>;
67 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
68 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
74 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
76 reg = <0x3e002000 0x118>;
77 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
78 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
83 L2: cache-controller@3ff20000 {
84 compatible = "arm,pl310-cache";
85 reg = <0x3ff20000 0x1000>;
90 brcm,resetmgr@35001f00 {
91 compatible = "brcm,bcm21664-resetmgr";
92 reg = <0x35001f00 0x24>;
96 compatible = "brcm,kona-timer";
97 reg = <0x35006000 0x1c>;
98 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
102 gpio: gpio@35003000 {
103 compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
104 reg = <0x35003000 0x524>;
106 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
111 #interrupt-cells = <2>;
113 interrupt-controller;
116 sdio1: sdio@3f180000 {
117 compatible = "brcm,kona-sdhci";
118 reg = <0x3f180000 0x801c>;
119 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
124 sdio2: sdio@3f190000 {
125 compatible = "brcm,kona-sdhci";
126 reg = <0x3f190000 0x801c>;
127 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
132 sdio3: sdio@3f1a0000 {
133 compatible = "brcm,kona-sdhci";
134 reg = <0x3f1a0000 0x801c>;
135 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
140 sdio4: sdio@3f1b0000 {
141 compatible = "brcm,kona-sdhci";
142 reg = <0x3f1b0000 0x801c>;
143 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
149 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
150 reg = <0x3e016000 0x70>;
151 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
152 #address-cells = <1>;
154 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
159 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
160 reg = <0x3e017000 0x70>;
161 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
162 #address-cells = <1>;
164 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
169 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
170 reg = <0x3e018000 0x70>;
171 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
172 #address-cells = <1>;
174 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
179 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
180 reg = <0x3e01c000 0x70>;
181 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
182 #address-cells = <1>;
184 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
189 #address-cells = <1>;
194 * Fixed clocks are defined before CCUs whose
195 * clocks may depend on them.
198 ref_32k_clk: ref_32k {
200 compatible = "fixed-clock";
201 clock-frequency = <32768>;
204 bbl_32k_clk: bbl_32k {
206 compatible = "fixed-clock";
207 clock-frequency = <32768>;
210 ref_13m_clk: ref_13m {
212 compatible = "fixed-clock";
213 clock-frequency = <13000000>;
216 var_13m_clk: var_13m {
218 compatible = "fixed-clock";
219 clock-frequency = <13000000>;
222 dft_19_5m_clk: dft_19_5m {
224 compatible = "fixed-clock";
225 clock-frequency = <19500000>;
228 ref_crystal_clk: ref_crystal {
230 compatible = "fixed-clock";
231 clock-frequency = <26000000>;
234 ref_52m_clk: ref_52m {
236 compatible = "fixed-clock";
237 clock-frequency = <52000000>;
240 var_52m_clk: var_52m {
242 compatible = "fixed-clock";
243 clock-frequency = <52000000>;
246 usb_otg_ahb_clk: usb_otg_ahb {
248 compatible = "fixed-clock";
249 clock-frequency = <52000000>;
252 ref_96m_clk: ref_96m {
254 compatible = "fixed-clock";
255 clock-frequency = <96000000>;
258 var_96m_clk: var_96m {
260 compatible = "fixed-clock";
261 clock-frequency = <96000000>;
264 ref_104m_clk: ref_104m {
266 compatible = "fixed-clock";
267 clock-frequency = <104000000>;
270 var_104m_clk: var_104m {
272 compatible = "fixed-clock";
273 clock-frequency = <104000000>;
276 ref_156m_clk: ref_156m {
278 compatible = "fixed-clock";
279 clock-frequency = <156000000>;
282 var_156m_clk: var_156m {
284 compatible = "fixed-clock";
285 clock-frequency = <156000000>;
288 root_ccu: root_ccu@35001000 {
289 compatible = BCM21664_DT_ROOT_CCU_COMPAT;
290 reg = <0x35001000 0x0f00>;
292 clock-output-names = "frac_1m";
295 aon_ccu: aon_ccu@35002000 {
296 compatible = BCM21664_DT_AON_CCU_COMPAT;
297 reg = <0x35002000 0x0f00>;
299 clock-output-names = "hub_timer";
302 master_ccu: master_ccu@3f001000 {
303 compatible = BCM21664_DT_MASTER_CCU_COMPAT;
304 reg = <0x3f001000 0x0f00>;
306 clock-output-names = "sdio1",
316 slave_ccu: slave_ccu@3e011000 {
317 compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
318 reg = <0x3e011000 0x0f00>;
320 clock-output-names = "uartb",
330 usbotg: usb@3f120000 {
331 compatible = "snps,dwc2";
332 reg = <0x3f120000 0x10000>;
333 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&usb_otg_ahb_clk>;
337 phy-names = "usb2-phy";
341 usbphy: usb-phy@3f130000 {
342 compatible = "brcm,kona-usb2-phy";
343 reg = <0x3f130000 0x28>;