2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
24 #if defined(CONFIG_DEBUG_ICEDCC)
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
30 mcr p14, 0, \ch, c0, c5, 0
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
36 mcr p14, 0, \ch, c8, c0, 0
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c1, c0, 0
48 #include CONFIG_DEBUG_LL_INCLUDE
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
60 add \rb, \rb, #0x00010000 @ Ser1
63 #elif defined(CONFIG_ARCH_S3C24XX)
64 .macro loadsp, rb, tmp
66 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
69 .macro loadsp, rb, tmp
87 .macro debug_reloc_start
90 kphex r6, 8 /* processor id */
92 kphex r7, 8 /* architecture id */
93 #ifdef CONFIG_CPU_CP15
95 mrc p15, 0, r0, c1, c0
96 kphex r0, 8 /* control reg */
99 kphex r5, 8 /* decompressed kernel start */
101 kphex r9, 8 /* decompressed kernel end */
103 kphex r4, 8 /* kernel execution address */
108 .macro debug_reloc_end
110 kphex r5, 8 /* end of kernel */
113 bl memdump /* dump 256 bytes at start of kernel */
117 .section ".start", #alloc, #execinstr
119 * sort out different calling conventions
122 .arm @ Always enter in ARM state
124 .type start,#function
130 THUMB( adr r12, BSYM(1f) )
133 .word 0x016f2818 @ Magic numbers to help the loader
134 .word start @ absolute load/run zImage address
135 .word _edata @ zImage end address
138 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
140 #ifdef CONFIG_ARM_VIRT_EXT
141 bl __hyp_stub_install @ get into SVC mode, reversibly
143 mov r7, r1 @ save architecture ID
144 mov r8, r2 @ save atags pointer
147 * Booting from Angel - need to enter SVC mode and disable
148 * FIQs/IRQs (numeric definitions from angel arm.h source).
149 * We only do this if we were in user mode on entry.
151 mrs r2, cpsr @ get current mode
152 tst r2, #3 @ not user?
154 mov r0, #0x17 @ angel_SWIreason_EnterSVC
155 ARM( swi 0x123456 ) @ angel_SWI_ARM
156 THUMB( svc 0xab ) @ angel_SWI_THUMB
158 safe_svcmode_maskall r0
159 msr spsr_cxsf, r9 @ Save the CPU boot mode in
162 * Note that some cache flushing and other stuff may
163 * be needed here - is there an Angel SWI call for this?
167 * some architecture specific code can be inserted
168 * by the linker here, but it should preserve r7, r8, and r9.
173 #ifdef CONFIG_AUTO_ZRELADDR
174 @ determine final kernel image address
176 and r4, r4, #0xf8000000
177 add r4, r4, #TEXT_OFFSET
183 * Set up a page table only if it won't overwrite ourself.
184 * That means r4 < pc && r4 - 16k page directory > &_end.
185 * Given that r4 > &_end is most unfrequent, we add a rough
186 * additional 1MB of room for a possible appended DTB.
193 orrcc r4, r4, #1 @ remember we skipped cache_on
197 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
201 * We might be running at a different address. We need
202 * to fix up various pointers.
204 sub r0, r0, r1 @ calculate the delta offset
205 add r6, r6, r0 @ _edata
206 add r10, r10, r0 @ inflated kernel size location
209 * The kernel build system appends the size of the
210 * decompressed kernel at the end of the compressed data
211 * in little-endian form.
215 orr r9, r9, lr, lsl #8
218 orr r9, r9, lr, lsl #16
219 orr r9, r9, r10, lsl #24
221 #ifndef CONFIG_ZBOOT_ROM
222 /* malloc space is above the relocated stack (64k max) */
224 add r10, sp, #0x10000
227 * With ZBOOT_ROM the bss/stack is non relocatable,
228 * but someone could still run this code from RAM,
229 * in which case our reference is _edata.
234 mov r5, #0 @ init dtb size to 0
235 #ifdef CONFIG_ARM_APPENDED_DTB
240 * r4 = final kernel address (possibly with LSB set)
241 * r5 = appended dtb size (still unknown)
243 * r7 = architecture ID
244 * r8 = atags/device tree pointer
245 * r9 = size of decompressed image
246 * r10 = end of this image, including bss/stack/malloc space if non XIP
251 * if there are device trees (dtb) appended to zImage, advance r10 so that the
252 * dtb data will get relocated along with the kernel if necessary.
257 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
262 bne dtb_check_done @ not found
264 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
266 * OK... Let's do some funky business here.
267 * If we do have a DTB appended to zImage, and we do have
268 * an ATAG list around, we want the later to be translated
269 * and folded into the former here. To be on the safe side,
270 * let's temporarily move the stack away into the malloc
271 * area. No GOT fixup has occurred yet, but none of the
272 * code we're about to call uses any global variable.
275 stmfd sp!, {r0-r3, ip, lr}
282 * If returned value is 1, there is no ATAG at the location
283 * pointed by r8. Try the typical 0x100 offset from start
284 * of RAM and hope for the best.
287 sub r0, r4, #TEXT_OFFSET
294 ldmfd sp!, {r0-r3, ip, lr}
298 mov r8, r6 @ use the appended device tree
301 * Make sure that the DTB doesn't end up in the final
302 * kernel's .bss area. To do so, we adjust the decompressed
303 * kernel size to compensate if that .bss size is larger
304 * than the relocated code.
306 ldr r5, =_kernel_bss_size
307 adr r1, wont_overwrite
312 /* Get the dtb's size */
315 /* convert r5 (dtb size) to little endian */
316 eor r1, r5, r5, ror #16
317 bic r1, r1, #0x00ff0000
319 eor r5, r5, r1, lsr #8
322 /* preserve 64-bit alignment */
326 /* relocate some pointers past the appended dtb */
334 * Check to see if we will overwrite ourselves.
335 * r4 = final kernel address (possibly with LSB set)
336 * r9 = size of decompressed image
337 * r10 = end of this image, including bss/stack/malloc space if non XIP
339 * r4 - 16k page directory >= r10 -> OK
340 * r4 + image length <= address of wont_overwrite -> OK
341 * Note: the possible LSB in r4 is harmless here.
347 adr r9, wont_overwrite
352 * Relocate ourselves past the end of the decompressed kernel.
354 * r10 = end of the decompressed kernel
355 * Because we always copy ahead, we need to do it from the end and go
356 * backward in case the source and destination overlap.
359 * Bump to the next 256-byte boundary with the size of
360 * the relocation code added. This avoids overwriting
361 * ourself when the offset is small.
363 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
366 /* Get start of code we want to copy and align it down. */
370 /* Relocate the hyp vector base if necessary */
371 #ifdef CONFIG_ARM_VIRT_EXT
373 and r0, r0, #MODE_MASK
384 sub r9, r6, r5 @ size to copy
385 add r9, r9, #31 @ rounded up to a multiple
386 bic r9, r9, #31 @ ... of 32 bytes
390 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
392 stmdb r9!, {r0 - r3, r10 - r12, lr}
395 /* Preserve offset to relocated code. */
398 #ifndef CONFIG_ZBOOT_ROM
399 /* cache_clean_flush may use the stack, so relocate it */
405 adr r0, BSYM(restart)
411 * If delta is zero, we are running at the address we were linked at.
415 * r4 = kernel execution address (possibly with LSB set)
416 * r5 = appended dtb size (0 if not present)
417 * r7 = architecture ID
429 #ifndef CONFIG_ZBOOT_ROM
431 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
432 * we need to fix up pointers into the BSS region.
433 * Note that the stack pointer has already been fixed up.
439 * Relocate all entries in the GOT table.
440 * Bump bss entries to _edata + dtb size
442 1: ldr r1, [r11, #0] @ relocate entries in the GOT
443 add r1, r1, r0 @ This fixes up C references
444 cmp r1, r2 @ if entry >= bss_start &&
445 cmphs r3, r1 @ bss_end > entry
446 addhi r1, r1, r5 @ entry += dtb size
447 str r1, [r11], #4 @ next entry
451 /* bump our bss pointers too */
458 * Relocate entries in the GOT table. We only relocate
459 * the entries that are outside the (relocated) BSS region.
461 1: ldr r1, [r11, #0] @ relocate entries in the GOT
462 cmp r1, r2 @ entry < bss_start ||
463 cmphs r3, r1 @ _end < entry
464 addlo r1, r1, r0 @ table. This fixes up the
465 str r1, [r11], #4 @ C references.
470 not_relocated: mov r0, #0
471 1: str r0, [r2], #4 @ clear bss
479 * Did we skip the cache setup earlier?
480 * That is indicated by the LSB in r4.
488 * The C runtime environment should now be setup sufficiently.
489 * Set up some pointers, and start decompressing.
490 * r4 = kernel execution address
491 * r7 = architecture ID
495 mov r1, sp @ malloc space above stack
496 add r2, sp, #0x10000 @ 64k max
501 mov r1, r7 @ restore architecture number
502 mov r2, r8 @ restore atags pointer
504 #ifdef CONFIG_ARM_VIRT_EXT
505 mrs r0, spsr @ Get saved CPU boot mode
506 and r0, r0, #MODE_MASK
507 cmp r0, #HYP_MODE @ if not booted in HYP mode...
508 bne __enter_kernel @ boot kernel directly
510 adr r12, .L__hyp_reentry_vectors_offset
515 __HVC(0) @ otherwise bounce to hyp mode
517 b . @ should never be reached
520 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
528 .word __bss_start @ r2
531 .word input_data_end - 4 @ r10 (inflated size location)
532 .word _got_start @ r11
534 .word .L_user_stack_end @ sp
535 .word _end - restart + 16384 + 1024*1024
538 #ifdef CONFIG_ARCH_RPC
540 params: ldr r0, =0x10000100 @ params_phys for RPC
547 * Turn on the cache. We need to setup some page tables so that we
548 * can have both the I and D caches on.
550 * We place the page tables 16k down from the kernel execution address,
551 * and we hope that nothing else is using it. If we're using it, we
555 * r4 = kernel execution address
556 * r7 = architecture number
559 * r0, r1, r2, r3, r9, r10, r12 corrupted
560 * This routine must preserve:
564 cache_on: mov r3, #8 @ cache_on function
568 * Initialize the highest priority protection region, PR7
569 * to cover all 32bit address and cacheable and bufferable.
571 __armv4_mpu_cache_on:
572 mov r0, #0x3f @ 4G, the whole
573 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
574 mcr p15, 0, r0, c6, c7, 1
577 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
578 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
579 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
582 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
583 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
586 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
587 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
588 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
589 mrc p15, 0, r0, c1, c0, 0 @ read control reg
590 @ ...I .... ..D. WC.M
591 orr r0, r0, #0x002d @ .... .... ..1. 11.1
592 orr r0, r0, #0x1000 @ ...1 .... .... ....
594 mcr p15, 0, r0, c1, c0, 0 @ write control reg
597 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
598 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
601 __armv3_mpu_cache_on:
602 mov r0, #0x3f @ 4G, the whole
603 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
606 mcr p15, 0, r0, c2, c0, 0 @ cache on
607 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
610 mcr p15, 0, r0, c5, c0, 0 @ access permission
613 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
615 * ?? ARMv3 MMU does not allow reading the control register,
616 * does this really work on ARMv3 MPU?
618 mrc p15, 0, r0, c1, c0, 0 @ read control reg
619 @ .... .... .... WC.M
620 orr r0, r0, #0x000d @ .... .... .... 11.1
621 /* ?? this overwrites the value constructed above? */
623 mcr p15, 0, r0, c1, c0, 0 @ write control reg
625 /* ?? invalidate for the second time? */
626 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
629 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
635 __setup_mmu: sub r3, r4, #16384 @ Page directory size
636 bic r3, r3, #0xff @ Align the pointer
639 * Initialise the page tables, turning on the cacheable and bufferable
640 * bits for the RAM area only.
644 mov r9, r9, lsl #18 @ start of RAM
645 add r10, r9, #0x10000000 @ a reasonable RAM size
646 mov r1, #0x12 @ XN|U + section mapping
647 orr r1, r1, #3 << 10 @ AP=11
649 1: cmp r1, r9 @ if virt > start of RAM
650 cmphs r10, r1 @ && end of RAM > virt
651 bic r1, r1, #0x1c @ clear XN|U + C + B
652 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
653 orrhs r1, r1, r6 @ set RAM section settings
654 str r1, [r0], #4 @ 1:1 mapping
659 * If ever we are running from Flash, then we surely want the cache
660 * to be enabled also for our execution instance... We map 2MB of it
661 * so there is no map overlap problem for up to 1 MB compressed kernel.
662 * If the execution is in RAM then we would only be duplicating the above.
664 orr r1, r6, #0x04 @ ensure B is set for this
668 orr r1, r1, r2, lsl #20
669 add r0, r3, r2, lsl #2
676 @ Enable unaligned access on v6, to allow better code generation
677 @ for the decompressor C code:
678 __armv6_mmu_cache_on:
679 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
680 bic r0, r0, #2 @ A (no unaligned access fault)
681 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
682 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
683 b __armv4_mmu_cache_on
685 __arm926ejs_mmu_cache_on:
686 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
687 mov r0, #4 @ put dcache in WT mode
688 mcr p15, 7, r0, c15, c0, 0
691 __armv4_mmu_cache_on:
694 mov r6, #CB_BITS | 0x12 @ U
697 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
698 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
699 mrc p15, 0, r0, c1, c0, 0 @ read control reg
700 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
702 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
703 bl __common_mmu_cache_on
705 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
709 __armv7_mmu_cache_on:
712 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
714 movne r6, #CB_BITS | 0x02 @ !XN
717 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
719 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
721 mrc p15, 0, r0, c1, c0, 0 @ read control reg
722 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
723 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
724 orr r0, r0, #0x003c @ write buffer
725 bic r0, r0, #2 @ A (no unaligned access fault)
726 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
727 @ (needed for ARM1176)
729 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
730 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
731 orrne r0, r0, #1 @ MMU enabled
732 movne r1, #0xfffffffd @ domain 0 = client
733 bic r6, r6, #1 << 31 @ 32-bit translation system
734 bic r6, r6, #3 << 0 @ use only ttbr0
735 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
736 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
737 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
739 mcr p15, 0, r0, c7, c5, 4 @ ISB
740 mcr p15, 0, r0, c1, c0, 0 @ load control register
741 mrc p15, 0, r0, c1, c0, 0 @ and read it back
743 mcr p15, 0, r0, c7, c5, 4 @ ISB
748 mov r6, #CB_BITS | 0x12 @ U
751 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
752 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
753 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
754 mrc p15, 0, r0, c1, c0, 0 @ read control reg
755 orr r0, r0, #0x1000 @ I-cache enable
756 bl __common_mmu_cache_on
758 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
761 __common_mmu_cache_on:
762 #ifndef CONFIG_THUMB2_KERNEL
764 orr r0, r0, #0x000d @ Write buffer, mmu
767 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
768 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
770 .align 5 @ cache line aligned
771 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
772 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
773 sub pc, lr, r0, lsr #32 @ properly flush pipeline
776 #define PROC_ENTRY_SIZE (4*5)
779 * Here follow the relocatable cache support functions for the
780 * various processors. This is a generic hook for locating an
781 * entry and jumping to an instruction at the specified offset
782 * from the start of the block. Please note this is all position
792 call_cache_fn: adr r12, proc_types
793 #ifdef CONFIG_CPU_CP15
794 mrc p15, 0, r9, c0, c0 @ get processor ID
796 ldr r9, =CONFIG_PROCESSOR_ID
798 1: ldr r1, [r12, #0] @ get value
799 ldr r2, [r12, #4] @ get mask
800 eor r1, r1, r9 @ (real ^ match)
802 ARM( addeq pc, r12, r3 ) @ call cache function
803 THUMB( addeq r12, r3 )
804 THUMB( moveq pc, r12 ) @ call cache function
805 add r12, r12, #PROC_ENTRY_SIZE
809 * Table for cache operations. This is basically:
812 * - 'cache on' method instruction
813 * - 'cache off' method instruction
814 * - 'cache flush' method instruction
816 * We match an entry using: ((real_id ^ match) & mask) == 0
818 * Writethrough caches generally only need 'on' and 'off'
819 * methods. Writeback caches _must_ have the flush method
823 .type proc_types,#object
825 .word 0x41000000 @ old ARM ID
834 .word 0x41007000 @ ARM7/710
843 .word 0x41807200 @ ARM720T (writethrough)
845 W(b) __armv4_mmu_cache_on
846 W(b) __armv4_mmu_cache_off
850 .word 0x41007400 @ ARM74x
852 W(b) __armv3_mpu_cache_on
853 W(b) __armv3_mpu_cache_off
854 W(b) __armv3_mpu_cache_flush
856 .word 0x41009400 @ ARM94x
858 W(b) __armv4_mpu_cache_on
859 W(b) __armv4_mpu_cache_off
860 W(b) __armv4_mpu_cache_flush
862 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
864 W(b) __arm926ejs_mmu_cache_on
865 W(b) __armv4_mmu_cache_off
866 W(b) __armv5tej_mmu_cache_flush
868 .word 0x00007000 @ ARM7 IDs
877 @ Everything from here on will be the new ID system.
879 .word 0x4401a100 @ sa110 / sa1100
881 W(b) __armv4_mmu_cache_on
882 W(b) __armv4_mmu_cache_off
883 W(b) __armv4_mmu_cache_flush
885 .word 0x6901b110 @ sa1110
887 W(b) __armv4_mmu_cache_on
888 W(b) __armv4_mmu_cache_off
889 W(b) __armv4_mmu_cache_flush
892 .word 0xffffff00 @ PXA9xx
893 W(b) __armv4_mmu_cache_on
894 W(b) __armv4_mmu_cache_off
895 W(b) __armv4_mmu_cache_flush
897 .word 0x56158000 @ PXA168
899 W(b) __armv4_mmu_cache_on
900 W(b) __armv4_mmu_cache_off
901 W(b) __armv5tej_mmu_cache_flush
903 .word 0x56050000 @ Feroceon
905 W(b) __armv4_mmu_cache_on
906 W(b) __armv4_mmu_cache_off
907 W(b) __armv5tej_mmu_cache_flush
909 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
910 /* this conflicts with the standard ARMv5TE entry */
911 .long 0x41009260 @ Old Feroceon
913 b __armv4_mmu_cache_on
914 b __armv4_mmu_cache_off
915 b __armv5tej_mmu_cache_flush
918 .word 0x66015261 @ FA526
920 W(b) __fa526_cache_on
921 W(b) __armv4_mmu_cache_off
922 W(b) __fa526_cache_flush
924 @ These match on the architecture ID
926 .word 0x00020000 @ ARMv4T
928 W(b) __armv4_mmu_cache_on
929 W(b) __armv4_mmu_cache_off
930 W(b) __armv4_mmu_cache_flush
932 .word 0x00050000 @ ARMv5TE
934 W(b) __armv4_mmu_cache_on
935 W(b) __armv4_mmu_cache_off
936 W(b) __armv4_mmu_cache_flush
938 .word 0x00060000 @ ARMv5TEJ
940 W(b) __armv4_mmu_cache_on
941 W(b) __armv4_mmu_cache_off
942 W(b) __armv5tej_mmu_cache_flush
944 .word 0x0007b000 @ ARMv6
946 W(b) __armv6_mmu_cache_on
947 W(b) __armv4_mmu_cache_off
948 W(b) __armv6_mmu_cache_flush
950 .word 0x000f0000 @ new CPU Id
952 W(b) __armv7_mmu_cache_on
953 W(b) __armv7_mmu_cache_off
954 W(b) __armv7_mmu_cache_flush
956 .word 0 @ unrecognised type
965 .size proc_types, . - proc_types
968 * If you get a "non-constant expression in ".if" statement"
969 * error from the assembler on this line, check that you have
970 * not accidentally written a "b" instruction where you should
973 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
974 .error "The size of one or more proc_types entries is wrong."
978 * Turn off the Cache and MMU. ARMv3 does not support
979 * reading the control register, but ARMv4 does.
982 * r0, r1, r2, r3, r9, r12 corrupted
983 * This routine must preserve:
987 cache_off: mov r3, #12 @ cache_off function
990 __armv4_mpu_cache_off:
991 mrc p15, 0, r0, c1, c0
993 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
995 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
996 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
997 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1000 __armv3_mpu_cache_off:
1001 mrc p15, 0, r0, c1, c0
1003 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1005 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1008 __armv4_mmu_cache_off:
1010 mrc p15, 0, r0, c1, c0
1012 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1014 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1015 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1019 __armv7_mmu_cache_off:
1020 mrc p15, 0, r0, c1, c0
1026 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1028 bl __armv7_mmu_cache_flush
1031 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1033 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1034 mcr p15, 0, r0, c7, c10, 4 @ DSB
1035 mcr p15, 0, r0, c7, c5, 4 @ ISB
1039 * Clean and flush the cache to maintain consistency.
1042 * r1, r2, r3, r9, r10, r11, r12 corrupted
1043 * This routine must preserve:
1051 __armv4_mpu_cache_flush:
1056 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1057 mov r1, #7 << 5 @ 8 segments
1058 1: orr r3, r1, #63 << 26 @ 64 entries
1059 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1060 subs r3, r3, #1 << 26
1061 bcs 2b @ entries 63 to 0
1062 subs r1, r1, #1 << 5
1063 bcs 1b @ segments 7 to 0
1066 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1067 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1070 __fa526_cache_flush:
1074 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1075 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1076 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1079 __armv6_mmu_cache_flush:
1082 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1083 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1084 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1085 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1088 __armv7_mmu_cache_flush:
1091 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1092 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1095 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1098 mcr p15, 0, r10, c7, c10, 5 @ DMB
1099 stmfd sp!, {r0-r7, r9-r11}
1100 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1101 ands r3, r0, #0x7000000 @ extract loc from clidr
1102 mov r3, r3, lsr #23 @ left align loc bit field
1103 beq finished @ if loc is 0, then no need to clean
1104 mov r10, #0 @ start clean at cache level 0
1106 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1107 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1108 and r1, r1, #7 @ mask of the bits for current cache only
1109 cmp r1, #2 @ see what cache we have at this level
1110 blt skip @ skip if no cache, or just i-cache
1111 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1112 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1113 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1114 and r2, r1, #7 @ extract the length of the cache lines
1115 add r2, r2, #4 @ add 4 (line length offset)
1117 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1118 clz r5, r4 @ find bit position of way size increment
1120 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1122 mov r9, r4 @ create working copy of max way size
1124 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1125 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1126 THUMB( lsl r6, r9, r5 )
1127 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1128 THUMB( lsl r6, r7, r2 )
1129 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1130 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1131 subs r9, r9, #1 @ decrement the way
1133 subs r7, r7, #1 @ decrement the index
1136 add r10, r10, #2 @ increment cache number
1140 ldmfd sp!, {r0-r7, r9-r11}
1141 mov r10, #0 @ swith back to cache level 0
1142 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1144 mcr p15, 0, r10, c7, c10, 4 @ DSB
1145 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1146 mcr p15, 0, r10, c7, c10, 4 @ DSB
1147 mcr p15, 0, r10, c7, c5, 4 @ ISB
1150 __armv5tej_mmu_cache_flush:
1153 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1155 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1156 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1159 __armv4_mmu_cache_flush:
1162 mov r2, #64*1024 @ default: 32K dcache size (*2)
1163 mov r11, #32 @ default: 32 byte line size
1164 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1165 teq r3, r9 @ cache ID register present?
1170 mov r2, r2, lsl r1 @ base dcache size *2
1171 tst r3, #1 << 14 @ test M bit
1172 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1176 mov r11, r11, lsl r3 @ cache line size in bytes
1179 bic r1, r1, #63 @ align to longest cache line
1182 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1183 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1184 THUMB( add r1, r1, r11 )
1188 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1189 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1190 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1193 __armv3_mmu_cache_flush:
1194 __armv3_mpu_cache_flush:
1198 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1202 * Various debugging routines for printing hex characters and
1203 * memory, which again must be relocatable.
1207 .type phexbuf,#object
1209 .size phexbuf, . - phexbuf
1211 @ phex corrupts {r0, r1, r2, r3}
1212 phex: adr r3, phexbuf
1226 @ puts corrupts {r0, r1, r2, r3}
1228 1: ldrb r2, [r0], #1
1241 @ putc corrupts {r0, r1, r2, r3}
1248 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1249 memdump: mov r12, r0
1252 2: mov r0, r11, lsl #2
1260 ldr r0, [r12, r11, lsl #2]
1280 #ifdef CONFIG_ARM_VIRT_EXT
1282 __hyp_reentry_vectors:
1288 W(b) __enter_kernel @ hyp
1291 #endif /* CONFIG_ARM_VIRT_EXT */
1294 mov r0, #0 @ must be 0
1295 ARM( mov pc, r4 ) @ call kernel
1296 THUMB( bx r4 ) @ entry point is always ARM
1301 .section ".stack", "aw", %nobits
1302 .L_user_stack: .space 4096